From: Mark Marshall <Mark.Marshall@omicron.at>
Date: Tue, 24 Jan 2017 14:40:23 +0000 (+0100)
Subject: powerpc: mpc85xx: Use symbolic names for cache control bits
X-Git-Tag: v2025.01-rc5-pxa1908~7590^2~1
X-Git-Url: http://git.dujemihanovic.xyz/html/%7B%7B%20%24image.RelPermalink%20%7D%7D?a=commitdiff_plain;h=2ec70961e7dc6548451822857aca5dc2573cee55;p=u-boot.git

powerpc: mpc85xx: Use symbolic names for cache control bits

We should use the symbolic names for the cache control bits.

Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
Reviewed-by: Thomas Graziadei <thomas.graziadei@omicronenergy.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 932216c237..eb817f1e86 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1373,8 +1373,8 @@ icache_enable:
 	mtlr	r8
 	isync
 	mfspr	r4,L1CSR1
-	ori	r4,r4,0x0001
-	oris	r4,r4,0x0001
+	ori	r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l
+	oris	r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h
 	mtspr	L1CSR1,r4
 	isync
 	blr
@@ -1402,8 +1402,8 @@ dcache_enable:
 	mtlr	r8
 	isync
 	mfspr	r0,L1CSR0
-	ori	r0,r0,0x0001
-	oris	r0,r0,0x0001
+	ori	r0,r0,(L1CSR0_CPE |  L1CSR0_DCE)@l
+	oris	r0,r0,(L1CSR0_CPE |  L1CSR0_DCE)@h
 	msync
 	isync
 	mtspr	L1CSR0,r0