From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Mon, 9 Sep 2024 23:18:09 +0000 (+0200)
Subject: sh: cache: Fill in invalidate_icache_all()
X-Git-Url: http://git.dujemihanovic.xyz/html/%7B%7B%20%24image.RelPermalink%20%7D%7D?a=commitdiff_plain;h=0034edc2f49faa3d773536b8f01f1e4cf8fca2a9;p=u-boot.git

sh: cache: Fill in invalidate_icache_all()

Implement invalidate_icache_all() by clearing all V bits in
IC and OC. This is done by setting CCR cache control register
ICI and OCI bits.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: u-boot@lists.denx.de
---

diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c
index d3c480e79e..99acc59996 100644
--- a/arch/sh/cpu/sh4/cache.c
+++ b/arch/sh/cpu/sh4/cache.c
@@ -33,8 +33,9 @@ static inline void cache_wback_all(void)
 	}
 }
 
-#define CACHE_ENABLE      0
-#define CACHE_DISABLE     1
+#define CACHE_ENABLE		0
+#define CACHE_DISABLE		1
+#define CACHE_INVALIDATE	2
 
 static int cache_control(unsigned int cmd)
 {
@@ -46,7 +47,9 @@ static int cache_control(unsigned int cmd)
 	if (ccr & CCR_CACHE_ENABLE)
 		cache_wback_all();
 
-	if (cmd == CACHE_DISABLE)
+	if (cmd == CACHE_INVALIDATE)
+		outl(CCR_CACHE_ICI | ccr, CCR);
+	else if (cmd == CACHE_DISABLE)
 		outl(CCR_CACHE_STOP, CCR);
 	else
 		outl(CCR_CACHE_INIT, CCR);
@@ -103,7 +106,7 @@ void icache_disable(void)
 
 void invalidate_icache_all(void)
 {
-	puts("No arch specific invalidate_icache_all available!\n");
+	cache_control(CACHE_INVALIDATE);
 }
 
 int icache_status(void)