From b5e9b296251f138ef9f9cfc15f408710a24831cd Mon Sep 17 00:00:00 2001 From: Marek Vasut <marex@denx.de> Date: Mon, 15 Sep 2014 01:45:14 +0200 Subject: [PATCH] arm: socfpga: cache: Enable PL310 L2 cache Enable the PL310 L2 cache controller support for the SoCFPGA. With the cache related issues resolved, this is safe to be done. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> --- include/configs/socfpga_cyclone5.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index de60bb2f06..c8986d9811 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -27,6 +27,8 @@ #define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -- 2.39.5