From: Han Xu <han.xu@nxp.com>
Date: Sat, 5 Oct 2024 23:46:20 +0000 (+0800)
Subject: mtd: spi-nor: Add mt35xu01gbba octal mode SPI NOR flash
X-Git-Tag: v2025.01-rc5-pxa1908~213^2
X-Git-Url: http://git.dujemihanovic.xyz/browse.php?a=commitdiff_plain;h=a3384940edf3cf2d2e0e0b78af9541f8be3a15ec;p=u-boot.git

mtd: spi-nor: Add mt35xu01gbba octal mode SPI NOR flash

Add SPI NOR flash id for mt35xu01gbba which supports 4 bytes address with
octal mode read.

Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
---

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 10654d5dc6..91ae49c948 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -358,6 +358,7 @@ const struct flash_info spi_nor_ids[] = {
 #ifdef CONFIG_SPI_FLASH_MT35XU
 	{ INFO("mt35xl512aba", 0x2c5a1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
 	{ INFO("mt35xu512aba", 0x2c5b1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
+	{ INFO("mt35xu01gaba", 0x2c5b1b, 0,  128 * 1024,  1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
 #endif /* CONFIG_SPI_FLASH_MT35XU */
 	{ INFO6("mt35xu01g",  0x2c5b1b, 0x104100, 128 * 1024,  1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("mt35xu02g",  0x2c5b1c, 0, 128 * 1024,  2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },