drop coreprimevelte.c, move its stuff to mach-mmp

diff --git a/arch/arm/mach-mmp/board.c b/arch/arm/mach-mmp/board.c
index 21059444c437d188bd1d31e74238730e76dc8c71..5115dafc148fdbe0807a1c7aca0cc4b79c9e5774 100644 (file)
--- a/arch/arm/mach-mmp/board.c
+++ b/arch/arm/mach-mmp/board.c
@@ -1,8 +1,51 @@
 #include <init.h>
 #include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Timer constants */
+#define APBC_COUNTER_CLK_SEL   0xd4015064
+#define COUNTER_BASE           0xd4101000
+#define COUNTER_EN             BIT(0)
+#define COUNTER_HALT_ON_DEBUG  BIT(1)
+
+int timer_init(void)
+{
+       u32 tmp = readl(APBC_COUNTER_CLK_SEL);
+
+       if ((tmp >> 16) != 0x319)
+               return -1;
+
+       /* Set timer frequency to 26MHz */
+       writel(tmp | 1, APBC_COUNTER_CLK_SEL);
+       writel(COUNTER_EN | COUNTER_HALT_ON_DEBUG, COUNTER_BASE);
+
+       gd->arch.timer_rate_hz = 26000000;
+
+       return 0;
+}
+
+int board_init(void)
+{
+       return 0;
+}
+
+int dram_init(void)
+{
+       if (fdtdec_setup_mem_size_base() != 0)
+               puts("fdtdec_setup_mem_size_base() has failed\n");
+
+       return 0;
+}
+
+#ifndef CONFIG_SYSRESET
+void reset_cpu(void)
+{
+}
+#endif
+
 /* Stolen from arch/arm/mach-snapdragon/board.c */
 void *board_fdt_blob_setup(int *err)
 {

diff --git a/board/samsung/coreprimevelte/Makefile b/board/samsung/coreprimevelte/Makefile
deleted file mode 100644 (file)
index 9fb9822..0000000
--- a/board/samsung/coreprimevelte/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += coreprimevelte.o

diff --git a/board/samsung/coreprimevelte/coreprimevelte.c b/board/samsung/coreprimevelte/coreprimevelte.c
deleted file mode 100644 (file)
index 170566d..0000000
--- a/board/samsung/coreprimevelte/coreprimevelte.c
+++ /dev/null
@@ -1,46 +0,0 @@
-#include <fdtdec.h>
-#include <asm/io.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Timer constants */
-#define APBC_COUNTER_CLK_SEL   0xd4015064
-#define COUNTER_BASE           0xd4101000
-#define COUNTER_EN             BIT(0)
-#define COUNTER_HALT_ON_DEBUG  BIT(1)
-
-int timer_init(void)
-{
-       u32 tmp = readl(APBC_COUNTER_CLK_SEL);
-
-       if ((tmp >> 16) != 0x319)
-               return -1;
-
-       /* Set timer frequency to 26MHz */
-       writel(tmp | 1, APBC_COUNTER_CLK_SEL);
-       writel(COUNTER_EN | COUNTER_HALT_ON_DEBUG, COUNTER_BASE);
-
-       gd->arch.timer_rate_hz = 26000000;
-
-       return 0;
-}
-
-int board_init(void)
-{
-       return 0;
-}
-
-int dram_init(void)
-{
-       if (fdtdec_setup_mem_size_base() != 0)
-               puts("fdtdec_setup_mem_size_base() has failed\n");
-
-       return 0;
-}
-
-#ifndef CONFIG_SYSRESET
-void reset_cpu(void)
-{
-}
-#endif