From fd3dc72945474ca3665cd76c96350f7c0e7d95cf Mon Sep 17 00:00:00 2001 From: =?utf8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Apr 2022 14:39:57 +0200 Subject: [PATCH] powerpc: dts: p2020: Define L2 cache node MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Copy definition of L2 cache node from upstream Linux kernel P2020 dts files. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 8 ++++++++ arch/powerpc/dts/p2020.dtsi | 2 ++ 2 files changed, 10 insertions(+) diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 0a296cffe5..1c3f78798e 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -56,6 +56,14 @@ /include/ "pq3-duart-0.dtsi" /include/ "pq3-gpio-0.dtsi" + L2: l2-cache-controller@20000 { + compatible = "fsl,p2020-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; /* 32 bytes */ + cache-size = <0x80000>; /* L2,512K */ + interrupts = <16 2 0 0>; + }; + /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-timer-0.dtsi" diff --git a/arch/powerpc/dts/p2020.dtsi b/arch/powerpc/dts/p2020.dtsi index 7c4c2061d4..7fdcb85c80 100644 --- a/arch/powerpc/dts/p2020.dtsi +++ b/arch/powerpc/dts/p2020.dtsi @@ -22,10 +22,12 @@ cpu0: PowerPC,P2020@0 { device_type = "cpu"; reg = <0>; + next-level-cache = <&L2>; }; cpu1: PowerPC,P2020@1 { device_type = "cpu"; reg = <1>; + next-level-cache = <&L2>; }; }; }; -- 2.39.5