From f6689614856b7eb9099dbbe21c8880ffbd80514e Mon Sep 17 00:00:00 2001 From: Harini Katakam Date: Mon, 10 Jul 2023 14:37:30 +0200 Subject: [PATCH] arm64: zynqmp: Assign TSU clock frequency for KR260 Set TSU clock frequency as 250MHz (minimum when running at 1G) on KR260 CC to allow PTP functionality. Signed-off-by: Harini Katakam Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d065b5c2c6450910bf57d104d65946111493caaa.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 ++ arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 ++ 3 files changed, 8 insertions(+) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 4d44924f66..a21dca87d2 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -169,24 +169,28 @@ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gpio { diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts index 5ac66bc1ec..caaf71d729 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -188,6 +188,7 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; + assigned-clock-rates = <250000000>; }; &gem1 { /* mdio mio50/51, gem mio38 - mio49 */ @@ -196,6 +197,7 @@ pinctrl-0 = <&pinctrl_gem1_default>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts index 401de9efb9..f9d87559a7 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -188,6 +188,7 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; + assigned-clock-rates = <250000000>; }; &gem1 { /* mdio mio50/51, gem mio38 - mio49 */ @@ -196,6 +197,7 @@ pinctrl-0 = <&pinctrl_gem1_default>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; -- 2.39.5