From e967c84a6d211562ff800a00b0c30d7aa808ae4b Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Beh=C3=BAn?= Date: Thu, 11 Nov 2021 16:35:44 +0100 Subject: [PATCH] pci: pci_mvebu, pci_aardvark: Fix size of configuration cache MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Since u32 takes up 4 bytes, we need to divide the number of u32s by 4 for cfgcache. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- drivers/pci/pci-aardvark.c | 2 +- drivers/pci/pci_mvebu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 4e94b776c5..8abbc3ffe8 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -202,7 +202,7 @@ struct pcie_advk { int sec_busno; struct udevice *dev; struct gpio_desc reset_gpio; - u32 cfgcache[0x34 - 0x10]; + u32 cfgcache[(0x34 - 0x10) / 4]; bool cfgcrssve; }; diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 14cd82db6f..2d1624deb2 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -88,7 +88,7 @@ struct mvebu_pcie { unsigned int mem_attr; unsigned int io_target; unsigned int io_attr; - u32 cfgcache[0x34 - 0x10]; + u32 cfgcache[(0x34 - 0x10) / 4]; }; /* -- 2.39.5