From d396f1384ce89ecd26b5784a4644b789198e0f8b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 4 Nov 2019 09:44:34 -0300 Subject: [PATCH] mx6: Allow configuring the NoC registers on i.MX6QP The NoC registers on i.MX6QP needs to be configured, otherwise some usecases in the kernel behave incorrectly, such as rotation and resize. Currently the NoC registers are not configured in the kernel, so configure them in U-Boot like it is done in the NXP U-Boot tree. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan Reviewed-by: Stefano Babic --- arch/arm/mach-imx/mx6/soc.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 926718b49c..4d62197b15 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -375,6 +375,37 @@ static void init_bandgap(void) } } +#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL) +static void noc_setup(void) +{ + enable_ipu_clock(); + + writel(0x80000201, 0xbb0608); + /* Bypass IPU1 QoS generator */ + writel(0x00000002, 0x00bb048c); + /* Bypass IPU2 QoS generator */ + writel(0x00000002, 0x00bb050c); + /* Bandwidth THR for of PRE0 */ + writel(0x00000200, 0x00bb0690); + /* Bandwidth THR for of PRE1 */ + writel(0x00000200, 0x00bb0710); + /* Bandwidth THR for of PRE2 */ + writel(0x00000200, 0x00bb0790); + /* Bandwidth THR for of PRE3 */ + writel(0x00000200, 0x00bb0810); + /* Saturation THR for of PRE0 */ + writel(0x00000010, 0x00bb0694); + /* Saturation THR for of PRE1 */ + writel(0x00000010, 0x00bb0714); + /* Saturation THR for of PRE2 */ + writel(0x00000010, 0x00bb0794); + /* Saturation THR for of PRE */ + writel(0x00000010, 0x00bb0814); + + disable_ipu_clock(); +} +#endif + int arch_cpu_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -452,6 +483,10 @@ int arch_cpu_init(void) init_src(); +#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL) + if (is_mx6dqp()) + noc_setup(); +#endif return 0; } -- 2.39.5