From bd6eb5ddd715e7441d804c67f434418e172a1423 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sat, 11 Nov 2023 11:46:18 +0100 Subject: [PATCH] clk: stm32f: fix setting of division factor for LCD_CLK The value to be written to the register must be appropriately shifted, as is correctly done in other parts of the code. Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock") Signed-off-by: Dario Binacchi Reviewed-by: Patrice Chotard --- drivers/clk/stm32/clk-stm32f.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index ed7660196e..4c18641933 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -530,7 +530,8 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate) /* set pll_saidivr with found value */ clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK, - pllsaidivr_table[i]); + pllsaidivr_table[i] << + RCC_DCKCFGR_PLLSAIDIVR_SHIFT); return rate; } -- 2.39.5