From b33953b796ccaafdff903455860b86659c3f44f3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:32 -0500 Subject: [PATCH] global: Migrate CONFIG_PME_PLAT_CLK_DIV to CFG Perform a simple rename of CONFIG_PME_PLAT_CLK_DIV to CFG_PME_PLAT_CLK_DIV Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/speed.c | 6 +++--- arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index eec071022e..c2e3e00f7b 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -67,7 +67,7 @@ void get_sys_info(sys_info_t *sys_info) [14] = 4, /* CC4 PPL / 4 */ }; uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; -#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CFG_PME_PLAT_CLK_DIV) uint rcw_tmp; #endif uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; @@ -206,7 +206,7 @@ void get_sys_info(sys_info_t *sys_info) #define FM1_CLK_SEL 0x1c000000 #define FM1_CLK_SHIFT 26 #endif -#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CFG_PME_PLAT_CLK_DIV) #if defined(CONFIG_ARCH_T1024) rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; #else @@ -215,7 +215,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_SYS_DPAA_PME -#ifndef CONFIG_PME_PLAT_CLK_DIV +#ifndef CFG_PME_PLAT_CLK_DIV switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { case 1: sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK]; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 283181ec2d..fc584895ee 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -144,8 +144,8 @@ #define CONFIG_SYS_FSL_SRDS_1 #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_PME_PLAT_CLK_DIV 2 -#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CFG_PME_PLAT_CLK_DIV 2 +#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CFG_FM_PLAT_CLK_DIV 1 #define CFG_SYS_FM1_CLK CFG_FM_PLAT_CLK_DIV @@ -182,8 +182,8 @@ #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #endif -#define CONFIG_PME_PLAT_CLK_DIV 1 -#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CFG_PME_PLAT_CLK_DIV 1 +#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV #define CFG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CFG_SYS_FM_MURAM_SIZE 0x28000 -- 2.39.5