From b0c5e37d0e8aaaadec6298fc7932797b1eb38d9c Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Thu, 28 Nov 2019 15:27:50 +0100 Subject: [PATCH] rockchip: px30: Fixup PMUGRF registers layout order According to the PX30 TRM, the iomux registers come first, before the pull and strength control registers. Signed-off-by: Paul Kocialkowski Reviewed-by: Kever Yang Reviewed-by: Heiko Stuebner --- arch/arm/include/asm/arch-rockchip/grf_px30.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/grf_px30.h b/arch/arm/include/asm/arch-rockchip/grf_px30.h index c167bb42fa..3d2a877032 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_px30.h +++ b/arch/arm/include/asm/arch-rockchip/grf_px30.h @@ -112,18 +112,18 @@ struct px30_grf { check_member(px30_grf, mac_con1, 0x904); struct px30_pmugrf { - unsigned int gpio0a_e; - unsigned int gpio0b_e; - unsigned int gpio0c_e; - unsigned int gpio0d_e; - unsigned int gpio0a_p; - unsigned int gpio0b_p; - unsigned int gpio0c_p; - unsigned int gpio0d_p; unsigned int gpio0al_iomux; unsigned int gpio0bl_iomux; unsigned int gpio0cl_iomux; unsigned int gpio0dl_iomux; + unsigned int gpio0a_p; + unsigned int gpio0b_p; + unsigned int gpio0c_p; + unsigned int gpio0d_p; + unsigned int gpio0a_e; + unsigned int gpio0b_e; + unsigned int gpio0c_e; + unsigned int gpio0d_e; unsigned int gpio0l_sr; unsigned int gpio0h_sr; unsigned int gpio0l_smt; -- 2.39.5