From afe18f205e269682edd680cb4a5bcbe2094ea58b Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Tue, 26 Nov 2019 21:15:39 +0800 Subject: [PATCH] rockchip: px5: enable spl-fifo-mode for emmc for px5-evb We need load some parts of ATF to sram, but rockchip dwmmc controllers can't do dma to non-ddr addresses space, so set the mmc controller into fifo mode in spl. Signed-off-by: Andy Yan Reviewed-by: Philipp Tomsich Reviewed-by: Kever Yang --- arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi index 002767a033..936ce55727 100644 --- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi @@ -58,6 +58,8 @@ }; &emmc { + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; u-boot,dm-pre-reloc; }; -- 2.39.5