From a8436a01a833d23bc1a48a8c183bdb590bb416fe Mon Sep 17 00:00:00 2001
From: =?utf8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
Date: Thu, 23 Jun 2022 14:39:03 +0200
Subject: [PATCH] powerpc: dts: p2020: Sort DT nodes by their addresses
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

No functional change.

Signed-off-by: Pali Rohár <pali@kernel.org>
---
 arch/powerpc/dts/p2020-post.dtsi | 89 ++++++++++++++++----------------
 1 file changed, 45 insertions(+), 44 deletions(-)

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 0d0cd2273c..3351874b53 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -13,49 +13,6 @@
 	compatible = "fsl,p2020-immr", "simple-bus";
 	bus-frequency = <0x0>;
 
-	usb@22000 {
-		compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
-		reg = <0x22000 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <28 0x2 0 0>;
-		phy_type = "ulpi";
-	};
-
-	mpic: pic@40000 {
-		interrupt-controller;
-		#address-cells = <0>;
-		#interrupt-cells = <4>;
-		reg = <0x40000 0x40000>;
-		compatible = "fsl,mpic";
-		device_type = "open-pic";
-		big-endian;
-		single-cpu-affinity;
-		last-interrupt-source = <255>;
-	};
-
-	esdhc: sdhc@2e000 {
-		compatible = "fsl,p2020-esdhc", "fsl,esdhc";
-		reg = <0x2e000 0x1000>;
-		interrupts = <72 0x2 0 0>;
-		/* Filled in by U-Boot */
-		clock-frequency = <0>;
-	};
-
-	espi0: spi@7000 {
-		compatible = "fsl,mpc8536-espi";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x7000 0x1000>;
-		interrupts = < 0x3b 0x02 0x00 0x00 >;
-		fsl,espi-num-chipselects = <4>;
-	};
-
-/include/ "pq3-i2c-0.dtsi"
-/include/ "pq3-i2c-1.dtsi"
-/include/ "pq3-duart-0.dtsi"
-/include/ "pq3-gpio-0.dtsi"
-
 	ecm-law@0 {
 		compatible = "fsl,ecm-law";
 		reg = <0x0 0x1000>;
@@ -74,6 +31,22 @@
 		interrupts = <18 2 0 0>;
 	};
 
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+
+	espi0: spi@7000 {
+		compatible = "fsl,mpc8536-espi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x7000 0x1000>;
+		interrupts = < 0x3b 0x02 0x00 0x00 >;
+		fsl,espi-num-chipselects = <4>;
+	};
+
+/include/ "pq3-dma-1.dtsi"
+/include/ "pq3-gpio-0.dtsi"
+
 	L2: l2-cache-controller@20000 {
 		compatible = "fsl,p2020-l2-cache-controller";
 		reg = <0x20000 0x1000>;
@@ -83,7 +56,15 @@
 	};
 
 /include/ "pq3-dma-0.dtsi"
-/include/ "pq3-dma-1.dtsi"
+
+	usb@22000 {
+		compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
+		reg = <0x22000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <28 0x2 0 0>;
+		phy_type = "ulpi";
+	};
 
 /include/ "pq3-etsec1-0.dtsi"
 /include/ "pq3-etsec1-timer-0.dtsi"
@@ -95,10 +76,30 @@
 /include/ "pq3-etsec1-1.dtsi"
 /include/ "pq3-etsec1-2.dtsi"
 
+	esdhc: sdhc@2e000 {
+		compatible = "fsl,p2020-esdhc", "fsl,esdhc";
+		reg = <0x2e000 0x1000>;
+		interrupts = <72 0x2 0 0>;
+		/* Filled in by U-Boot */
+		clock-frequency = <0>;
+	};
+
 /include/ "pq3-sec3.1-0.dtsi"
 /include/ "pq3-mpic.dtsi"
 /include/ "pq3-mpic-timer-B.dtsi"
 
+	mpic: pic@40000 {
+		interrupt-controller;
+		#address-cells = <0>;
+		#interrupt-cells = <4>;
+		reg = <0x40000 0x40000>;
+		compatible = "fsl,mpic";
+		device_type = "open-pic";
+		big-endian;
+		single-cpu-affinity;
+		last-interrupt-source = <255>;
+	};
+
 	global-utilities@e0000 {
 		compatible = "fsl,p2020-guts";
 		reg = <0xe0000 0x1000>;
-- 
2.39.5