From 98cacab76542dba7fa7d42e32fc848d89d88d55a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Feb 2022 15:52:02 +0100 Subject: [PATCH] video: Add skeleton driver for ZynqMP Display port driver The reason for this driver is to use call power management driver to enable it in PMUFW. There is missing functionality now but should be added in near future. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/598cb9515bbabc803f72e287464e3d107cd106a3.1645627920.git.michal.simek@xilinx.com --- drivers/video/Kconfig | 8 +++++ drivers/video/Makefile | 1 + drivers/video/zynqmp_dpsub.c | 66 ++++++++++++++++++++++++++++++++++++ 3 files changed, 75 insertions(+) create mode 100644 drivers/video/zynqmp_dpsub.c diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index ff8e11f648..646fec7026 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -680,6 +680,14 @@ config VIDEO_SEPS525 Enable support for the Syncoam PM-OLED display driver (RGB 160x128). Currently driver is supporting only SPI interface. +config VIDEO_ZYNQMP_DPSUB + bool "Enable video support for ZynqMP Display Port" + depends on DM_VIDEO && ZYNQMP_POWER_DOMAIN + help + Enable support for Xilinx ZynqMP Display Port. Currently this file + is used as placeholder for driver. The main reason is to record + compatible string and calling power domain driver. + source "drivers/video/nexell/Kconfig" config VIDEO diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 4038395b12..2530791eb4 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -74,6 +74,7 @@ obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o obj-$(CONFIG_VIDEO_VESA) += vesa.o obj-$(CONFIG_VIDEO_SEPS525) += seps525.o +obj-$(CONFIG_VIDEO_ZYNQMP_DPSUB) += zynqmp_dpsub.o obj-y += bridge/ obj-y += sunxi/ diff --git a/drivers/video/zynqmp_dpsub.c b/drivers/video/zynqmp_dpsub.c new file mode 100644 index 0000000000..4ead663cd5 --- /dev/null +++ b/drivers/video/zynqmp_dpsub.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Xilinx Inc. + */ + +#include +#include +#include +#include +#include +#include + +#define WIDTH 640 +#define HEIGHT 480 + +/** + * struct zynqmp_dpsub_priv - Private structure + * @dev: Device uclass for video_ops + */ +struct zynqmp_dpsub_priv { + struct udevice *dev; +}; + +static int zynqmp_dpsub_probe(struct udevice *dev) +{ + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct zynqmp_dpsub_priv *priv = dev_get_priv(dev); + + uc_priv->bpix = VIDEO_BPP16; + uc_priv->xsize = WIDTH; + uc_priv->ysize = HEIGHT; + uc_priv->rot = 0; + + priv->dev = dev; + + /* Only placeholder for power domain driver */ + return 0; +} + +static int zynqmp_dpsub_bind(struct udevice *dev) +{ + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + + plat->size = WIDTH * HEIGHT * 16; + + return 0; +} + +static const struct video_ops zynqmp_dpsub_ops = { +}; + +static const struct udevice_id zynqmp_dpsub_ids[] = { + { .compatible = "xlnx,zynqmp-dpsub-1.7" }, + { } +}; + +U_BOOT_DRIVER(zynqmp_dpsub_video) = { + .name = "zynqmp_dpsub_video", + .id = UCLASS_VIDEO, + .of_match = zynqmp_dpsub_ids, + .ops = &zynqmp_dpsub_ops, + .plat_auto = sizeof(struct video_uc_plat), + .bind = zynqmp_dpsub_bind, + .probe = zynqmp_dpsub_probe, + .priv_auto = sizeof(struct zynqmp_dpsub_priv), +}; -- 2.39.5