From 910c7a881f5b64dc92d3ba9232ce59ae54fd6486 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 9 Dec 2022 20:35:46 +0100 Subject: [PATCH] pmic: pca9450: Make warm reset on WDOG_B assertion The default configuration of the PMIC behavior makes the PMIC power cycle most regulators on WDOG_B assertion. This power cycling causes the memory contents of OCRAM to be lost. Some systems neeeds some memory that survives reset and reboot, therefore this patch is created. The implementation is taken almost verbatim from Linux commit 2364a64d0673f ("regulator: pca9450: Make warm reset on WDOG_B assertion") Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam Reviewed-by: Peng Fan --- drivers/power/pmic/pca9450.c | 11 ++++++++++- include/power/pca9450.h | 4 ++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index a186edc08d..2427abfb7a 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -86,6 +86,7 @@ static int pca9450_bind(struct udevice *dev) static int pca9450_probe(struct udevice *dev) { struct pca9450_priv *priv = dev_get_priv(dev); + unsigned int reset_ctrl; int ret = 0; if (CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(DM_REGULATOR_PCA9450)) { @@ -95,10 +96,18 @@ static int pca9450_probe(struct udevice *dev) if (IS_ERR(priv->sd_vsel_gpio)) { ret = PTR_ERR(priv->sd_vsel_gpio); dev_err(dev, "Failed to request SD_VSEL GPIO: %d\n", ret); + if (ret) + return ret; } } - return ret; + if (ofnode_read_bool(dev_ofnode(dev), "nxp,wdog_b-warm-reset")) + reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_WARM; + else + reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12; + + return pmic_clrsetbits(dev, PCA9450_RESET_CTRL, + PCA9450_PMIC_RESET_WDOG_B_CFG_MASK, reset_ctrl); } static struct dm_pmic_ops pca9450_ops = { diff --git a/include/power/pca9450.h b/include/power/pca9450.h index fa0405fcb8..6efecee96c 100644 --- a/include/power/pca9450.h +++ b/include/power/pca9450.h @@ -67,4 +67,8 @@ enum { #define PCA9450_LDO34_MASK 0x1f #define PCA9450_LDO5_MASK 0x0f +#define PCA9450_PMIC_RESET_WDOG_B_CFG_MASK 0xc0 +#define PCA9450_PMIC_RESET_WDOG_B_CFG_WARM 0x40 +#define PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12 0x80 + #endif -- 2.39.5