From 6d426bb173d7fdde102c3709bfad02d3bd6c6b7a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 20 Feb 2021 20:06:03 -0500 Subject: [PATCH] arm: Remove am3517_crane board This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Nagendra T S Signed-off-by: Tom Rini --- arch/arm/mach-omap2/omap3/Kconfig | 4 - board/ti/am3517crane/Kconfig | 12 - board/ti/am3517crane/MAINTAINERS | 6 - board/ti/am3517crane/Makefile | 9 - board/ti/am3517crane/am3517crane.c | 72 ------ board/ti/am3517crane/am3517crane.h | 343 ----------------------------- configs/am3517_crane_defconfig | 43 ---- include/configs/am3517_crane.h | 236 -------------------- 8 files changed, 725 deletions(-) delete mode 100644 board/ti/am3517crane/Kconfig delete mode 100644 board/ti/am3517crane/MAINTAINERS delete mode 100644 board/ti/am3517crane/Makefile delete mode 100644 board/ti/am3517crane/am3517crane.c delete mode 100644 board/ti/am3517crane/am3517crane.h delete mode 100644 configs/am3517_crane_defconfig delete mode 100644 include/configs/am3517_crane.h diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index 8bf42aa751..81c898b66e 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -89,9 +89,6 @@ config TARGET_OMAP3_OVERO select OMAP3_GPIO_6 imply CMD_DM -config TARGET_AM3517_CRANE - bool "am3517_crane" - config TARGET_OMAP3_PANDORA bool "OMAP3 Pandora" select OMAP3_GPIO_4 @@ -162,7 +159,6 @@ source "board/ti/beagle/Kconfig" source "board/timll/devkit8000/Kconfig" source "board/ti/evm/Kconfig" source "board/isee/igep00x0/Kconfig" -source "board/ti/am3517crane/Kconfig" source "board/logicpd/omap3som/Kconfig" source "board/nokia/rx51/Kconfig" source "board/lg/sniper/Kconfig" diff --git a/board/ti/am3517crane/Kconfig b/board/ti/am3517crane/Kconfig deleted file mode 100644 index ad025a3228..0000000000 --- a/board/ti/am3517crane/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_AM3517_CRANE - -config SYS_BOARD - default "am3517crane" - -config SYS_VENDOR - default "ti" - -config SYS_CONFIG_NAME - default "am3517_crane" - -endif diff --git a/board/ti/am3517crane/MAINTAINERS b/board/ti/am3517crane/MAINTAINERS deleted file mode 100644 index cbc3213ec5..0000000000 --- a/board/ti/am3517crane/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -AM3517CRANE BOARD -M: Nagendra T S -S: Maintained -F: board/ti/am3517crane/ -F: include/configs/am3517_crane.h -F: configs/am3517_crane_defconfig diff --git a/board/ti/am3517crane/Makefile b/board/ti/am3517crane/Makefile deleted file mode 100644 index eab0400323..0000000000 --- a/board/ti/am3517crane/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Author: Srinath R -# -# Based on logicpd/am3517evm/Makefile -# -# Copyright (C) 2011 Mistral Solutions Pvt Ltd - -obj-y := am3517crane.o diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c deleted file mode 100644 index b1017d6c9b..0000000000 --- a/board/ti/am3517crane/am3517crane.c +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * am3517crane.c - board file for AM3517 CraneBoard - * - * Author: Srinath.R - * - * Based on logicpd/am3517evm/am3517evm.c - * - * Copyright (C) 2011 Mistral Solutions Pvt Ltd - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "am3517crane.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_CRANEBOARD; - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -/* - * Routine: misc_init_r - * Description: Init i2c, ethernet, etc... (done here so udelay works) - */ -int misc_init_r(void) -{ -#ifdef CONFIG_SYS_I2C_OMAP24XX - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); -#endif - - omap_die_id_display(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_AM3517CRANE(); -} - -#if defined(CONFIG_MMC) -int board_mmc_init(struct bd_info *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif diff --git a/board/ti/am3517crane/am3517crane.h b/board/ti/am3517crane/am3517crane.h deleted file mode 100644 index 1e6dece14b..0000000000 --- a/board/ti/am3517crane/am3517crane.h +++ /dev/null @@ -1,343 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * am3517crane.h - Header file for the AM3517 CraneBoard. - * - * Author: Srinath R - * - * Based on logicpd/am3517evm/am3517evm.h - * - * Copyright (C) 2011 Mistral Solutions Pvt Ltd - */ - -#ifndef _AM3517CRANE_H_ -#define _AM3517CRANE_H_ - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "CraneBoard", - "NAND", -}; - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_AM3517CRANE()\ - /*SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_CKE0), (M0))\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(SDRC_CKE0), (M0))\ - MUX_VAL(CP(SDRC_CKE1), (M0))\ - /*sdrc_strben_dly0*/\ - MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0))\ - /*sdrc_strben_dly1*/\ - MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0))\ - /*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (M7))\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_A6), (M7))\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_A9), (M7))\ - MUX_VAL(CP(GPMC_A10), (M7))\ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_NCS2), (M7))\ - MUX_VAL(CP(GPMC_NCS3), (M7))\ - MUX_VAL(CP(GPMC_NCS4), (M7))\ - MUX_VAL(CP(GPMC_NCS5), (M7))\ - MUX_VAL(CP(GPMC_NCS6), (M7))\ - MUX_VAL(CP(GPMC_NCS7), (M7))\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0))/*TP*/\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_NBE1), (M7))\ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_WAIT1), (M7))\ - MUX_VAL(CP(GPMC_WAIT2), (M7))\ - MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4))/*GPIO_65*/\ - /*DSS*/\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0))\ - /*MMC1*/\ - MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M0))\ - /*MMC2*/\ - MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0))\ - /*McBSP*/\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0))\ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0))\ - \ - MUX_VAL(CP(MCBSP2_FSX), (M7))\ - MUX_VAL(CP(MCBSP2_CLKX), (M7))\ - MUX_VAL(CP(MCBSP2_DR), (M7))\ - MUX_VAL(CP(MCBSP2_DX), (M7))\ - \ - MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0))\ - \ - MUX_VAL(CP(MCBSP4_CLKX), (M7))\ - MUX_VAL(CP(MCBSP4_DR), (M7))\ - MUX_VAL(CP(MCBSP4_DX), (M7))\ - MUX_VAL(CP(MCBSP4_FSX), (M7))\ - /*UART*/\ - MUX_VAL(CP(UART1_TX), (M7))\ - MUX_VAL(CP(UART1_RTS), (M7))\ - MUX_VAL(CP(UART1_CTS), (M7))\ - MUX_VAL(CP(UART1_RX), (M7))\ - \ - MUX_VAL(CP(UART2_CTS), (M7))\ - MUX_VAL(CP(UART2_RTS), (M7))\ - MUX_VAL(CP(UART2_TX), (M7))\ - MUX_VAL(CP(UART2_RX), (M7))\ - \ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0))\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0))\ - /*I2C 1, 2, 3*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\ - /*McSPI*/\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4))/*GPIO_171 TP*/\ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4))/*GPIO_172 TP*/\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4))/*GPIO_173 TP*/\ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTU | EN | M4))/*GPIO_174 TP*/\ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4))/*GPIO_175 TP*/\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4))/*GPIO_176 TP*/\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4))/*GPIO_176 TP*/\ - \ - MUX_VAL(CP(MCSPI2_CLK), (M7))\ - MUX_VAL(CP(MCSPI2_SIMO), (M7))\ - MUX_VAL(CP(MCSPI2_SOMI), (M7))\ - MUX_VAL(CP(MCSPI2_CS0), (M7))\ - MUX_VAL(CP(MCSPI2_CS1), (M7))\ - /*CCDC*/\ - MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1))/*CCDC_DATA8*/\ - MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1))/*CCDC_DATA9 */\ - MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0))\ - /*RMII*/\ - MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0))\ - MUX_VAL(CP(RMII_MDIO_CLK), (M0))\ - MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0))\ - MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0))\ - MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0))\ - MUX_VAL(CP(RMII_RXER), (PTD | M0))\ - MUX_VAL(CP(RMII_TXD0), (PTD | M0))\ - MUX_VAL(CP(RMII_TXD1), (PTD | M0))\ - MUX_VAL(CP(RMII_TXEN), (PTD | M0))\ - MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0))\ - /*HECC*/\ - MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0))\ - /*HSUSB*/\ - MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0))\ - /*HDQ*/\ - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4))\ - /*Control and debug*/\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M4))/*GPIO_1 TPS_SLEEP*/\ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0))\ - /*SYS_nRESWARM*/\ - MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | EN | M0))/*GPIO_30 ToExp*/\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))/*GPIO_10 TP*/\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0))\ - /*JTAG*/\ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0))\ - /*ETK (ES2 onwards)*/\ - MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M3))\ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3))\ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3))\ - MUX_VAL(CP(ETK_D10_ES2), (M7))\ - MUX_VAL(CP(ETK_D11_ES2), (M7))\ - MUX_VAL(CP(ETK_D12_ES2), (M7))\ - MUX_VAL(CP(ETK_D13_ES2), (M7))\ - MUX_VAL(CP(ETK_D14_ES2), (M7))\ - MUX_VAL(CP(ETK_D15_ES2), (M7))\ - /*Die to Die*/\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))\ - -#endif /* _AM3517CRANE_H_ */ diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig deleted file mode 100644 index 94d5598bee..0000000000 --- a/configs/am3517_crane_defconfig +++ /dev/null @@ -1,43 +0,0 @@ -CONFIG_ARM=y -# CONFIG_SYS_THUMB_BUILD is not set -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80100000 -# CONFIG_SPL_GPIO_SUPPORT is not set -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL_TEXT_BASE=0x40200800 -CONFIG_TARGET_AM3517_CRANE=y -CONFIG_EMIF4=y -CONFIG_SPL=y -CONFIG_BOOTDELAY=10 -# CONFIG_SPL_FS_EXT4 is not set -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_ECC=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_SPL_NAND_BASE=y -CONFIG_HUSH_PARSER=y -# CONFIG_CMDLINE_EDITING is not set -CONFIG_SYS_PROMPT="AM3517_CRANE # " -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_MUSB_HCD=y -CONFIG_USB_AM35X=y -CONFIG_USB_STORAGE=y -# CONFIG_REGEX is not set diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h deleted file mode 100644 index aa20a7d8f2..0000000000 --- a/include/configs/am3517_crane.h +++ /dev/null @@ -1,236 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * am3517_crane.h - Default configuration for AM3517 CraneBoard. - * - * Author: Srinath.R - * - * Based on include/configs/am3517evm.h - * - * Copyright (C) 2011 Mistral Solutions pvt Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#include /* get chip and board defs */ -#include - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - /* initial data */ -/* - * DDR related - */ -#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 - -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* - * USB configuration - * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard - * Enable CONFIG_USB_MUSB_UDC for Device functionalities. - */ - -#ifdef CONFIG_USB_AM35X -#ifdef CONFIG_USB_MUSB_UDC -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" -#endif /* CONFIG_USB_MUSB_UDC */ - -#endif /* CONFIG_USB_AM35X */ - -#define CONFIG_SYS_I2C - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access */ - /* nand at CS0 */ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ - /* NAND devices */ - -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ - -/* Environment information */ - -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyS2,115200n8\0" \ - "mmcdev=0\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ - "nandargs=setenv bootargs console=${console} " \ - "root=/dev/mtdblock4 rw " \ - "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command */ - /* args */ -/* memtest works on */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ - -/* - * AM3517 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ - /* on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_SYS_FLASH_BASE NAND_BASE - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) - -/* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ - CONFIG_SYS_MAX_NAND_DEVICE) -#define CONFIG_SYS_JFFS2_MEM_NAND -/* use flash_info[2] */ -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -#endif /* __CONFIG_H */ -- 2.39.5