From 610083e547d19e87b567849b299187d66b643fb9 Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Sat, 7 Aug 2021 16:00:48 +0800
Subject: [PATCH] arm: imx8ulp: Enable full L2 cache in SPL

SRAM2 is half L2 cache and default to SRAM after system boot.
To enable the full l2 cache (512KB), it needs to reset A35 to make
the change happen.

So re-implement the jump entry function in SPL:
1. configure the core0 reset vector to entry (ATF)
2. enable the L2 full cache
3. reset A35
So when core0 up, it runs into ATF. And we have 512KB L2 cache working.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/soc.c | 34 +++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index cddcdc2d20..33aec228e3 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -9,6 +9,8 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/armv8/mmu.h>
 #include <asm/mach-imx/boot_mode.h>
+#include <efi_loader.h>
+#include <spl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -292,3 +294,35 @@ int arch_cpu_init(void)
 
 	return 0;
 }
+
+#if defined(CONFIG_SPL_BUILD)
+__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	debug("image entry point: 0x%lx\n", spl_image->entry_point);
+
+	/* Update SIM1 DGO8 for reset vector base */
+	writel((u32)spl_image->entry_point, SIM1_BASE_ADDR + 0x5c);
+
+	/* set update bit */
+	setbits_le32(SIM1_BASE_ADDR + 0x8, 0x1 << 24);
+
+	/* polling the ack */
+	while ((readl(SIM1_BASE_ADDR + 0x8) & (0x1 << 26)) == 0)
+		;
+
+	/* clear the update */
+	clrbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 24));
+
+	/* clear the ack by set 1 */
+	setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
+
+	/* Enable the 512KB cache */
+	setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 4));
+
+	/* reset core */
+	setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 16));
+
+	while (1)
+		;
+}
+#endif
-- 
2.39.5