From 4f340244b974d52c48e01cb845cfe8315f7e5764 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Mon, 4 Dec 2023 14:15:15 +0530 Subject: [PATCH] clk: zynqmp: enable topsw_lsbus clock Display port is using topsw_lsbus clock, it is failing while enabling the clock, so enable the topsw_lsbus clock. Signed-off-by: Sreekanth Sunnam Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20231204084515.9488-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- drivers/clk/clk_zynqmp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 1cfe0e25b1..c059b9e8e6 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -844,6 +844,7 @@ static int zynqmp_clk_enable(struct clk *clk) break; case qspi_ref ... can1_ref: case lpd_lsbus: + case topsw_lsbus: clkact_shift = 24; mask = 0x1; break; -- 2.39.5