From 4892e8301bd0907c6c1b87c20beaa5a4ba7989a2 Mon Sep 17 00:00:00 2001 From: Hiroyuki Yokoyama Date: Wed, 13 Feb 2019 12:35:53 +0900 Subject: [PATCH] pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N According to the R-Car Gen3 Hardware Manual Rev.1.50, the MOD_SEL0 bit16 is set to 0 when NFALE_A and NFRB_N_A pin functions are selected. Signed-off-by: Hiroyuki Yokoyama Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/pinctrl/renesas/pfc-r8a77990.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index 92be19a8bf..992910087e 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -1027,7 +1027,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP10_23_20, NFCLE), PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD), - PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A), + PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDFC_0), PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD), PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1), @@ -1036,7 +1036,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0), PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP), - PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A), + PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDFC_0), PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP), PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1), -- 2.39.5