From 3ed6734e698e4280361f1a509856c50b07861c99 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Mon, 22 Jul 2019 01:24:45 +0000 Subject: [PATCH] i.MX7ULP: Correct the clock index On i.MX7ULP, value zero is reserved in SCG1 RCCR register, so the val should be decreased by 1 to get the correct clock source index. Signed-off-by: Bai Ping Signed-off-by: Peng Fan --- arch/arm/mach-imx/mx7ulp/scg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index b4f2ea875a..85d726fe30 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -440,7 +440,7 @@ static u32 scg_sys_get_rate(enum scg_clk clk) case SCG_SCS_SLOW_IRC: case SCG_SCS_FAST_IRC: case SCG_SCS_RTC_OSC: - rate = scg_src_get_rate(scg_scs_array[val]); + rate = scg_src_get_rate(scg_scs_array[val - 1]); break; case 5: rate = scg_apll_get_rate(); -- 2.39.5