From 3480879a5598735753e8dffda8c38791d19fd467 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Pali=20Roh=C3=A1r?= Date: Wed, 27 Jul 2022 17:21:28 +0200 Subject: [PATCH] board: freescale: p1_p2_rdb_pc: Remove I-flag from second L2 SRAM mapping MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit U-Boot for initial L2 SRAM uses L2 memory-mapping mode and not L2 with locked lines. P2020 reference manual about L2 memory-mapping mode says: Accesses to memory-mapped SRAM are cacheable only in the corresponding e500 L1 caches. So there is no need to set Caching-Inhibit I-bit for second part of initial L2 SRAM mapping in TLB entry. Remove it. First part of initial L2 SRAM mapping already does not have I-bit set. For more details see also: https://lore.kernel.org/u-boot/20220508150844.qqxg452rs4wtf5bs@pali/ Signed-off-by: Pali Rohár --- board/freescale/p1_p2_rdb_pc/tlb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 38843a96cb..105d9e38aa 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -90,14 +90,14 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* RAMBOOT/SPL */ #ifdef CONFIG_SYS_INIT_L2_ADDR - /* *I*G - L2SRAM */ + /* ***G - L2SRAM */ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1), #if CONFIG_SYS_L2_SIZE >= (256 << 10) SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 12, BOOKE_PAGESZ_256K, 1) #endif #endif -- 2.39.5