From 21609289e254c9cae99b651c4a83bcf8e6e8716d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Jul 2024 15:19:03 +0200 Subject: [PATCH] arm: include: sunxi: Remove duplicate newlines Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut --- arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h | 2 -- arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 1 - arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h | 1 - arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h | 1 - arch/arm/include/asm/arch-sunxi/dram_sun9i.h | 2 -- 5 files changed, 7 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h index 14df3cc8f4..35ca0491ac 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h @@ -262,7 +262,6 @@ struct sunxi_ccm_reg { #define CCM_DRAM_GATE_OFFSET_DE_BE0 26 #define CCM_DRAM_GATE_OFFSET_DE_BE1 27 - #define MBUS_CLK_DEFAULT 0x81000002 /* PLL6 / 2 */ #define MBUS_CLK_GATE (0x1 << 31) @@ -295,7 +294,6 @@ struct sunxi_ccm_reg { #define APB2_RESET_TWI_SHIFT (0) #define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) - #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int hz); void clock_set_pll5(unsigned int clk); diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index 0264bfe1c5..006f7761fc 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -217,7 +217,6 @@ struct sunxi_ccm_reg { #define APB1_RESET_TWI_SHIFT 0 #define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT) - #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int clk); void clock_set_pll6(unsigned int clk); diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h index be02655cdd..f0caecc807 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h @@ -323,7 +323,6 @@ struct dram_para { const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; }; - static inline int ns_to_t(int nanoseconds) { const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h index 2a87996354..28b6560ff5 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h @@ -146,7 +146,6 @@ struct sunxi_mctl_ctl_reg { u32 perfwr1; /* 0x1d8 */ }; - #define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x) #define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x) #define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x) diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun9i.h b/arch/arm/include/asm/arch-sunxi/dram_sun9i.h index 41df5fe5b6..a77daecb10 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun9i.h @@ -40,7 +40,6 @@ struct sunxi_mctl_com_reg { u32 mdfstcr; /* 0x14c */ }; - struct sunxi_mctl_ctl_reg { u32 mstr; /* 0x00 master register */ u32 stat; /* 0x04 operating mode status register */ @@ -92,7 +91,6 @@ struct sunxi_mctl_ctl_reg { u32 perfwr1; /* 0x26c write CAM register 1 */ }; - struct sunxi_mctl_phy_reg { u8 res0[0x04]; /* 0x00 revision id ??? */ u32 pir; /* 0x04 PHY initialisation register */ -- 2.39.5