From 0b30cb3de70fbaa4525d169a6fc09f732b290d97 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Apr 2022 12:16:18 +0200 Subject: [PATCH] board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G SDRAM map MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Like for first 1G SDRAM map, do not enable Caching-inhibited nor Guarded attribute for second 1G SDRAM mapping. Whole 2G SDRAM should use caches and also allow speculative loading (by not setting Guarded attribute). Also enable Memory Coherency attribute for second 1G SDRAM map. In commit 316f0d0f8f3c ("powerpc: mpc85xx: Fix static TLB table for SDRAM") it was enabled for all SDRAM maps on all other boards, just missed this one case. As a last thing, first 1G SDRAM map has wrong comment, so adjust it. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- board/freescale/p1_p2_rdb_pc/tlb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index fcd7a55199..5931ec650b 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -79,16 +79,16 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_SYS_RAMBOOT) || \ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) - /* *I*G - eSDHC/eSPI/NAND boot */ + /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), #if defined(CONFIG_TARGET_P1020RDB_PD) - /* 2G DDR on P1020MBG, map the second 1G */ + /* **M** - 2G DDR on P1020MBG, map the second 1G */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 9, BOOKE_PAGESZ_1G, 1), #endif #endif /* RAMBOOT/SPL */ -- 2.39.5