From 054eb8774309636263cbf1a9f5f67f8c8412619c Mon Sep 17 00:00:00 2001 From: Volodymyr Babchuk Date: Mon, 11 Mar 2024 21:33:45 +0000 Subject: [PATCH] clk: qcom: clear div mask before assigning a new divider The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits may be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk Reviewed-by: Caleb Connolly Reviewed-by: Sumit Garg [caleb: minor wording fix] Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-qcom.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 7c683e5192..729d190c54 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -117,7 +117,8 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, /* setup src select and divider */ cfg = readl(base + regs->cfg_rcgr); - cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); + cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK | + CFG_SRC_DIV_MASK); cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */ if (div) -- 2.39.5