]> git.dujemihanovic.xyz Git - u-boot.git/log
u-boot.git
4 years agoARM: zynq: Change zc770 xm011 Nand x16 configurations
Michal Simek [Tue, 18 Feb 2020 14:58:33 +0000 (15:58 +0100)]
ARM: zynq: Change zc770 xm011 Nand x16 configurations

Instead of symlink include origin file and just change model description.
Difference is not in DT but in ps7_init configurations which is taken based
on device tree name that's why the same DT can't be used.

Also update model and update comments to match configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoenv: Kconfig: Adding default values for Microblaze
Varalaxmi Bingi [Wed, 5 Feb 2020 10:58:20 +0000 (03:58 -0700)]
env: Kconfig: Adding default values for Microblaze

This patch will add default values for ENV_OFFSET
and ENV_SECT_SIZE for Microblaze.

Signed-off-by: Varalaxmi Bingi <varalaxmi.bingi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoarm64: zynqmp: Move pinctrl node under firmware node
Michal Simek [Tue, 18 Feb 2020 12:04:06 +0000 (13:04 +0100)]
arm64: zynqmp: Move pinctrl node under firmware node

Pinctrl is handled via firmare interface that's why move it there without
reg property and new compatible string.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoarm64: zynqmp: Fix GIC compatible property
Michal Simek [Tue, 18 Feb 2020 09:01:26 +0000 (10:01 +0100)]
arm64: zynqmp: Fix GIC compatible property

dtbs_check is showing warning around GIC compatible property as
interrupt-controller@f9010000: compatible: ['arm,gic-400', 'arm,cortex-a15-gic']
is not valid under any of the given schemas

Similar change has been done also by Linux kernel commit 5400cdc1410b
("ARM: dts: sunxi: Fix GIC compatible")

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoARM: zynq: Fix addresses in partition definitions
Michal Simek [Wed, 19 Feb 2020 09:57:34 +0000 (10:57 +0100)]
ARM: zynq: Fix addresses in partition definitions

Node name should be <name>@<address> which is not how partitions are
described.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoarm64: zynqmp: Fix addresses in partition definitions
Michal Simek [Fri, 14 Feb 2020 13:19:56 +0000 (14:19 +0100)]
arm64: zynqmp: Fix addresses in partition definitions

Node name should be <name>@<address> which is not how partitions are
described.

Issue was found by running dtbs_check as:
flash@0: 'partition@qspi-device-tree', 'partition@qspi-fsbl-uboot',
'partition@qspi-linux', 'partition@qspi-rootfs'
do not match any of the regexes: ...

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoarm64: zynqmp: Sync DP subsystem
Michal Simek [Tue, 18 Feb 2020 08:24:08 +0000 (09:24 +0100)]
arm64: zynqmp: Sync DP subsystem

Sync DP subsystem with the latest state in Xilinx U-Boot repository.
This binding hasn't been approved in mainline Linux but it is much better
than ancient version which this patch removes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoarm64: zynqmp: Do not duplicate flash partition label property
Amit Kumar Mahapatra [Mon, 17 Feb 2020 14:50:05 +0000 (07:50 -0700)]
arm64: zynqmp: Do not duplicate flash partition label property

In kernel 5.4, support has been added for reading MTD devices via
the nvmem API.
For this the mtd devices are registered as read-only NVMEM providers
under sysfs with the same name as the flash partition label property.

So if flash partition label property of multiple flash devices are identical
then the second mtd device fails to get registered as a NVMEM provider.

This patch fixes the issue by having different label property for different
flashes.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoarm64: dts: zynqmp: Add clk cells for sdhci
Ashok Reddy Soma [Tue, 18 Feb 2020 06:32:57 +0000 (23:32 -0700)]
arm64: dts: zynqmp: Add clk cells for sdhci

Add clock-cells and clock-output-names for sdhci0 and sdhci1.
These are needed for linux sdhci driver from 5.4 version onwards.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoarm64: zynqmp: Remove second copy of reset-controller
Michal Simek [Tue, 18 Feb 2020 08:20:21 +0000 (09:20 +0100)]
arm64: zynqmp: Remove second copy of reset-controller

Reset controller is handled via firmware that's why it should be the part
of firmware node. Origin solution hasn't been removed when above change was
applied by commit b07e97b4ba27 ("arm64: zynqmp: Use reset header in
zynqmp.dtsi").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoarm64: zynqmp: Add 'no-1-8-v' property for ZynqMP Boards
Manish Narani [Fri, 14 Feb 2020 06:37:30 +0000 (23:37 -0700)]
arm64: zynqmp: Add 'no-1-8-v' property for ZynqMP Boards

Modify dts files to add 'no-1-8-v' property for all the ZynqMP boards.
User can remove this property to enable the UHS mode. This is to keep
the same speed (HS) modes across all the stages of the Linux Boot. Due
to power cycling limitation of some of the ZynqMP boards, some SD cards
don't get power cycled and are failing in Linux.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
4 years agoarm64: zynqmp: Sync zynqmp fpga manager with mainline
Nava kishore Manne [Fri, 18 Oct 2019 16:07:32 +0000 (18:07 +0200)]
arm64: zynqmp: Sync zynqmp fpga manager with mainline

Sync zynqmp fpga manager with mainline.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoarm64: zynqmp: Remove unused zynqmp-clk.dtsi
Michal Simek [Tue, 18 Feb 2020 08:10:18 +0000 (09:10 +0100)]
arm64: zynqmp: Remove unused zynqmp-clk.dtsi

All boards have been converted to firmware based driver that's why we can
remove this file now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoARM: zynq: Fix spi name node
Michal Simek [Thu, 26 Sep 2019 10:53:09 +0000 (12:53 +0200)]
ARM: zynq: Fix spi name node

None name address should be aligned with address. DTC 1.5.1 is reporting
issues related to that.

arch/arm/boot/dts/zynq-zc770-xm010.dts:106.10-119.4: Warning
 (spi_bus_reg): /amba/spi@e0007000/flash@0: SPI bus unit address format
 error, expected "1"
arch/arm/boot/dts/zynq-zc770-xm013.dts:101.19-109.4: Warning
(spi_bus_reg): /amba/spi@e0006000/eeprom@0: SPI bus unit address format
 error, expected "2"

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoarm64: zynqmp: Update Copyright years to 2020
Michal Simek [Tue, 18 Feb 2020 07:38:06 +0000 (08:38 +0100)]
arm64: zynqmp: Update Copyright years to 2020

Trivial change.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoarm64: zynqmp: Replace gpio-key,wakeup with wakeup source
Michal Simek [Tue, 18 Feb 2020 11:06:14 +0000 (12:06 +0100)]
arm64: zynqmp: Replace gpio-key,wakeup with wakeup source

The same change has been done for Zynq by commit 1241c72b6db1
("ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source property")
in mainline Linux kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoARM: dts: zynq: replace gpio-key,wakeup with wakeup-source property
Sudeep Holla [Fri, 21 Dec 2018 18:12:13 +0000 (18:12 +0000)]
ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source property

Most of the legacy "gpio-key,wakeup" boolean property is already
replaced with "wakeup-source". However few occurrences of old property
has popped up again, probably from the remnants in downstream trees.

Replace the legacy properties with the unified "wakeup-source"
property introduced in the Linux kernel commit 700a38b27eef
("Input: gpio_keys - switch to using generic device properties")

Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoARM: dts: zc702: Fix I2C bus warnings
Quanyang Wang [Mon, 23 Sep 2019 09:47:08 +0000 (17:47 +0800)]
ARM: dts: zc702: Fix I2C bus warnings

The dtc has new checks for I2C and SPI buses.
Fix the warnings in node names and unit-addresses.

Warning from Linux kernel:
arch/arm/boot/dts/zynq-zc702.dts:187.13-190.6: Warning (i2c_bus_reg): /amba/i2c@e0004000/i2c-mux@74/i2c@7/hwmon@52: I2C bus unit address format error, expected "34"
arch/arm/boot/dts/zynq-zc702.dts:191.13-194.6: Warning (i2c_bus_reg): /amba/i2c@e0004000/i2c-mux@74/i2c@7/hwmon@53: I2C bus unit address format error, expected "35"
arch/arm/boot/dts/zynq-zc702.dts:195.13-198.6: Warning (i2c_bus_reg): /amba/i2c@e0004000/i2c-mux@74/i2c@7/hwmon@54: I2C bus unit address format error, expected "36"

Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoarm64: zynqmp: Enable cache command for mini mtest configuration
Michal Simek [Mon, 17 Feb 2020 11:14:32 +0000 (12:14 +0100)]
arm64: zynqmp: Enable cache command for mini mtest configuration

Enable cache commands by default for mtest configuration. It is good to be
able to enable/disable caches when you test memory.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoconfigs: versal: Add CONFIG_DISTRO_DEFAULTS to versal defconfig
T Karthik Reddy [Fri, 14 Feb 2020 05:26:56 +0000 (22:26 -0700)]
configs: versal: Add CONFIG_DISTRO_DEFAULTS to versal defconfig

Add DISTRO_DEFAULTS config to versal virt defconfig file which is
suitable for booting general purpose Linux distributions. Remove
other configs which are selected by default by DISTRO_DEFAULTS
configuration.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoarm64: zynqmp: Print multiboot register value in EL3
Michal Simek [Tue, 11 Feb 2020 11:43:14 +0000 (12:43 +0100)]
arm64: zynqmp: Print multiboot register value in EL3

Multi boot register can be used for using different boot images and design
better boot strategy. Let EL3 SPL or U-Boot to read it and print it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoMerge branch 'master' of git://git.denx.de/u-boot-sh
Tom Rini [Sat, 4 Apr 2020 23:20:45 +0000 (19:20 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sh

- net: sh_eth: Init the hardware before PHY access

4 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
Tom Rini [Sat, 4 Apr 2020 23:20:26 +0000 (19:20 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86

- verdin-imx8mm board reST documentation update
- Intel Edison board ACPI table I2C/USB minor updates
- Fix a regression of ns16550 serial driver that breaks Intel Edison

4 years agoserial: ns16550: Fix ordering of getting base address
Bin Meng [Sat, 4 Apr 2020 01:35:32 +0000 (18:35 -0700)]
serial: ns16550: Fix ordering of getting base address

Currently the driver gets ns16550 base address in the driver
probe() routine, which may potentially break any ns16550 wrapper
driver that does additional initialization before calling
ns16550_serial_probe().

Things are complicated that we need consider ns16550 devices on
both simple-bus and PCI bus. To fix the issue we move the base
address assignment for simple-bus ns16550 device back to the
ofdata_to_platdata(), and assign base address for PCI ns16550
device in ns16550_serial_probe().

This is still not perfect. If any PCI bus based ns16550 wrapper
driver tries to access plat->base before calling probe(), it is
still subject to break.

Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()")
Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agox86: acpi: Describe USB 3 host controller found on Intel Tangier
Andy Shevchenko [Thu, 26 Mar 2020 10:33:36 +0000 (12:33 +0200)]
x86: acpi: Describe USB 3 host controller found on Intel Tangier

USB 3 host controller may be described in ACPI to allow users alter
the properties or other features. Describe it for Intel Tangier SoC.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: acpi: Add I²C timings to Intel Merrifield platform
Andy Shevchenko [Fri, 20 Mar 2020 17:59:21 +0000 (19:59 +0200)]
x86: acpi: Add I²C timings to Intel Merrifield platform

There is established way to provide I²C timings, or actually counters,
to the OS via ACPI. Fill them for Intel Merrifield platform.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agodoc: board: verdin-imx8mm: use mainline TF-A
Igor Opaniuk [Thu, 5 Mar 2020 20:56:26 +0000 (22:56 +0200)]
doc: board: verdin-imx8mm: use mainline TF-A

1. Update build steps where mainline Trusted Firmware A is used.
2. Fix BL31_BASE to the proper one according to the SoC reference
manual.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: acpi: Refactor XSDT handling in acpi_add_table()
Andy Shevchenko [Thu, 27 Feb 2020 14:00:51 +0000 (16:00 +0200)]
x86: acpi: Refactor XSDT handling in acpi_add_table()

There is no need to have an assignment to NULL for XSDT pointer.
Therefore, no need to assign it when rsdt_address is not set.
Because of above changes we may decrease indentation level as well.

While here, drop unnecessary parentheses.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agonet: sh_eth: Init the hardware before PHY access
Marek Vasut [Sat, 4 Apr 2020 13:01:22 +0000 (15:01 +0200)]
net: sh_eth: Init the hardware before PHY access

To access the PHY, the MAC registers must be initialized. Call the init
function in probe() to make it so, otherwise the PHY ID readout returns
all zeroes.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
4 years agoMerge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-tegra
Tom Rini [Fri, 3 Apr 2020 20:05:46 +0000 (16:05 -0400)]
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-tegra

- Add support for Jetson Nano, plus miscellaneous other fixes found
  during Nano bringup.
- Add Igor's update_uboot wrapper patches.

4 years agoarch: Add explicit linker script for u-boot-elf
Michal Simek [Mon, 30 Mar 2020 11:58:59 +0000 (13:58 +0200)]
arch: Add explicit linker script for u-boot-elf

Commit f4dc714aaa2d ("arm64: Turn u-boot.bin back into an ELF file after
relocate-rela")
introduce REMAKE_ELF option to recreate u-boot.elf from u-boot ->
u-boot.bin + DT -> u-boot.elf.

The best is to ilustrate it from make V=1 output
  cat u-boot-nodtb.bin dts/dt.dtb > u-boot-dtb.bin
  cp u-boot-dtb.bin u-boot.bin
aarch64-linux-gnu-objcopy -I binary -B aarch64 -O elf64-littleaarch64  u-boot.bin u-boot-elf.o
  aarch64-linux-gnu-ld.bfd u-boot-elf.o -o u-boot.elf --defsym="_start"=0x8000000 -Ttext=0x8000000

Last command has no explicit linker script passed that's why toolchain
internal linker script is used.
In Binutils 2.32 case it contains SIZEOF_HEADERS symbol which has changed
behavior by commit
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=64029e93683a266c38d19789e780f3748bd6a188
which result in situation that program headers has changed from
(xilinx_zynqmp_mini_defconfig)

Program Headers:
  Type           Offset             VirtAddr           PhysAddr
                 FileSiz            MemSiz              Flags  Align
  LOAD           0x0000000000010000 0x00000000fffc0000 0x00000000fffc0000
                 0x0000000000018918 0x0000000000018918  RW     0x10000

to

Program Headers:
  Type           Offset             VirtAddr           PhysAddr
                 FileSiz            MemSiz              Flags  Align
  LOAD           0x0000000000000000 0x00000000fffb0000 0x00000000fffb0000
                 0x0000000000028918 0x0000000000028918  RW     0x10000

Xilinx tools like XSDB or Bootgen are using program headers for loading ELF
to the right location and by above binutils change ELF is loaded to
incorrect location.

The patch is explicitly use u-boot-elf.lds (just cat now) for u-boot.elf
recreation which is called when REMAKE_ELF is setup.
By purpose u-boot-elf.lds doesn't contain OUTPUT_FORMAT/OUTPUT_ARCH to be
able to use by all archs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-By: Álvaro Fernández Rojas <noltari@gmail.com>
4 years agomach-snapdragon: Fix overwriting last digit of serial number
Jan-Christoph Tebbe [Mon, 16 Mar 2020 16:51:51 +0000 (17:51 +0100)]
mach-snapdragon: Fix overwriting last digit of serial number

When generating the MAC address based on the boards serial number
the last digit was overwritten with the null termination. That way
boards with serial numbers close to each other would use the same
MAC address.

Signed-off-by: Jan-Christoph Tebbe <Jan-Christoph.Tebbe@ithinx.io>
4 years agoRevert "common: spl_fit: Default to IH_OS_U_BOOT if FIT_IMAGE_TINY enabled"
Ye Li [Wed, 1 Apr 2020 14:42:04 +0000 (07:42 -0700)]
Revert "common: spl_fit: Default to IH_OS_U_BOOT if FIT_IMAGE_TINY enabled"

Commit cf8dcc5d02c3 ("common: spl_fit: Default to IH_OS_U_BOOT if
FIT_IMAGE_TINY enabled") is not correct, it will append fdt to each loadable
image. Actually when using TINY FIT, the first loadable image is thought as
u-boot and already have fdt appended.

Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
4 years agoMerge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi
Tom Rini [Fri, 3 Apr 2020 15:26:13 +0000 (11:26 -0400)]
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi

- fix for MMIO window size (Tudor Ambarus)

4 years agoARM: tegra: Add NVIDIA Jetson Nano Developer Kit support
Tom Warren [Fri, 28 Feb 2020 23:17:07 +0000 (16:17 -0700)]
ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support

The Jetson Nano Developer Kit is a Tegra X1-based development board. It
is similar to Jetson TX1 but it is not pin compatible. It features 4GB
of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot
used for storage.

HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
Ethernet controller provides onboard network connectivity. NVMe support
has also been added. Env save is at the end of QSPI (4MB-8K).

A 40-pin header on the board can be used to extend the capabilities and
exposed interfaces of the Jetson Nano.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
4 years agomtd: spi: Add Macronix MX25U3235F device
Tom Warren [Fri, 20 Mar 2020 21:20:09 +0000 (14:20 -0700)]
mtd: spi: Add Macronix MX25U3235F device

Add Macronix MX25U3235F flash device description.
This is a 4MiB part.

Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agot210: Adjust ramdisk_addr_r/fdt_addr_r to allow for large kernels
Tom Warren [Tue, 17 Mar 2020 00:01:43 +0000 (17:01 -0700)]
t210: Adjust ramdisk_addr_r/fdt_addr_r to allow for large kernels

The L4T kernel is 32MB+, and can overwrite the ramdisk/fdt loaded
from extlinux.conf. Adjust the load addresses to fix this for now.
Using the calculated_env addresses table from T186 U-Boot is a
better fix, but it isn't working correctly on T210 U-Boot right now,
so this will do until I can fix it.

Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoqspi: t210: Use dev_read calls to get FDT data like base, freq
Tom Warren [Fri, 20 Mar 2020 21:33:00 +0000 (14:33 -0700)]
qspi: t210: Use dev_read calls to get FDT data like base, freq

This Tegra QSPI driver hadn't been brought up to date with how
DM drivers are fetching data from the FDT now, and was pulling
in bogus data for base, max freq, etc. Fixed ofdata_to_platdata
to work the same way it does in the tegra114 SPI driver, using
dev_read_ functions.

Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoqspi: t210: Fix QSPI clock and tap delays
Tom Warren [Mon, 25 Nov 2019 21:43:50 +0000 (14:43 -0700)]
qspi: t210: Fix QSPI clock and tap delays

When claim_bus was setting the clock, it reset the QSPI controller,
which wipes out any tap delays set by previous bootloaders (nvtboot,
CBoot for example on Nano). Instead of doing that in claim_bus, which
gets called a lot, moved clock setting to probe(), and set tap delays
there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env
save works reliably again.

Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoqspi: t210: Fix claim_bus's use of the wrong bus/device
Tom Warren [Tue, 12 Nov 2019 20:17:37 +0000 (13:17 -0700)]
qspi: t210: Fix claim_bus's use of the wrong bus/device

claim_bus() is passed a udevice *dev, which is the bus device's parent.
In this driver, claim_bus assumed it was the bus, which caused the
'priv' info pointer to be wrong, and periph_id was incorrect. This in
turn caused the periph clock call to assign the wrong clock (PLLM
instead of PLLP0), which caused a kernel warning. I only saw the 'bad'
periph_id when enabling DEBUG due to an assert. Not sure how QSPI was
working w/this errant clock, but it was moot as QSPI wasn't active
unless you probed it, and that wasn't happening until I posted a patch
to enable env save to QSPI for Nano (coming soon).

Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agommc: t210: Fix 'bad' SD-card clock when doing 400KHz card detect
Tom Warren [Mon, 3 Jun 2019 23:06:34 +0000 (16:06 -0700)]
mmc: t210: Fix 'bad' SD-card clock when doing 400KHz card detect

According to the HW team, for some reason the normal clock select code
picks what appears to be a perfectly valid 375KHz SD card clock, based
on the CAR clock source and SDMMC1 controller register settings (CAR =
408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register
divisor of 16 = 375KHz). But the resulting SD card clock, as measured by
the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the
values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR
clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on
T210 when the requested clock is <= 400KHz. Note that as far as I can
tell, the other requests for clocks in the Tegra MMC driver result in
valid SD clocks.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
4 years agommc: t210: Add autocal and tap/trim updates for SDMMC1/3
Tom Warren [Wed, 29 May 2019 16:30:01 +0000 (09:30 -0700)]
mmc: t210: Add autocal and tap/trim updates for SDMMC1/3

As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and
autocal values need to be set to condition the signals correctly before
talking to the SD-card. This is the same as what's being done in CBoot,
but it gets reset when the SDMMC1 HW is soft-reset during SD driver
init, so needs to be repeated here. Also set autocal and tap/trim for
SDMMC3, although no T210 boards use it for SD-card at this time.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
4 years agotegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all Jetson boards
Tom Warren [Thu, 26 Mar 2020 22:59:14 +0000 (15:59 -0700)]
tegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all Jetson boards

This allows the user to set $serverip in the environment before
executing a DHCP request. If they do, U-Boot will use that IP rather
than using the IP in the DHCP response.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
4 years agoARM: tegra: p2771-0000: enable PIE relocation
Vishruth [Thu, 26 Mar 2020 22:20:43 +0000 (15:20 -0700)]
ARM: tegra: p2771-0000: enable PIE relocation

U-Boot is configured to build as position independent executable. Enable
relocation of RELA section required to work with different load
addresses.

Signed-off-by: Vishruth <vishruthj@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Peter Robinson <probinson@gmail.com>
4 years agoi2c: t210: Add VI_I2C clock source support
Tom Warren [Fri, 27 Mar 2020 17:24:31 +0000 (10:24 -0700)]
i2c: t210: Add VI_I2C clock source support

Fix VI_I2C clock source type. Will be needed by VI_I2C driver.
Also added use of INTERNAL_ID macro in two places, needed to keep
the id returned to 8 bits.

Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agot210: pinmux: Remove pinmux/GPIO init from T210 boards
Tom Warren [Thu, 26 Mar 2020 23:10:11 +0000 (16:10 -0700)]
t210: pinmux: Remove pinmux/GPIO init from T210 boards

T210 CBoot is now doing the full pinmux and GPIO init, based on the DTB
tables. Remove pinmux/GPIO init tables & code from all T210-based builds
below:

p2371-2180 aka TX1
p2371-0000
e2220-1170
p2571

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
4 years agot210: do not enable PLLE and UPHY PLL HW PWRSEQ
JC Kuo [Thu, 26 Mar 2020 23:10:09 +0000 (16:10 -0700)]
t210: do not enable PLLE and UPHY PLL HW PWRSEQ

This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.

Adds call to board_cleanup_before_linux to facilitate this.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
4 years agoARM: tegra: p2371-2180: add I2C nodes to DT
Stephen Warren [Thu, 26 Mar 2020 22:20:45 +0000 (15:20 -0700)]
ARM: tegra: p2371-2180: add I2C nodes to DT

This adds to the DT the I2C controllers that connect to the board ID EEPROM,
etc. With this change, you can now probe all I2C devices on a TX1 board.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
4 years agocolibri_t30: add update_uboot wrapper
Igor Opaniuk [Fri, 27 Mar 2020 10:15:48 +0000 (12:15 +0200)]
colibri_t30: add update_uboot wrapper

Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage.

Create an proper tegra image:
$ cbootimage -s tegra30 colibri_t30.img.cfg colibri_t30.img

Flash in U-boot shell:
> tftpboot ${loadaddr} ${board_name}/${board_name}.img
> run update_uboot

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
4 years agocolibri_t20: add update_uboot wrapper
Igor Opaniuk [Fri, 27 Mar 2020 10:15:47 +0000 (12:15 +0200)]
colibri_t20: add update_uboot wrapper

Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage(NAND).

Create an proper tegra image:
$ cbootimage -s tegra20 colibri_t20-512-v12-nand.img.cfg colibri_t20.img

Flash in U-boot shell:
> tftpboot ${loadaddr} ${board_name}/${board_name}.img
> run update_uboot

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
4 years agoapalis_t30: add update_uboot wrapper
Igor Opaniuk [Fri, 27 Mar 2020 10:15:46 +0000 (12:15 +0200)]
apalis_t30: add update_uboot wrapper

Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage.

Create an proper tegra image:
$ cbootimage -s tegra30 apalis_t30.img.cfg apalis_t30.img

Flash in U-boot shell:
> tftpboot ${loadaddr} ${board_name}/${board_name}.img
> run update_uboot

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
4 years agoapalis-tk1: add update_uboot wrapper
Igor Opaniuk [Fri, 27 Mar 2020 10:15:45 +0000 (12:15 +0200)]
apalis-tk1: add update_uboot wrapper

Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage.

Create an proper tegra image:
$ cbootimage -s tegra124 apalis-tk1.img.cfg apalis-tk1.img

Flash in U-boot shell:
> tftpboot ${loadaddr} ${board_name}/${board_name}.img
> run update_uboot

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
4 years agoMerge tag 'video-fixes-2apr20' of https://gitlab.denx.de/u-boot/custodians/u-boot...
Tom Rini [Thu, 2 Apr 2020 16:15:17 +0000 (12:15 -0400)]
Merge tag 'video-fixes-2apr20' of https://gitlab.denx.de/u-boot/custodians/u-boot-video

- rockchip RK3399 HDMI output fix

4 years agovideo: rockchip: Support 4K resolution for rk3399, HDMI
Jagan Teki [Thu, 2 Apr 2020 11:41:25 +0000 (17:11 +0530)]
video: rockchip: Support 4K resolution for rk3399, HDMI

The default resolution for rockchip display is 1920x1080
which failed to work on 4K HDMI out displays on rk3399.

So, mark the default resolution as 3480x2160 for rk3399
HDMI out.

This would work all the hdmi display resolutions till
4K.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
4 years agorockchip: Enable HDMI output on rk3399 board w/ HDMI
Jagan Teki [Thu, 2 Apr 2020 11:41:24 +0000 (17:11 +0530)]
rockchip: Enable HDMI output on rk3399 board w/ HDMI

Enable config options and console setting to respective
rk3399 board for HDMI output.

Boards supported and tested on this patch are:
- NanoPc T4
- NanoPi M4
- NanoPi Neo4
- ROC-RK3399-PC
- Rock960

Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: Enable pre console for rk3399
Jagan Teki [Thu, 2 Apr 2020 11:41:23 +0000 (17:11 +0530)]
rockchip: Enable pre console for rk3399

Enable pre console buffer for rk3399 platform.

This would help to capture the console messages prior to
the console being initialised. Enabling this would help
to capture all the console messages on video output source
like HDMI. So we can find the full console messages of
U-Boot proper on HDMI display when enabled it for RK3399
platform boards.

Buffer address used for pre console is 0x0f200000 which is
ram base plus 240MiB. right now the Allwinner SoC is using
similar computation.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
4 years agovideo: rockchip: Fix vop modes for rk3399
Jagan Teki [Thu, 2 Apr 2020 11:41:22 +0000 (17:11 +0530)]
video: rockchip: Fix vop modes for rk3399

VOP display endpoint pipeline configuration differs
between rk3288 vs rk3399.

These VOP pipeline configuration depends on how the
different display interfaces connected in sequence to
IN and OUT ports like for,

RK3288:

vopb_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopb_out_edp: endpoint@0 {
reg = <0>;
remote-endpoint = <&edp_in_vopb>;
};
vopb_out_hdmi: endpoint@1 {
reg = <1>;
                remote-endpoint = <&hdmi_in_vopb>;
        };
        vopb_out_lvds: endpoint@2 {
                reg = <2>;
                remote-endpoint = <&lvds_in_vopb>;
        };
        vopb_out_mipi: endpoint@3 {
                reg = <3>;
                remote-endpoint = <&mipi_in_vopb>;
        };
};

RK3399:

vopb_out: port {
         #address-cells = <1>;
         #size-cells = <0>;
         vopb_out_edp: endpoint@0 {
                reg = <0>;
                remote-endpoint = <&edp_in_vopb>;
         };
         vopb_out_mipi: endpoint@1 {
                reg = <1>;
                remote-endpoint = <&mipi_in_vopb>;
         };
         vopb_out_hdmi: endpoint@2 {
                reg = <2>;
                remote-endpoint = <&hdmi_in_vopb>;
         };
         vopb_out_mipi1: endpoint@3 {
                reg = <3>;
                remote-endpoint = <&mipi1_in_vopb>;
         };
         vopb_out_dp: endpoint@4 {
                reg = <4>;
                remote-endpoint = <&dp_in_vopb>;
         };
};

here, HDMI interface has endpoint 1 in rk3288 and 2 in rk3399.

The rockchip vop driver often depends on this determined endpoint
number and stored in vop_mode. So based on this vop_mode the bpp
and pin polarity would configure on detected display interface.

Since, the existing driver using rk3288 vop mode settings enabling
the same will result wrong display interface configuration for rk3399.

Add the patch for fixing these vop modes for rk3399.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
4 years agoclk: rk3399: Set empty for vopl assigned-clocks
Jagan Teki [Thu, 2 Apr 2020 11:41:21 +0000 (17:11 +0530)]
clk: rk3399: Set empty for vopl assigned-clocks

During vidconsole probe, the device probe will try to
check whether the assigned clocks on that video console
node is initialized or not? and return an error if not.

But, unlike Linux U-Boot won't require to handle these
vopl assigned-clocks since core clocks are enough to
handle the video out to process.

So, mark them as empty in set_rate to satisfy clk_set_defaults
so-that probe happened properly.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
4 years agospi: atmel-quadspi: Add verbose debug facilities to monitor register accesses
Tudor Ambarus [Fri, 20 Mar 2020 09:37:59 +0000 (09:37 +0000)]
spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses

This feature should not be enabled in release but can be useful for
developers who need to monitor register accesses at some specific places.

Helped me identify a bug in u-boot, by comparing the register accesses
from the u-boot driver with the ones from its linux variant.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
[jagan: use 16 bit array with tmp variable]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agospi: atmel-quadspi: fix possible MMIO window size overrun
Tudor Ambarus [Fri, 20 Mar 2020 09:37:59 +0000 (09:37 +0000)]
spi: atmel-quadspi: fix possible MMIO window size overrun

The sama5d2 QSPI controller memory space is limited to 128MB:
0x9000_00000-0x9800_00000/0XD000_0000--0XD800_0000.

There are nor flashes that are bigger in size than the memory size
supported by the controller: Micron MT25QL02G (256 MB).

Check if the address exceeds the MMIO window size. An improvement
would be to add support for regular SPI mode and fall back to it
when the flash memories overrun the controller's memory space.

Fixes: 24c8ff4684c5 ("spi: Add Atmel QuadSPI driver")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agoMerge tag 'dm-pull-1apr20' of git://git.denx.de/u-boot-dm
Tom Rini [Wed, 1 Apr 2020 18:29:21 +0000 (14:29 -0400)]
Merge tag 'dm-pull-1apr20' of git://git.denx.de/u-boot-dm

Vboot vulnerability fix

4 years agoMerge tag 'u-boot-stm32-20200401' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
Tom Rini [Wed, 1 Apr 2020 13:47:30 +0000 (09:47 -0400)]
Merge tag 'u-boot-stm32-20200401' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Fix device tree of Avenger96 board from Arrow Electronics and add
  compatibility with stm32mp15_dhcom_basic_defconfig

4 years agotest: vboot: Reduce fake kernel size to 500 bytes
Simon Glass [Wed, 18 Mar 2020 17:44:08 +0000 (11:44 -0600)]
test: vboot: Reduce fake kernel size to 500 bytes

We don't need 5KB to test things out. A smaller size makes it easier to
look at the FIT with fdtdump.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agotest: vboot: Move key creation into a function
Simon Glass [Wed, 18 Mar 2020 17:44:07 +0000 (11:44 -0600)]
test: vboot: Move key creation into a function

This code is repeated so move it into a function with a parameter.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoimage: Use constants for 'required' and 'key-name-hint'
Simon Glass [Wed, 18 Mar 2020 17:44:06 +0000 (11:44 -0600)]
image: Use constants for 'required' and 'key-name-hint'

These are used in multiple places so update them to use a shared #define.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
4 years agotest: vboot: Fix pylint errors
Simon Glass [Wed, 18 Mar 2020 17:44:05 +0000 (11:44 -0600)]
test: vboot: Fix pylint errors

Fix various minor things noticed by pylint.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agotest: vboot: Tidy up the code a little
Simon Glass [Wed, 18 Mar 2020 17:44:04 +0000 (11:44 -0600)]
test: vboot: Tidy up the code a little

Fix some long lines and comments. Use a distinct name for the
'required key' test.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agofit_check_sign: Allow selecting the configuration to verify
Simon Glass [Wed, 18 Mar 2020 17:44:03 +0000 (11:44 -0600)]
fit_check_sign: Allow selecting the configuration to verify

This tool always verifies the default configuration. It is useful to be
able to verify a specific one. Add a command-line flag for this and plumb
the logic through.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoimage: Load the correct configuration in fit_check_sign
Simon Glass [Wed, 18 Mar 2020 17:44:02 +0000 (11:44 -0600)]
image: Load the correct configuration in fit_check_sign

At present bootm_host_load_images() is passed the configuration that has
been verified, but ignores it and just uses the default configuration.
This may not be the same.

Update this function to use the selected configuration.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoimage: Check hash-nodes when checking configurations
Simon Glass [Wed, 18 Mar 2020 17:44:01 +0000 (11:44 -0600)]
image: Check hash-nodes when checking configurations

It is currently possible to use a different configuration's signature and
thus bypass the configuration check. Make sure that the configuration node
that was hashed matches the one being checked, to catch this problem.

Also add a proper function comment to fit_config_check_sig() and make it
static.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agotest: vboot: Parameterise the test
Simon Glass [Wed, 18 Mar 2020 17:44:00 +0000 (11:44 -0600)]
test: vboot: Parameterise the test

This test is actually made up of five separate tests. Split them out so
that they appear as separate tests.

Unfortunately this restarts U-Boot multiple times which adds about a
second to the already-long vboot test, about 8 seconds total on my
machine. We could add a special 'teardown' test afterwards but if the
tests are executed out of order that would not work.

Changing test_vboot into a class causes it not to be discovered and makes
it different from all other tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agotest: vboot: Add a test for a forged configuration
Simon Glass [Wed, 18 Mar 2020 17:43:59 +0000 (11:43 -0600)]
test: vboot: Add a test for a forged configuration

Add a check to make sure that it is not possible to add a new
configuration and use the hashed nodes and hash of another configuration.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agotest: vboot: Drop unnecessary parameter for fit_check_sign
Simon Glass [Wed, 18 Mar 2020 17:43:58 +0000 (11:43 -0600)]
test: vboot: Drop unnecessary parameter for fit_check_sign

This tool only uses the last -k parameter provided. Drop the earlier one
since it has no effect.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoimage: Return an error message from fit_config_verify_sig()
Simon Glass [Wed, 18 Mar 2020 17:43:57 +0000 (11:43 -0600)]
image: Return an error message from fit_config_verify_sig()

This function only returns an error message sometimes. Update it to always
return an error message if one is available. This makes it easier to see
what went wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoimage: Be a little more verbose when checking signatures
Simon Glass [Wed, 18 Mar 2020 17:43:56 +0000 (11:43 -0600)]
image: Be a little more verbose when checking signatures

It is useful to be a little more specific about what is being checked.
Update a few messages to help with this.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoimage: Correct comment for fit_conf_get_node()
Simon Glass [Wed, 18 Mar 2020 17:43:55 +0000 (11:43 -0600)]
image: Correct comment for fit_conf_get_node()

This should mention that conf_uname can be NULL and should be in the
header file. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoARM: dts: stm32: Repair PMIC configuration on AV96
Marek Vasut [Tue, 31 Mar 2020 17:51:34 +0000 (19:51 +0200)]
ARM: dts: stm32: Repair PMIC configuration on AV96

The core and vdd PMIC buck regulators were misconfigured, which caused
instability of the board and malfunction of high-speed interfaces, like
the RGMII. Configure the PMIC correctly to repair these problems. Also,
model the missing Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
4 years agoARM: dts: stm32: Add missing ethernet PHY reset on AV96
Marek Vasut [Tue, 31 Mar 2020 17:51:33 +0000 (19:51 +0200)]
ARM: dts: stm32: Add missing ethernet PHY reset on AV96

Add PHY reset GPIO on AV96 ethernet PHY.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
4 years agoARM: dts: stm32: Repair ethernet operation on AV96
Marek Vasut [Tue, 31 Mar 2020 17:51:32 +0000 (19:51 +0200)]
ARM: dts: stm32: Repair ethernet operation on AV96

The AV96 RGMII uses different pinmux for ETH_RGMII_TXD0, ETH_RGMII_RXD2
and ETH_RGMII_TX_CTL. Use the correct pinmux to make ethernet operational.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
4 years agoARM: dts: stm32: Add alternate pinmux for ethernet RGMII
Marek Vasut [Tue, 31 Mar 2020 17:51:31 +0000 (19:51 +0200)]
ARM: dts: stm32: Add alternate pinmux for ethernet RGMII

Add another mux option for DWMAC RGMII, this is used on AV96 board.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
4 years agoARM: dts: stm32: Add configuration EEPROM on AV96
Marek Vasut [Tue, 31 Mar 2020 17:51:30 +0000 (19:51 +0200)]
ARM: dts: stm32: Add configuration EEPROM on AV96

The board has an EEPROM on the same I2C bus as PMIC, at address 0x53.
The EEPROM contains the board MAC address.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Change-Id: I340a0675c11e4599968b2e3ef0515fb8da8d7b42

4 years agoARM: dts: stm32: Use DT alias for the configuration EEPROM
Marek Vasut [Tue, 31 Mar 2020 17:51:29 +0000 (19:51 +0200)]
ARM: dts: stm32: Use DT alias for the configuration EEPROM

Use DT /aliases node to establish a stable phandle to the configuration
EEPROM. This permits the configuration EEPROM to be moved e.g. to a
different address or a different bus. Adjust the board code to handle
new phandle lookup.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
4 years agoARM: dts: stm32: Add QSPI NOR on AV96
Marek Vasut [Tue, 31 Mar 2020 17:51:28 +0000 (19:51 +0200)]
ARM: dts: stm32: Add QSPI NOR on AV96

The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it
into the DT.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Change-Id: Ia7c454c496f50e3fc4851ec1154f3641c416e98e

4 years agoARM: dts: stm32: Repair SDMMC2 operation
Marek Vasut [Tue, 31 Mar 2020 17:51:27 +0000 (19:51 +0200)]
ARM: dts: stm32: Repair SDMMC2 operation

The eMMC uses different pinmux for the top four data lines, use such
a pinmux, otherwise it takes a very long time until the test for 8bit
operation times out. And this is the correct pinmux per schematic too.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
4 years agoARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7
Marek Vasut [Tue, 31 Mar 2020 17:51:26 +0000 (19:51 +0200)]
ARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7

Add another mux option for SDMMC2 pins 4..7, this is used on AV96 board.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
4 years agoARM: dts: stm32: Repair SDMMC1 operation on AV96
Marek Vasut [Tue, 31 Mar 2020 17:51:25 +0000 (19:51 +0200)]
ARM: dts: stm32: Repair SDMMC1 operation on AV96

The SD uses different pinmux for the D123DIRline, use such a pinmux,
otherwise there is a pinmux collision on the AV96. Add missing SD
voltage regulator switch and enable SDR104 operation.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
4 years agoARM: dts: stm32: Add alternate pinmux for SDMMC1 direction pins
Marek Vasut [Tue, 31 Mar 2020 17:51:24 +0000 (19:51 +0200)]
ARM: dts: stm32: Add alternate pinmux for SDMMC1 direction pins

Add another mux option for SDMMC1 direction pins, in particular
SDMMC1_D123DIR, this is used on AV96 board.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
4 years agoARM: dts: stm32: Repair SD1 pre-reloc pinmux DT node on AV96
Marek Vasut [Tue, 31 Mar 2020 17:51:23 +0000 (19:51 +0200)]
ARM: dts: stm32: Repair SD1 pre-reloc pinmux DT node on AV96

The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41d9d4
("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{};
became pins1{};pins2{};, however the SPL extras were not updated to reflect
that change. Fix this.

This fixes booting from SD1 X9 slot on the AV96 board.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Fixes: 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
4 years agoMerge tag 'arc-last-minute-fixes-for-2020.04' of https://gitlab.denx.de/u-boot/custod...
Tom Rini [Tue, 31 Mar 2020 19:10:54 +0000 (15:10 -0400)]
Merge tag 'arc-last-minute-fixes-for-2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-arc

This last minute pull-request is intended to fix some drivers
when used on ARC boards. The problem was introduced by
https://gitlab.denx.de/u-boot/u-boot/-/commit/07906b3dad157bd58411664bcc6a2a7976d5e0a9

What happened while doing one pretty simple improvement to make
U-Boot port more flexible and portable (by switching accessors from
assembly-written to plain C version) we implicitly added 2 problems:

 1. Downgraded accessors from being volatile which signalled to
    the compiler that it's now possible to do all kinds of optimizations
    which may easily include merge of subsequent byte reads/writes into
    word operations. Which is OK for accessing mormal memory but
    breaks operation of peripherals if we access its memory-mapped regs
    in such a "creative" manner.
 2. As a part of assembly-written implementation we had compiler barriers
    in form of the following construction 'asm volatile("" : : : "memory")',
    and we dropped it in C implemntation. This in its turn enabled compiler
    to mess with instruction ordering. Guess what it gives us in the end :)

So with all that we had in some corner-cases veeery funny instruction flows
generated. And in particular it broke DW SPI functionality when we were
writing large amount of data. Funny enough our tests which were writing
small amount of data still worked and only by the chance we caught that
breakage and unrolled that quite interesting loop of unexpected
problems.

The road to hell is paved with good intentions. Amen :)

4 years agoARC: IO: add MB for __raw_* memory accessors
Eugeniy Paltsev [Mon, 30 Mar 2020 19:44:45 +0000 (22:44 +0300)]
ARC: IO: add MB for __raw_* memory accessors

We add memory barriers for __raw_readX / __raw_writeX accessors same
way as it is done for readX and writeX accessors as lots of U-boot
driver uses __raw_readX / __raw_writeX instead of proper accessor
with barrier.

It will save us from lot's of debugging in the future and it is OK
as U-Boot is not that performance oriented as real run-time
software like OS or user bare-metal app so we may afford being not
super fast as we only being executed once.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
4 years agoARC: IO: add compiler barriers to IO accessors
Eugeniy Paltsev [Mon, 30 Mar 2020 19:44:44 +0000 (22:44 +0300)]
ARC: IO: add compiler barriers to IO accessors

We must use compiler barriers in C-version read/write IO accessors
before and after operation (read or write) so it won't be reordered
by compiler.

Fixes commit 07906b3dad15 ("ARC: Switch to generic accessors")

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
4 years agoARC: IO: add volatile to accessors
Eugeniy Paltsev [Mon, 30 Mar 2020 19:44:43 +0000 (22:44 +0300)]
ARC: IO: add volatile to accessors

We must use 'volatile' in C-version read/write IO accessors
implementation to avoid merging several reads (writes) into
one read (write), or optimizing them out by compiler.

Fixes commit 07906b3dad15 ("ARC: Switch to generic accessors")

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
4 years agoMerge branch '2020-03-31-master-imports'
Tom Rini [Tue, 31 Mar 2020 14:07:01 +0000 (10:07 -0400)]
Merge branch '2020-03-31-master-imports'

- mpc8xxx GPIO, SPI bugfixes
- Add VxWorks to FIT images
- macb ethernet driver bugfix

4 years agonet: macb: Fix incorrect write function name when MACB_ZYNQ is enabled.
Michal Simek [Thu, 26 Mar 2020 14:01:29 +0000 (15:01 +0100)]
net: macb: Fix incorrect write function name when MACB_ZYNQ is enabled.

When MACB_ZYNQ is enabled there is compilation warnings
drivers/net/macb.c: In function ‘_macb_init’:
drivers/net/macb.h:675:33: error: ‘MACB_DMACFG’ undeclared (first use in this function);
 did you mean ‘MACB_MCF’?
  writel((value), (port)->regs + MACB_##reg)
                                 ^~~~~

It has been caused by changing macros name by commit below.

Fixes: 6c636514d499 ("net: macb: sync header definitions as taken from Linux")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agompc8xxx_spi: implement real ->set_speed
Rasmus Villemoes [Tue, 11 Feb 2020 15:20:25 +0000 (15:20 +0000)]
mpc8xxx_spi: implement real ->set_speed

Not all boards have the same CSB frequency, nor do every SPI slave
necessarily support running at 16.7 MHz. So implement ->set_speed;
that also allows using a smaller PM (i.e., 0) for slaves that do
support a higher speed.

Based on work by Klaus H. Sørensen.

Cc: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
4 years agompc8xxx_spi: always use 8-bit characters, don't read or write garbage
Rasmus Villemoes [Tue, 11 Feb 2020 15:20:25 +0000 (15:20 +0000)]
mpc8xxx_spi: always use 8-bit characters, don't read or write garbage

There are a few problems with the current driver.

First, it unconditionally reads from dout/writes to din whether or not
those pointers are NULL. So for example a simple "sf probe" ends up
writing four bytes at address 0:

=> md.l 0x0 8
0000000045454545 45454545 05050505 05050505    EEEEEEEE........
0000001000000000 00000000 07070707 07070707    ................
=> sf probe 0
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53618 din 00000000 bitlen 8
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 0FB536B8 bitlen 48
SF: Detected s25sl032p with page size 256 Bytes, erase size 64 KiB, total 4 MiB
=> md.l 0x0 8
00000000ff000000 45454545 05050505 05050505    ....EEEE........
0000001000000000 00000000 07070707 07070707    ................

(here I've change the first debug statement to a printf, and made it
print the din/dout pointers rather than the uints they point at).

Second, as we can also see above, it always writes a full 32 bits,
even if a smaller amount was requested. So for example

=> mw.l $loadaddr 0xaabbccdd 8
=> md.l $loadaddr 8
02000000aabbccdd aabbccdd aabbccdd aabbccdd    ................
02000010aabbccdd aabbccdd aabbccdd aabbccdd    ................
=> sf read $loadaddr 0x400 6
device 0 offset 0x400, size 0x6
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 48
SF: 6 bytes @ 0x400 Read: OK
=> sf read 0x02000010 0x400 8
device 0 offset 0x400, size 0x8
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53848 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000010 bitlen 64
SF: 8 bytes @ 0x400 Read: OK
=> md.l $loadaddr 8
0200000045454545 45450000 aabbccdd aabbccdd    EEEEEE..........
0200001045454545 45454545 aabbccdd aabbccdd    EEEEEEEE........

Finally, when the bitlen is 24 mod 32 (e.g. requesting to read 3 or 7
bytes), the last three bytes and up being the wrong ones, since the
driver does a full 32 bit read and then shifts the wrong byte out:

=> mw.l $loadaddr 0xaabbccdd 4
=> md.l $loadaddr 4
02000000aabbccdd aabbccdd aabbccdd aabbccdd    ................
=> sf read $loadaddr 0x444 10
device 0 offset 0x444, size 0x10
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 128
SF: 16 bytes @ 0x444 Read: OK
=> md.l $loadaddr 4
02000000552d426f 6f742032 3031392e 30342d30    U-Boot 2019.04-0
=> mw.l $loadaddr 0xaabbccdd 4
=> sf read $loadaddr 0x444 0xb
device 0 offset 0x444, size 0xb
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 88
SF: 11 bytes @ 0x444 Read: OK
=> md.l $loadaddr 4
02000000552d426f 6f742032 31392e00 aabbccdd    U-Boot 219......

Fix all of that by always using a character size of 8, and reject
transfers that are not a whole number of bytes. While it ends being
more work for the CPU, we're mostly bounded by the speed of the SPI
bus, and we avoid writing to the mode register in every loop.

Based on work by Klaus H. Sørensen.

Cc: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
4 years agompc8xxx_spi: put max_cs to use
Rasmus Villemoes [Tue, 11 Feb 2020 15:20:24 +0000 (15:20 +0000)]
mpc8xxx_spi: put max_cs to use

Currently, max_cs is write-only; it's just set in
mpc8xxx_spi_ofdata_to_platdata and not otherwise used.

My mpc8309 was always resetting during an "sf probe 0". It turns out
dm_gpio_set_dir_flags() was being called with garbage, since nothing
had initialized priv->gpios[0] - our device tree used "cs-gpios"
rather than "gpios", so gpio_request_list_by_name() had returned 0.

That would have been a lot easier to figure out if the chip select
index was sanity checked, so rename max_cs to cs_count, and reject a
xfer with a too large cs index.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
4 years agogazerbeam: add clocks property to SPI node
Rasmus Villemoes [Tue, 11 Feb 2020 15:20:23 +0000 (15:20 +0000)]
gazerbeam: add clocks property to SPI node

Prepare for supporting setting different speeds in mpc8xxx_spi.c.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
4 years agogpio/mpc83xx_spisel_boot.c: gpio driver for SPISEL_BOOT signal
Klaus H. Sorensen [Tue, 11 Feb 2020 15:20:22 +0000 (15:20 +0000)]
gpio/mpc83xx_spisel_boot.c: gpio driver for SPISEL_BOOT signal

Some SoCs in the mpc83xx family, e.g. mpc8309, have a dedicated spi
chip select, SPISEL_BOOT, that is used by the boot code to boot from
flash.

This chip select will typically be used to select a SPI boot
flash. The SPISEL_BOOT signal is controlled by a single bit in the
SPI_CS register.

Implement a gpio driver for the spi chip select register. This allows a
spi driver capable of using gpios as chip select, to bind a chip select
to SPISEL_BOOT.

It may be a little odd to do this as a GPIO driver, since the signal
is neither GP or I, but it is quite convenient to present it to the
spi driver that way. The alternative it to teach mpc8xxx_spi to handle
the SPISEL_BOOT signal itself (that is how it's done in the linux
kernel, see commit 69b921acae8a)

Signed-off-by: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
4 years agogpio: mpc8xxx: don't do RMW on gpdat register when setting value
Rasmus Villemoes [Tue, 28 Jan 2020 12:04:34 +0000 (12:04 +0000)]
gpio: mpc8xxx: don't do RMW on gpdat register when setting value

The driver correctly handles reading back the value of an output gpio
by reading from the shadow register for output, and from gpdat for
inputs.

Unfortunately, when setting the value of some gpio, we do a RMW cycle
on the gpdat register without taking the shadow register into account,
thus accidentally setting other output gpios (at least those whose
value cannot be read back) to 0 at the same time.

When changing a gpio from input to output, we still need to make sure
it initially has the requested value. So, the procedure is

- update the shadow register
- compute the new gpdir register
- write the bitwise and of the shadow and new gpdir register to gpdat
- write the new gpdir register

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>