]> git.dujemihanovic.xyz Git - u-boot.git/log
u-boot.git
7 weeks agomemory: ti-aemif: Add ARCH_DAVINCI to architectures that uses TI_AEMIF
Bastien Curutchet [Mon, 21 Oct 2024 15:13:27 +0000 (17:13 +0200)]
memory: ti-aemif: Add ARCH_DAVINCI to architectures that uses TI_AEMIF

TI_AEMIF configuration doesn't depend on ARCH_DAVINCI while the AEMIF
controller is present in the DaVinci SoCs.

Add ARCH_DAVINCI to the potential users of the TI_AEMIF driver
Add <asm/io.h> to driver's includes to fix build issue on ARCH_DAVINCI

Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 weeks agomemory: ti-aemif: Make AEMIF driver architecture agnostic
Bastien Curutchet [Mon, 21 Oct 2024 15:13:26 +0000 (17:13 +0200)]
memory: ti-aemif: Make AEMIF driver architecture agnostic

AEMIF controller is present on other SoCs than the Keystone ones.

Remove Keystone specificities from the driver to be able to use it from
other architectures.
Adapt the ks2_evm/board.c to fit the new driver.

Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 weeks agomemory: ti-aemif: Correct macro to ensure avoiding precedence issues
Bastien Curutchet [Mon, 21 Oct 2024 15:13:25 +0000 (17:13 +0200)]
memory: ti-aemif: Correct macro to ensure avoiding precedence issues

Fix following CHECK pointed out by checkpatch:

   CHECK: Macro argument 'cs' may be better as '(cs)' to avoid precedence issues
   #62: FILE: drivers/memory/ti-aemif.c:15:
   +#define AEMIF_CONFIG(cs)               (0x10 + (cs * 4))

Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 months agoarch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD
Simon Glass [Mon, 30 Sep 2024 01:49:46 +0000 (19:49 -0600)]
arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agodoc: Update init docs for the xPL changes
Simon Glass [Mon, 30 Sep 2024 01:49:45 +0000 (19:49 -0600)]
doc: Update init docs for the xPL changes

Update the documentation here to cover the meaning of xPL

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agodoc: Move init-related things out of README
Simon Glass [Mon, 30 Sep 2024 01:49:44 +0000 (19:49 -0600)]
doc: Move init-related things out of README

Move this section to rst, changing it just enough so that it builds.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agoREADME: Drop SoC-specific comment about SPL
Simon Glass [Mon, 30 Sep 2024 01:49:43 +0000 (19:49 -0600)]
README: Drop SoC-specific comment about SPL

This should not be in the generic README file, so drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agodoc: Update SPL docs for the xPL changes
Simon Glass [Mon, 30 Sep 2024 01:49:42 +0000 (19:49 -0600)]
doc: Update SPL docs for the xPL changes

Update the various references to SPL in this document. Make sure to
refer to 'phases' instead of 'stages', which is not a U-Boot term.

Fix a few U-boot typos and try to improve grammar a little while we are
here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agolog: global: Rename warn_non_spl()
Simon Glass [Mon, 30 Sep 2024 01:49:41 +0000 (19:49 -0600)]
log: global: Rename warn_non_spl()

This should now refer to xPL rather than SPL, so update it throughout
the tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agoxpl: Rename spl_phase_prefix() and spl_phase_name()
Simon Glass [Mon, 30 Sep 2024 01:49:40 +0000 (19:49 -0600)]
xpl: Rename spl_phase_prefix() and spl_phase_name()

Use simpler names for these functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agoxpl: Rename spl_next_phase() and spl_prev_phase()
Simon Glass [Mon, 30 Sep 2024 01:49:39 +0000 (19:49 -0600)]
xpl: Rename spl_next_phase() and spl_prev_phase()

Rename this to use the xpl prefix.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agoxpl: Add a function to indicate when in xPL
Simon Glass [Mon, 30 Sep 2024 01:49:38 +0000 (19:49 -0600)]
xpl: Add a function to indicate when in xPL

Add the opposite function to not_xpl() for completeness.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agoxpl: Rename spl_in_proper() to not_xpl()
Simon Glass [Mon, 30 Sep 2024 01:49:37 +0000 (19:49 -0600)]
xpl: Rename spl_in_proper() to not_xpl()

Give this function a slightly easier name.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agoxpl: Rename spl_phase() to xpl_phase()
Simon Glass [Mon, 30 Sep 2024 01:49:36 +0000 (19:49 -0600)]
xpl: Rename spl_phase() to xpl_phase()

Rename this function to indicate that it refers to any xPL phase.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agoxpl: Rename spl_phase to xpl_phase_t
Simon Glass [Mon, 30 Sep 2024 01:49:35 +0000 (19:49 -0600)]
xpl: Rename spl_phase to xpl_phase_t

This name fits better with the new naming scheme, so update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agoxpl: Rename u_boot_first_phase to xpl_is_first_phase()
Simon Glass [Mon, 30 Sep 2024 01:49:34 +0000 (19:49 -0600)]
xpl: Rename u_boot_first_phase to xpl_is_first_phase()

This is a better name for this function, so update it.

Tidy up the function comment to mention VPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agoqconfig: Add XPL_BUILD to ignored symbols
Simon Glass [Mon, 30 Sep 2024 01:49:33 +0000 (19:49 -0600)]
qconfig: Add XPL_BUILD to ignored symbols

This now appears in the code base, so add it to the list of ignored
symbols in qconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agoscripts: Define CONFIG_XPL_BUILD for all xPL builds
Simon Glass [Mon, 30 Sep 2024 01:49:32 +0000 (19:49 -0600)]
scripts: Define CONFIG_XPL_BUILD for all xPL builds

The new name 'xPL' is intended to indicate a build of any phase which is
not U-Boot proper. Define it for all such phases.

Note that we also define CONFIG_SPL_BUILD for all xPL builds. This
preserves existing behaviour, but future patches will adjust that.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agoscripts: Add some comments about autoconf.mk
Simon Glass [Mon, 30 Sep 2024 01:49:31 +0000 (19:49 -0600)]
scripts: Add some comments about autoconf.mk

Now that the conversion of all CONFIG options to Kconfig is complete,
these files only contain the xPL_BUILD defines. Add a comment to make
this clear.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agoscripts: Rename Makefile.spl to Makefile.xpl
Simon Glass [Mon, 30 Sep 2024 01:49:30 +0000 (19:49 -0600)]
scripts: Rename Makefile.spl to Makefile.xpl

Rename this file to indicate that it refers to any non-U-Boot-proper
phase, not just SPL, which is the phase immediately before U-Boot
proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agostdio: Make use of the SERIAL define
Simon Glass [Mon, 30 Sep 2024 01:49:29 +0000 (19:49 -0600)]
stdio: Make use of the SERIAL define

This is always enabled for U-Boot proper, so simplify the condition
in the common Makefile.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 months agoserial: Make use of the SERIAL define
Simon Glass [Mon, 30 Sep 2024 01:49:28 +0000 (19:49 -0600)]
serial: Make use of the SERIAL define

This is always enabled for U-Boot proper, so simplify the condition
in the common Makefile.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agonet: freescale: Drop use of SPL_BUILD dependency
Simon Glass [Mon, 30 Sep 2024 01:49:27 +0000 (19:49 -0600)]
net: freescale: Drop use of SPL_BUILD dependency

SPL_BUILD is not a Kconfig symbol. Perhaps the intent here is to use
SPL instead. However, this causes build errors, e.g. with T1024RDB_NAND

So drop the dependency on !SPL_BUILD since it does nothing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agotegra: Drop dependency on SPL_BUILD
Simon Glass [Mon, 30 Sep 2024 01:49:26 +0000 (19:49 -0600)]
tegra: Drop dependency on SPL_BUILD

SPL_BUILD is not a Kconfig symbol so perhaps the intent here is to
use SPL instead. But that changes the output size.

So drop the dependency on !SPL_BUILD since it does nothing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 months agoboot: Drop unnecessary ifdef for LOAD_FIT
Simon Glass [Mon, 30 Sep 2024 01:49:25 +0000 (19:49 -0600)]
boot: Drop unnecessary ifdef for LOAD_FIT

Use the normal SPL_TPL_ approach for this option.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 months agoMakefile: Add a u-boot.cfg file for VPL
Simon Glass [Mon, 30 Sep 2024 01:49:24 +0000 (19:49 -0600)]
Makefile: Add a u-boot.cfg file for VPL

Create this file for VPL as well, for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
3 months agoboard: xilinx: Remove conditional check for Microblaze
Padmarao Begari [Fri, 13 Sep 2024 09:32:31 +0000 (15:02 +0530)]
board: xilinx: Remove conditional check for Microblaze

U-Boot is not picking boot.scr script address from device tree
rather it's using default address for Microblaze platform,
and it's picking for other platforms. Remove conditional check
for Microblaze platform, so that u-boot pick up boot.scr script
address for all platforms from device tree.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20240913093231.2343528-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
3 months agommc: zynq_sdhci: Remove device_is_compatible() function
Padmarao Begari [Fri, 13 Sep 2024 09:31:57 +0000 (15:01 +0530)]
mmc: zynq_sdhci: Remove device_is_compatible() function

There are lot of device_is_compatible() present in the driver.
Remove them and replace with a variables "SDHCI_COMPATIBLE_SDHCI_89A"
and "SDHCI_COMPATIBLE_VERSAL_NET_EMMC" with match data.
This change saves the space and reduce the execution time.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20240913093157.2343476-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
3 months agoarm64: zynqmp: Remove overlays and add new dtb entries for ZynqMP
Prasad Kummari [Fri, 6 Sep 2024 07:08:08 +0000 (12:38 +0530)]
arm64: zynqmp: Remove overlays and add new dtb entries for ZynqMP

Remove device tree overlay (DTBO) entries for the ZynqMP target
from the Makefile. Add new device tree binaries (DTBs) for the
zynqmp-sm-k24-revA and zynqmp-smk-k24-revA configurations.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240906070808.1045991-3-prasad.kummari@amd.com
3 months agokbuild: cherry-pick kbuild fdtoverlay changes from linux
Prasad Kummari [Fri, 6 Sep 2024 07:08:07 +0000 (12:38 +0530)]
kbuild: cherry-pick kbuild fdtoverlay changes from linux

Linux commits:
15d16d6dadf6 kbuild: Add generic rule to apply fdtoverlay
44f87191d105 kbuild: parameterize the .o part of suffix-search

The Linux commit 15d16d6dadf6 adds a generic rule in Makefile.lib
to automatically apply fdtoverlay, so that each platform doesn't
need to include a complex rule. This also automatically appends
DTC_FLAGS_foo_base += -@ to all base files

The platform's Makefile only needs to have this now:

foo-dtbs := foo_base.dtb foo_overlay1.dtbo foo_overlay2.dtbo
dtb-y := foo.dtb

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240906070808.1045991-2-prasad.kummari@amd.com
3 months agoarm64: zynqmp: Add missing vc7_xin fixed clock to sc-vpk180-revA
Michal Simek [Mon, 9 Sep 2024 11:24:09 +0000 (13:24 +0200)]
arm64: zynqmp: Add missing vc7_xin fixed clock to sc-vpk180-revA

Add missing vc7_xin fixed clock as clock input for some clock generators.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4904f5e0aab8a0b0c2fcc1912be493d4185e6173.1725881047.git.michal.simek@amd.com
3 months agoarm: zynqmp: Enable non-invasive CCI-400 PMU debug
Sean Anderson [Thu, 5 Sep 2024 17:18:33 +0000 (13:18 -0400)]
arm: zynqmp: Enable non-invasive CCI-400 PMU debug

Set NIDEN, enabling non-invasive debug for the CCI-400 PMU. Otherwise,
the PMU is effectively disabled.

Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240905171833.325548-3-sean.anderson@linux.dev
Signed-off-by: Michal Simek <michal.simek@amd.com>
3 months agozynqmp: Disable secure access for boot devices
Sean Anderson [Thu, 5 Sep 2024 17:18:32 +0000 (13:18 -0400)]
zynqmp: Disable secure access for boot devices

Boot devices (QSPI, MMC, NAND, and Ethernet) use secure access for DMA
by default. As this causes problems when using the SMMU [1], configure
them for normal access instead.

[1] https://support.xilinx.com/s/article/72164

Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Link: https://lore.kernel.org/r/20240905171833.325548-2-sean.anderson@linux.dev
Signed-off-by: Michal Simek <michal.simek@amd.com>
3 months agoxilinx: Enable SIMPLE_PM_BUS
Michal Simek [Tue, 3 Sep 2024 07:48:15 +0000 (09:48 +0200)]
xilinx: Enable SIMPLE_PM_BUS

Enable simple-pm-bus driver to handle case where axi bus coming between PS
(fixed) part to PL (programmable) part has own clock or power domain.
That's why enable driver to be ready for this configuration.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b9f4bb85be502616edf3be2b79e52a0e2c03e821.1725349691.git.michal.simek@amd.com
3 months agoarm64: zynqmp: Add u-boot command to boot into recovery image
Prasad Kummari [Tue, 27 Aug 2024 11:55:30 +0000 (17:25 +0530)]
arm64: zynqmp: Add u-boot command to boot into recovery image

To boot into the firmware recovery tool, the user currently
needs to press a button on the board while powering the
system up. To simplify this process, a U-Boot command
was added to allow booting directly into the recovery tool.

For example:
ZynqMP> zynqmp reboot <multiboot offset in hex>

Co-develop-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Co-develop-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240827115529.2931334-1-prasad.kummari@amd.com
3 months agoxilinx: versal-net: fix no previous prototype for function warning.
Prasad Kummari [Thu, 5 Sep 2024 11:57:59 +0000 (17:27 +0530)]
xilinx: versal-net: fix no previous prototype for function warning.

Included the SPI header to resolve the no previous prototypes
for function. Removed unused mode variable.
sparse warnings
warning: no previous prototype for 'spi_get_env_dev'
[-Wmissing-prototypes]
warning: variable 'mode' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Link: https://lore.kernel.org/r/20240905115758.999936-1-prasad.kummari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
3 months agomtd: spi-nor: scale up timeout for full-chip erase
Venkatesh Yadav Abbarapu [Tue, 2 Jan 2024 12:53:03 +0000 (18:23 +0530)]
mtd: spi-nor: scale up timeout for full-chip erase

This patch fixes timeout issues seen on large NOR flash.
For full-chip erase, where we use the SPINOR_OP_CHIP_ERASE (0xc7)
opcode. Use a different timeout for full-chip erase than for other
commands.

 [Ported from Linux kernel commit
                09b6a377687b ("mtd: spi-nor: scale up timeout for
                               full-chip erase") ]

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
3 months agoMerge tag 'u-boot-imx-next-20240919' of https://gitlab.denx.de/u-boot/custodians...
Tom Rini [Thu, 19 Sep 2024 17:26:18 +0000 (11:26 -0600)]
Merge tag 'u-boot-imx-next-20240919' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22363

- Several updates to i.MX9 SOC and i.MX93 EVK.
- Power domain fixes.
- TRDC cleanup and update.
- MAC address layout update.
- Add support for the i.MX9301/9302 variants.
- Add runtime detection of voltage mode.
- Generalize some code for i.MX8M and i.MX9.
- Add support for Comvetia imx6q-lxr board.

3 months agoMerge tag 'fwu-next-19092024' of https://source.denx.de/u-boot/custodians/u-boot...
Tom Rini [Thu, 19 Sep 2024 17:25:26 +0000 (11:25 -0600)]
Merge tag 'fwu-next-19092024' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next

This PR contains various improvements in the A/B update logic for EFI

- Read both copies of metadata, in case one of the is corrupted
- Check the metadata version against the running firmware to make sure it's
  allowed
- Limit the use of a revert capsule if the board is on a trial state and
  make sure it's not applied if the max counter has expired

3 months agofwu: print a message if empty capsule checks fail
Sughosh Ganu [Mon, 9 Sep 2024 11:20:21 +0000 (16:50 +0530)]
fwu: print a message if empty capsule checks fail

When dealing with processing of the empty capsule, the capsule gets
applied only when the checks for the empty capsule pass. Print a
message to highlight if empty capsule checks fail, and return an error
value, similar to the normal capsules.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
3 months agofwu: do not allow capsule processing on exceeding Trial Counter threshold
Sughosh Ganu [Mon, 9 Sep 2024 11:20:20 +0000 (16:50 +0530)]
fwu: do not allow capsule processing on exceeding Trial Counter threshold

When in Trial State, the platform keeps a count of the number of times
it has booted in the Trial State. Once the threshold of the maximum
allowed count exceeds, the platform reverts to boot from a different
bank on subsequent boot, thus coming out of the Trial State. It is
expected that all the updated images would be accepted or rejected
while the platform is in Trial State. Put in checks so that it is not
possible to apply an empty capsule once the max Trial Count exceeds.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
3 months agofwu: add dependency checks for selecting FWU metadata version
Sughosh Ganu [Mon, 9 Sep 2024 11:20:19 +0000 (16:50 +0530)]
fwu: add dependency checks for selecting FWU metadata version

The FWU code supports both versions of the FWU metadata, i.e. v1 and
v2. A platform can then select one of the two versions through a
config symbol. Put a dependency in the FWU metadata version selection
config symbol to ensure that both versions of the metadata cannot be
enabled.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
3 months agofwu: check all images for transitioning out of Trial State
Sughosh Ganu [Mon, 9 Sep 2024 11:20:18 +0000 (16:50 +0530)]
fwu: check all images for transitioning out of Trial State

The platform transitions out of Trial State into the Regular State
only when all the images in the update bank have been accepted. Check
for this condition before transitioning out of Trial State.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
3 months agofwu: v1: do a version check for the metadata
Sughosh Ganu [Mon, 9 Sep 2024 11:20:17 +0000 (16:50 +0530)]
fwu: v1: do a version check for the metadata

Do a sanity check that the version of the FWU metadata that has been
read aligns with the version enabled in the image. This allows to
indicate an early failure as part of the FWU module initialisation.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
3 months agofwu: v2: try reading both copies of metadata
Sughosh Ganu [Mon, 9 Sep 2024 11:20:16 +0000 (16:50 +0530)]
fwu: v2: try reading both copies of metadata

In the version 2 of the FWU metadata, the metadata is broken into two
parts, a top-level structure, which provides information on the total
size of the structure among other things. Try reading the primary
partition first, and if that fails, try reading the secondary
partition. This will help in the scenario where the primary metadata
partition has been corrupted, but the secondary partition is intact.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
3 months agoimx6q-lxr: Add board support
Fabio Estevam [Sat, 14 Sep 2024 00:56:05 +0000 (21:56 -0300)]
imx6q-lxr: Add board support

Add support for the Comvetia i.MX6Q LXR2 board, which is
uses the Phytec PFLA02 SoM.

Based on the original work from Stefano Babic <sbabic@denx.de>.

The Phytec PFLA02 devicetrees are taken from kernel 6.11-rc7.

The imx6q-lxr.dts has been submitted upstream:

https://lore.kernel.org/linux-devicetree/20240913200906.1753458-3-festevam@gmail.com/

After it gets accepted in mainline (most likely in kernel 6.13),
the lxr2 board can then be switched to OF_UPSTREAM and these device trees
can be removed from U-Boot.

Signed-off-by: Fabio Estevam <festevam@denx.de>
3 months agoimx93_evk: add back Low drive mode ddr timing file
Peng Fan [Thu, 19 Sep 2024 04:01:39 +0000 (12:01 +0800)]
imx93_evk: add back Low drive mode ddr timing file

Add back low drive mode 1866mts ddr timing file, no need
CONFIG_IMX9_LOW_DRIVE_MODE anymore, using runtime selection.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx93_evk: Remove CONFIG_IMX9_LOW_DRIVE_MODE and ld defconfig
Peng Fan [Thu, 19 Sep 2024 04:01:38 +0000 (12:01 +0800)]
imx93_evk: Remove CONFIG_IMX9_LOW_DRIVE_MODE and ld defconfig

Remove unused CONFIG_IMX9_LOW_DRIVE_MODE kconfig and
imx93_11x11_evk_ld_defconfig.
Remove the ld timing file.
The LD mode support will be added back with runtime detection later.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx93_evk: spl: update pmic settings
Peng Fan [Thu, 19 Sep 2024 04:01:37 +0000 (12:01 +0800)]
imx93_evk: spl: update pmic settings

1. Use runtime voltage selection for LD/OD/ND mode.
2. According to latest PE/TE report, the voltages of VDD_SOC for
   LD and ND mode need add 50mv margin, so LD voltage is 0.75v->0.8v,
   ND voltage is 0.8v->0.85v.
3. Use TOFF_DEB to differentiate new trimmed pmic and old pmic

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx9: trdc: introduce trdc_mbc_blk_num
Peng Fan [Thu, 19 Sep 2024 04:01:36 +0000 (12:01 +0800)]
imx9: trdc: introduce trdc_mbc_blk_num

Add trdc_mbc_blk_num to get num blks in a MBC mem slot, then drop
the hardcoded value '40' for NIC OCRAM configuration.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx9: trdc: cleanup code
Peng Fan [Thu, 19 Sep 2024 04:01:35 +0000 (12:01 +0800)]
imx9: trdc: cleanup code

Replace magic number with meaningful macros.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx: Generalize fixup_thermal_trips
Peng Fan [Thu, 19 Sep 2024 04:01:34 +0000 (12:01 +0800)]
imx: Generalize fixup_thermal_trips

i.MX8M and i.MX9 have duplicated fixup_thermal_trips, so move it
to arch/arm/mach-imx/fdt.c to avoid duplicated code.

The critial temperature point for i.MX9 set to "maxc - 5" back to give
some margin.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx93: Add Low performance parts 9302/9301 support
Ye Li [Thu, 19 Sep 2024 04:01:33 +0000 (12:01 +0800)]
imx93: Add Low performance parts 9302/9301 support

Add support for iMX93 low performance parts 9302 and 9301 which
restrict to low drive voltage only.
The parts run A55 max speed at 900Mhz and M33 at 133Mhz, have NPU
and A55 core1 (9301) disabled.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx9: soc: Disable cpu1 for variants that only has one A55 core
Peng Fan [Thu, 19 Sep 2024 04:01:32 +0000 (12:01 +0800)]
imx9: soc: Disable cpu1 for variants that only has one A55 core

Disale CPU1 for i.MX93 variants that only has one A55 core and update
cooling maps.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx: Generalize disable_cpu_nodes
Peng Fan [Thu, 19 Sep 2024 04:01:31 +0000 (12:01 +0800)]
imx: Generalize disable_cpu_nodes

disable_cpu_nodes could be reused by i.MX9, so move disable_cpu_nodes
out from mach-imx/imx8m/soc.c to mach-imx/fdt.c and update
disable_cpu_nodes to make it easy to support different socs.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx8m: soc: Drop disable_pmu_cpu_nodes
Peng Fan [Thu, 19 Sep 2024 04:01:30 +0000 (12:01 +0800)]
imx8m: soc: Drop disable_pmu_cpu_nodes

i.MX8M use PPI for PMU interrupts, there is no reason to update
interrupt-affinity for PMU even interrupt-affinity was wrongly added
to device tree before.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx9: Add 233Mhz DDR PLL frequency
Ye Li [Thu, 19 Sep 2024 04:01:29 +0000 (12:01 +0800)]
imx9: Add 233Mhz DDR PLL frequency

To support 1.866GTS LPDDR4x timing script, need to add 233Mhz freq
to DDR PLL for second mission point at 933MTS. Otherwise DDR training
will fail.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx9: soc: Mask the wdog reset in src by default on i.mx9
Jacky Bai [Thu, 19 Sep 2024 04:01:28 +0000 (12:01 +0800)]
imx9: soc: Mask the wdog reset in src by default on i.mx9

Normally, the wdog will be used for trigger external PMIC reset
through the WDOG_ANY pin. If the PMIC chip has debounce logic for
the reset signal, in some corner case the wdog can NOT trigger
external PMIC reset if the SoC has been reset internal before the
PMIC captures the WDOG_ANY pin reset, so need to keep the WDOG3-5
reset masked in the SRC to let the PMIC to do the reset safely.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx9: clock: Update clock init function and sequence
Ye Li [Thu, 19 Sep 2024 04:01:27 +0000 (12:01 +0800)]
imx9: clock: Update clock init function and sequence

Since we use SPEED GRADE fuse to set A55 frequency, remove the
set_arm_core_low_drive_clk function which has hard coded frequency.
And adjust clock_init called sequence and split it to early and late
functions.
Set the authen register in early function, because CCF driver checks
NS bit.
Set bus and core clock in late function, because the fuse read and
SoC type/rev depend on ELE.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx9: soc: Add function to get target voltage mode
Ye Li [Thu, 19 Sep 2024 04:01:26 +0000 (12:01 +0800)]
imx9: soc: Add function to get target voltage mode

Replace the static CONFIG_IMX9_LOW_DRIVE_MODE with runtime target
voltage mode by checking the part's SPEED GRADE fuse.
SPL will configure to highest A55 speed which is indicated by the SPEED
fuse and select corresponding voltage mode.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx9: soc: Print ELE information
Peng Fan [Thu, 19 Sep 2024 04:01:25 +0000 (12:01 +0800)]
imx9: soc: Print ELE information

The boot image includes Edgelock Enclave(ELE) Firmware. Print the
information out to let user know which version firmware is being used.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx9: soc: Change second Ethernet MAC fuse layout
Ye Li [Thu, 19 Sep 2024 04:01:24 +0000 (12:01 +0800)]
imx9: soc: Change second Ethernet MAC fuse layout

The second Ethernet MAC (eQOS) fuse layout is changed since i.MX93 A1
following other i.MX platforms, for example i.MX8MP.

Order for A0:
MAC1_ADDR[15:0]
MAC1_ADDR[31:16]
MAC1_ADDR[47:32]
MAC2_ADDR[47:32]
MAC2_ADDR[15:0]
MAC2_ADDR[31:16]

Order since A1:
MAC1_ADDR[15:0]
MAC1_ADDR[31:16]
MAC1_ADDR[47:32]
MAC2_ADDR[15:0]
MAC2_ADDR[31:16]
MAC2_ADDR[47:32]

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx9: soc: Change FSB directly access to fuse API
Peng Fan [Thu, 19 Sep 2024 04:01:23 +0000 (12:01 +0800)]
imx9: soc: Change FSB directly access to fuse API

To support OSCCA enabled part which has disabled FSB access from SOC,
change directly read from FSB to use fuse_read API.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx9: soc: Print UID in big endian format for EL2GO
Ye Li [Thu, 19 Sep 2024 04:01:22 +0000 (12:01 +0800)]
imx9: soc: Print UID in big endian format for EL2GO

Print UID in big endian format and as one buffer of bytes, so customer
can directly use it for EdgeLock 2GO.

Before:
UID: 0xf6c8ae93 0x0f46b326 0x10d61eb3 0x0583c2d2

Become:
UID: 93aec8f626b3460fb31ed610d2c28305

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx9: soc: imx9: soc: Align UID endianness with ROM
Frank Li [Thu, 19 Sep 2024 04:01:21 +0000 (12:01 +0800)]
imx9: soc: imx9: soc: Align UID endianness with ROM

ROM use UID[0] and UID[1] as serial number with big endian when usb serial
download.

After update this, uuu(>1.6) can use below command to filter out devices
when multi boards connected.

uuu -ms <serial#> ...

[sudo] uuu -lsusb can list known devices with serial# informaiton.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoimx9: soc: Configure TRDC for M33 TCM access
Ye Li [Thu, 19 Sep 2024 04:01:20 +0000 (12:01 +0800)]
imx9: soc: Configure TRDC for M33 TCM access

On OSCCA part, M33 TCM is used for ROM PATCH and protected by ELE ROM.
So after release TRDC, we need to configure TRDC for M33 TCM,
otherwise A55 can't access the TCM.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
3 months agoimx9: soc: wait ssar when power on power domain
Peng Fan [Thu, 19 Sep 2024 04:01:19 +0000 (12:01 +0800)]
imx9: soc: wait ssar when power on power domain

SSAR handshake done means power on finished, not ISO done. so correct
the waiting mask.

Fixes: 0256577a83b ("imx: imx9: Add MIX power init")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 months agoMerge patch series "Fix various bugs"
Tom Rini [Wed, 18 Sep 2024 19:07:19 +0000 (13:07 -0600)]
Merge patch series "Fix various bugs"

Simon Glass <sjg@chromium.org> says:

This series includes the patches needed to make make the EFI 'boot' test
work. That test has now been split off into a separate series along with
the EFI patches.

This series fixes these problems:
- sandbox memory-mapping conflict with PCI
- the fix for that causes the mbr test to crash as it sets up pointers
  instead of addresses for its 'mmc' commands
- the mmc and read commands which cast addresses to pointers
- a tricky bug to do with USB keyboard and stdio
- a few other minor things

3 months agotest: mbr: Drop a duplicate test
Simon Glass [Sun, 1 Sep 2024 22:26:34 +0000 (16:26 -0600)]
test: mbr: Drop a duplicate test

The test currently runs twice as it is declared twice. Unwind this.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agotest: mbr: Use RAM for the buffers
Simon Glass [Sun, 1 Sep 2024 22:26:33 +0000 (16:26 -0600)]
test: mbr: Use RAM for the buffers

The normal approach with sandbox is to use a fixed memory address in the
RAM, to avoid needing to create a map for transient local variables.

Update this test to use this approach.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agotest: mbr: Use a constant for the block size
Simon Glass [Sun, 1 Sep 2024 22:26:32 +0000 (16:26 -0600)]
test: mbr: Use a constant for the block size

It isn't that important to factor out constants in tests, but in this
case we have 0x200 and 512 used. The commands don't use the constant
as they use a block count ('1'). It doesn't create more code to use a
constant, so create one.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agotest: mbr: Unmap the buffers after use
Simon Glass [Sun, 1 Sep 2024 22:26:31 +0000 (16:26 -0600)]
test: mbr: Unmap the buffers after use

This tests maps some local variables into sandbox's address space. Make
sure to unmap them afterwards.

Note that the normal approach with sandbox is to use a fixed memory
address in the RAM, to avoid needing to create a map for transient local
variables.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 04291ee0aba ("cmd: mbr: Allow 4 MBR partitions without need...")
3 months agocmd: Fix memory-mapping in cmp command
Simon Glass [Sun, 1 Sep 2024 22:26:30 +0000 (16:26 -0600)]
cmd: Fix memory-mapping in cmp command

This unmaps a different address from what was mapped. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agoread: Tidy up use of map_sysmem() in the read command
Simon Glass [Sun, 1 Sep 2024 22:26:29 +0000 (16:26 -0600)]
read: Tidy up use of map_sysmem() in the read command

Rename the variable to 'ptr' since it is a pointer, not an address. Make
sure to unmap the pointer.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agommc: Use map_sysmem() with buffers in the mmc command
Simon Glass [Sun, 1 Sep 2024 22:26:28 +0000 (16:26 -0600)]
mmc: Use map_sysmem() with buffers in the mmc command

The current implementation casts an address to a pointer. Make it more
sandbox-friendly by using map_sysmem().

Rename the variable to 'ptr' since it is a pointer, not an address.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agosandbox: Implement reference counting for address mapping
Simon Glass [Sun, 1 Sep 2024 22:26:27 +0000 (16:26 -0600)]
sandbox: Implement reference counting for address mapping

An address may be mapped twice and unmapped twice. Delete the mapping
only when the last user unmaps it.

Fix a missing comment while here.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agosandbox: Add some debugging to pci_io
Simon Glass [Sun, 1 Sep 2024 22:26:26 +0000 (16:26 -0600)]
sandbox: Add some debugging to pci_io

Add a little debugging to this driver. Convert the existing debugging to
use logging.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agosandbox: Unmap old tags
Simon Glass [Sun, 1 Sep 2024 22:26:25 +0000 (16:26 -0600)]
sandbox: Unmap old tags

So far unmapping has not been implemented. This means that if one test
maps a pointer to an address with map_sysmem(), then a second test can
use that same pointer, by mapping the address back to a pointer with
map_to_sysmem(). This is not really desirable, even if it doesn't
cause any problems at the moment.

Implement unmapping, to clean this up.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agosandbox: Update cpu to use logging
Simon Glass [Sun, 1 Sep 2024 22:26:24 +0000 (16:26 -0600)]
sandbox: Update cpu to use logging

Use log_debug() instead of including the function name in the string.
Add one more debug for PCI.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agosandbox: Change the range used for memory-mapping tags
Simon Glass [Sun, 1 Sep 2024 22:26:23 +0000 (16:26 -0600)]
sandbox: Change the range used for memory-mapping tags

Sandbox keeps a table of addresses which map to pointers which are
outside its emulated DRAM. The current range from 10000000 conflicts
with the PCI range, meaning that if PCI mapping is on, that particular
address can be decoded by PCI instead of the table.

Fix this by moving the range up to the top of memory. Update the docs
while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agotest: mbr: Adjust test to drop 0x
Simon Glass [Sun, 1 Sep 2024 22:26:22 +0000 (16:26 -0600)]
test: mbr: Adjust test to drop 0x

U-Boot commands typically don't need 0x to specify hex, since they use
hex by default. Adding 0x in this test is confusing since it suggests
that it is necessary. Drop it from the file.

Also use the %#x construct to get the 0x when needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agotest: mbr: Adjust test to use lower-case hex
Simon Glass [Sun, 1 Sep 2024 22:26:21 +0000 (16:26 -0600)]
test: mbr: Adjust test to use lower-case hex

Switch to lower-case hex which is more commonly used in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agodm: usb: Deal with USB keyboard persisting across tests
Simon Glass [Sun, 1 Sep 2024 22:26:20 +0000 (16:26 -0600)]
dm: usb: Deal with USB keyboard persisting across tests

Clear any USB-keyboard devices before running a unit test, to avoid
using a stale udevice pointer in stdio. Add a long comment to explain
this situation and why this solution seems best, at least for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agousb: Add DEV_FLAGS_DM to stdio for USB keyboard
Simon Glass [Sun, 1 Sep 2024 22:26:19 +0000 (16:26 -0600)]
usb: Add DEV_FLAGS_DM to stdio for USB keyboard

This device contains a pointer to struct udevice so set the flag
indicating that, just to be tidy.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agolog: Add a new log category for the console
Simon Glass [Sun, 1 Sep 2024 22:26:18 +0000 (16:26 -0600)]
log: Add a new log category for the console

Add a new category which covers the console, including the stdio
drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agousb: Drop old non-DM code
Simon Glass [Sun, 1 Sep 2024 22:26:17 +0000 (16:26 -0600)]
usb: Drop old non-DM code

The driver model deadline for USB was in 2019, so drop the old USB
keyboard code, to avoid needing to deal with the extra code path.

Drop the unnecessary #ifdef around USB_KBD_BOOT_REPORT_SIZE while we
are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agobootstd: Create a function to reset USB
Simon Glass [Sun, 1 Sep 2024 22:26:16 +0000 (16:26 -0600)]
bootstd: Create a function to reset USB

Set up a function for this, since it needs to be used from multiple test
files.

This test file is only used on sandbox, where USB is enabled, so drop
the local declaration of usb_started

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agoscripts: Update pylint.base
Simon Glass [Sun, 1 Sep 2024 22:26:15 +0000 (16:26 -0600)]
scripts: Update pylint.base

There have been quite a few changes in the Python scripts, so update the
pylint baseline.

This was created using:

   make pylint
   cp pylint.cur scripts/pylint.base

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agotest/py: Fix some pylint warnings in test_ut.py
Simon Glass [Sun, 1 Sep 2024 22:26:14 +0000 (16:26 -0600)]
test/py: Fix some pylint warnings in test_ut.py

Tidy up most of these warnings. Remaining are four of these:

   R0914: Too many local variables

which can only by fixed by splitting things into functions, so that is
left for another time.

Part of this change was done by the flynt tool.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agonvmxip: Avoid probing on boot
Simon Glass [Sun, 1 Sep 2024 22:26:13 +0000 (16:26 -0600)]
nvmxip: Avoid probing on boot

Devices should be probed when they are used, not before. Drop this
boot-time probing.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agonvmxip: Drop the message on probe
Simon Glass [Sun, 1 Sep 2024 22:26:12 +0000 (16:26 -0600)]
nvmxip: Drop the message on probe

We should not need to announce this device. Drop the message.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 months agocmd: osd: Depend on OSD
Marek Vasut [Fri, 6 Sep 2024 17:12:23 +0000 (19:12 +0200)]
cmd: osd: Depend on OSD

The OSD command calls functions from video_osd-uclass.o ,
which is built only when CONFIG_OSD is enabled. Add the
missing dependency into Kconfig.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
3 months agocmd: mmc: Allow using partition name in mmc erase command
Tomas Paukrt [Mon, 2 Sep 2024 18:49:17 +0000 (20:49 +0200)]
cmd: mmc: Allow using partition name in mmc erase command

The mmc erase command currently requires blk# and cnt parameters
which can be obtained using the part start and part size commands
if the entire partition needs to be erased.

Simplify the use of the mmc erase command by allowing the partition
name to be specified directly.

Signed-off-by: Tomas Paukrt <tomaspaukrt@email.cz>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
3 months agommc: Hide mmc speed command under mmc command
Marek Vasut [Mon, 2 Sep 2024 13:37:09 +0000 (15:37 +0200)]
mmc: Hide mmc speed command under mmc command

The mmc speed command configuration option keeps showing up in
Kconfig directly in 'Command line interface'. Move MMC_SPEED_MODE_SET
under CMD_MMC to make it show up alongside the MMC command.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
3 months agoMerge patch series "Arm: npcm: modify npcm8xx boot setting"
Tom Rini [Mon, 16 Sep 2024 22:43:53 +0000 (16:43 -0600)]
Merge patch series "Arm: npcm: modify npcm8xx boot setting"

Jim Liu <jim.t90615@gmail.com> says:

Modify npcm8xx new boot design.
Correct memory setting and set gpio default value.

3 months agopinctrl: npcm8xx: clear all gpio events
Stanley Chu [Wed, 4 Sep 2024 02:41:06 +0000 (10:41 +0800)]
pinctrl: npcm8xx: clear all gpio events

Clear all gpio events to avoid unexpected interrupts
during kernel booting.

Signed-off-by: Stanley Chu <yschu@nuvoton.com>
3 months agoconfigs: arbel_evb: change env offset and boot address
Jim Liu [Wed, 4 Sep 2024 02:41:05 +0000 (10:41 +0800)]
configs: arbel_evb: change env offset and boot address

Change env offset and boot address for new design.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
3 months agoboard: arbel: correct the dram bank size
Jim Liu [Wed, 4 Sep 2024 02:41:04 +0000 (10:41 +0800)]
board: arbel: correct the dram bank size

If CONFIG_SYS_MEM_TOP_HIDE is defined, gd->ram_size is reduced by
CONFIG_SYS_MEM_TOP_HIDE. Need to correct the actual ram size in
dram_init_banksize.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
3 months agodrivers/crypto: aspeed: Add Caliptra SHA ACC support
Chia-Wei Wang [Fri, 30 Aug 2024 07:23:34 +0000 (15:23 +0800)]
drivers/crypto: aspeed: Add Caliptra SHA ACC support

Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which
export a SHA accelerator interface for SoC to use.

Note that CPTRA 1.0 supports only SHA384 and SHA512 and this
patch is verified by the 'hash test sha384/sha512' commands.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
3 months agoMerge tag 'v2024.10-rc5' into next
Tom Rini [Mon, 16 Sep 2024 20:48:13 +0000 (14:48 -0600)]
Merge tag 'v2024.10-rc5' into next

Prepare v2024.10-rc5