Marek Vasut [Fri, 6 Mar 2020 20:52:21 +0000 (21:52 +0100)]
ARM: socfpga: Enable DM RTC bootcount on ABB SECU1
Add and enable RTC-backed boot counter on ABB SECU1 platform.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Refactor the printing sequence in dm_dump_drivers to make it more clear.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Cc: Sean Anderson <seanga2@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Mon, 6 Apr 2020 12:29:44 +0000 (14:29 +0200)]
usb: Keep async schedule running only across mass storage xfers
Rather than keeping the asynchronous schedule running always, keep it
running only across USB mass storage transfers for now, as it seems
that keeping it running all the time interferes with certain control
transfers during device enumeration.
Note that running the async schedule all the time should not be an
issue, especially on EHCI HCD, as that one implements most of the
transfers using async schedule.
Note that we have usb_disable_asynch(), which however is utterly broken.
The usb_disable_asynch() blocks the USB core from doing async transfers
by setting a global flag. The async schedule should however be disabled
per USB controller. Moreover, setting a global flag does not prevent the
controller from using the async schedule, which e.g. the EHCI HCD does.
This patch implements additional callback to the controller, which
permits it to lock the async schedule and keep it running across
multiple transfers. Once the schedule is unlocked, it must also be
disabled. This thus prevents the async schedule from running outside
of the USB mass storage transfers.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Lukasz Majewski <lukma@denx.de> Cc: Tom Rini <trini@konsulko.com> Tested-by: Tom Rini <trini@konsulko.com> [omap3_beagle, previously failing]
Ye Li [Thu, 9 Apr 2020 08:44:43 +0000 (01:44 -0700)]
imx: Fix imx8m FIT script issue
The FIT config node has reversed ATF and u-boot: ATF is set to 'firmware' but
u-boot is set to 'loadables'.
This script can work previously because spl fit driver wrongly appends fdt to
all loadable images. With the issue fixed in commit 9d15d1d1c24f ("Revert
"common: spl_fit: Default to IH_OS_U_BOOT if FIT_IMAGE_TINY enabled"") the
u-boot in 'loadables' does not have fdt appended and fails to work. So correct
the script by moving u-boot to 'firmware' and ATF to 'loadables'.
Signed-off-by: Ye Li <ye.li@nxp.com> Reported-by: Matt Porter <mporter@konsulko.com> Tested-by: Matt Porter <mporter@konsulko.com>
Stefan Roese [Thu, 13 Feb 2020 06:04:00 +0000 (07:04 +0100)]
mips: cmd: go: Flush cache before jumping to app/image
It has been noticed on MT7628/88 platforms, that booting the RAM image
does not work reliably. Sometimes it works and sometimes not. Debugging
showed that this "might" be a cache related issue as very strange
errors occurred (e.g. output corrupted etc).
This patch adds a cache flush for the complete SDRAM area to the go cmd
before jumping to the entry point for the MIPS architecture. The
complete area is flushed as we don't know at this point, how big the
area of the "application" really is.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Mauro Condarelli <mc5686@mclink.it> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Mauro Condarelli <mc5686@mclink.it> Cc: Weijie Gao <weijie.gao@mediatek.com>
Lars Povlsen [Thu, 6 Feb 2020 09:45:40 +0000 (10:45 +0100)]
mips: vcoreiii: Fix cache coherency issues
This patch fixes an stability issue seen on some vcoreiii targets,
which was root caused to a cache inconsistency situation.
The inconsistency was caused by having kuseg pointing to NOR area but
used as a stack/gd/heap area during initialization, while only
relatively late remapping the RAM area into kuseg position.
The fix is to initialize the DDR right after the TLB setup, and then
remapping it into position before gd/stack/heap usage.
Lars Povlsen [Thu, 6 Feb 2020 09:43:18 +0000 (10:43 +0100)]
mips: vcoreiii: Ajust CONFIG_SYS_MEMTEST_END
This patch ajust CONFIG_SYS_MEMTEST_END for vcoreiii-based systems to
avoid overwriting the relocated u-boot. The former setting was too
agressive with networking etc. enabled on some platforms.
Code sections should be syntax highlighted as bash.
Comment lines in code should start with a hash sign ('#') but code lines
should not.
Most commands can be executed as normal users. Prepend those commands
requiring elevated authorization with 'sudo'.
dd does not have a parameter cout.
sfdisk does not have a -C parameter on Debian Buster.
Provide the necessary input to sfdisk.
Creating a partition of length zero makes no sense.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Sean Anderson [Mon, 6 Apr 2020 14:23:09 +0000 (10:23 -0400)]
cmd: Add test and fix bugs for dm drivers
Add a test for the dm drivers command. Also fix a null pointer dereference
revealed by said test.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Igor Opaniuk [Fri, 27 Mar 2020 10:28:16 +0000 (12:28 +0200)]
ARM: dts: imx8qxp-colibri: dm-pre-proper for pd_dma nodes
pd_dma_* nodes should be accessible during pre-relocation stage of
U-Boot proper for properly handling power domains.
This fixes the issue with permanent failing of invocation of
power_domain_get_by_index() in the common code of DM power domain
uclass (drivers/power/domain/power-domain-uclass.c).
Fixes: f0cc4eae9a ("core: device: use dev_power_domain_on") Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Igor Opaniuk [Fri, 27 Mar 2020 10:28:15 +0000 (12:28 +0200)]
ARM: dts: imx8qm-apalis: dm-pre-proper for pd_dma nodes
pd_dma_* nodes should be accessible during pre-relocation stage of
U-Boot proper for properly handling power domains.
This fixes the issue with permanent failing of invocation of
power_domain_get_by_index() in the common code of DM power domain
uclass (drivers/power/domain/power-domain-uclass.c).
Fixes: f0cc4eae9a ("core: device: use dev_power_domain_on") Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Igor Opaniuk [Fri, 27 Mar 2020 10:28:14 +0000 (12:28 +0200)]
ARM: dts: imx8qxp-colibri: replace dm-spl with dm-pre-proper
For non-SPL/TPL setups dm-spl, dm-tpl, dm-pre-proper, dm-pre-reloc are
handled equally, forcing the nodes with these properties
to be accessible and device being probed
before pre-relocation of U-Boot proper (drivers/core/util.c):
bool ofnode_pre_reloc(ofnode node)
{
/* for SPL and TPL the remaining nodes after the fdtgrep 1st pass
* had property dm-pre-reloc or u-boot,dm-spl/tpl.
* They are removed in final dtb (fdtgrep 2nd pass)
*/
return true;
if (ofnode_read_bool(node, "u-boot,dm-pre-reloc"))
return true;
if (ofnode_read_bool(node, "u-boot,dm-pre-proper"))
return true;
/*
* In regular builds individual spl and tpl handling both
* count as handled pre-relocation for later second init.
*/
if (ofnode_read_bool(node, "u-boot,dm-spl") ||
ofnode_read_bool(node, "u-boot,dm-tpl"))
return true;
return false;
}
Howewer, to avoid confusion in future, replace dm-spl
`%s/dm-spl/dm-pre-proper/g` properties to dm-pre-proper
to explicitly state that they are handled during pre-relocation
stage of U-Boot proper.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Igor Opaniuk [Fri, 27 Mar 2020 10:28:13 +0000 (12:28 +0200)]
ARM: dts: imx8qm-apalis: replace dm-spl with dm-pre-proper
For non-SPL/TPL setups dm-spl, dm-tpl, dm-pre-proper, dm-pre-reloc are
handled equally, forcing the nodes with these properties
to be accessible and device being probed
before pre-relocation of U-Boot proper (drivers/core/util.c):
bool ofnode_pre_reloc(ofnode node)
{
/* for SPL and TPL the remaining nodes after the fdtgrep 1st pass
* had property dm-pre-reloc or u-boot,dm-spl/tpl.
* They are removed in final dtb (fdtgrep 2nd pass)
*/
return true;
if (ofnode_read_bool(node, "u-boot,dm-pre-reloc"))
return true;
if (ofnode_read_bool(node, "u-boot,dm-pre-proper"))
return true;
/*
* In regular builds individual spl and tpl handling both
* count as handled pre-relocation for later second init.
*/
if (ofnode_read_bool(node, "u-boot,dm-spl") ||
ofnode_read_bool(node, "u-boot,dm-tpl"))
return true;
return false;
}
Howewer, to avoid confusion in future, replace dm-spl
`%s/dm-spl/dm-pre-proper/g` properties to dm-pre-proper
to explicitly state that they are handled during pre-relocation
stage of U-Boot proper.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Chee Hong Ang [Mon, 9 Mar 2020 08:21:59 +0000 (01:21 -0700)]
clk: socfpga: Read the clock parent's register base in probe function
This commit (82de42fa14682d408da935adfb0f935354c5008f) calls child's
ofdata_to_platdata() method before the parent is probed in dm core.
This has caused the driver no longer able to get the correct parent
clock's register base in the ofdata_to_platdata() method because the
parent clocks will only be probed after the child's ofdata_to_platdata().
To resolve this, the clock parent's register base will only be retrieved
by the child in probe() method instead of ofdata_to_platdata().
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Thu, 2 Apr 2020 16:53:41 +0000 (18:53 +0200)]
ARM: dts: stm32: Temporarily drop cd-gpios from AV96 DT
The card-detect GPIO and any other GPIO access currently doesn't work in
U-Boot SPL on any STM32 platform and crashes the SPL. To work around this
problem on AV96 right before release, remove the cd-gpios from DT. This
patch must be reverted right after release, once the proper fix for the
GPIO driver, "gpio: stm32: support gpio ops in SPL", is applied.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Bin Meng [Sat, 4 Apr 2020 01:35:32 +0000 (18:35 -0700)]
serial: ns16550: Fix ordering of getting base address
Currently the driver gets ns16550 base address in the driver
probe() routine, which may potentially break any ns16550 wrapper
driver that does additional initialization before calling
ns16550_serial_probe().
Things are complicated that we need consider ns16550 devices on
both simple-bus and PCI bus. To fix the issue we move the base
address assignment for simple-bus ns16550 device back to the
ofdata_to_platdata(), and assign base address for PCI ns16550
device in ns16550_serial_probe().
This is still not perfect. If any PCI bus based ns16550 wrapper
driver tries to access plat->base before calling probe(), it is
still subject to break.
Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Andy Shevchenko [Thu, 27 Feb 2020 14:00:51 +0000 (16:00 +0200)]
x86: acpi: Refactor XSDT handling in acpi_add_table()
There is no need to have an assignment to NULL for XSDT pointer.
Therefore, no need to assign it when rsdt_address is not set.
Because of above changes we may decrease indentation level as well.
While here, drop unnecessary parentheses.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Marek Vasut [Sat, 4 Apr 2020 13:01:22 +0000 (15:01 +0200)]
net: sh_eth: Init the hardware before PHY access
To access the PHY, the MAC registers must be initialized. Call the init
function in probe() to make it so, otherwise the PHY ID readout returns
all zeroes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Michal Simek [Mon, 30 Mar 2020 11:58:59 +0000 (13:58 +0200)]
arch: Add explicit linker script for u-boot-elf
Commit f4dc714aaa2d ("arm64: Turn u-boot.bin back into an ELF file after
relocate-rela")
introduce REMAKE_ELF option to recreate u-boot.elf from u-boot ->
u-boot.bin + DT -> u-boot.elf.
The best is to ilustrate it from make V=1 output
cat u-boot-nodtb.bin dts/dt.dtb > u-boot-dtb.bin
cp u-boot-dtb.bin u-boot.bin
aarch64-linux-gnu-objcopy -I binary -B aarch64 -O elf64-littleaarch64 u-boot.bin u-boot-elf.o
aarch64-linux-gnu-ld.bfd u-boot-elf.o -o u-boot.elf --defsym="_start"=0x8000000 -Ttext=0x8000000
Last command has no explicit linker script passed that's why toolchain
internal linker script is used.
In Binutils 2.32 case it contains SIZEOF_HEADERS symbol which has changed
behavior by commit
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=64029e93683a266c38d19789e780f3748bd6a188
which result in situation that program headers has changed from
(xilinx_zynqmp_mini_defconfig)
Program Headers:
Type Offset VirtAddr PhysAddr
FileSiz MemSiz Flags Align
LOAD 0x0000000000010000 0x00000000fffc0000 0x00000000fffc0000
0x0000000000018918 0x0000000000018918 RW 0x10000
to
Program Headers:
Type Offset VirtAddr PhysAddr
FileSiz MemSiz Flags Align
LOAD 0x0000000000000000 0x00000000fffb0000 0x00000000fffb0000
0x0000000000028918 0x0000000000028918 RW 0x10000
Xilinx tools like XSDB or Bootgen are using program headers for loading ELF
to the right location and by above binutils change ELF is loaded to
incorrect location.
The patch is explicitly use u-boot-elf.lds (just cat now) for u-boot.elf
recreation which is called when REMAKE_ELF is setup.
By purpose u-boot-elf.lds doesn't contain OUTPUT_FORMAT/OUTPUT_ARCH to be
able to use by all archs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-By: Álvaro Fernández Rojas <noltari@gmail.com>
mach-snapdragon: Fix overwriting last digit of serial number
When generating the MAC address based on the boards serial number
the last digit was overwritten with the null termination. That way
boards with serial numbers close to each other would use the same
MAC address.
Ye Li [Wed, 1 Apr 2020 14:42:04 +0000 (07:42 -0700)]
Revert "common: spl_fit: Default to IH_OS_U_BOOT if FIT_IMAGE_TINY enabled"
Commit cf8dcc5d02c3 ("common: spl_fit: Default to IH_OS_U_BOOT if
FIT_IMAGE_TINY enabled") is not correct, it will append fdt to each loadable
image. Actually when using TINY FIT, the first loadable image is thought as
u-boot and already have fdt appended.
Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Fabio Estevam <festevam@gmail.com>
Tom Warren [Fri, 28 Feb 2020 23:17:07 +0000 (16:17 -0700)]
ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support
The Jetson Nano Developer Kit is a Tegra X1-based development board. It
is similar to Jetson TX1 but it is not pin compatible. It features 4GB
of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot
used for storage.
HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
Ethernet controller provides onboard network connectivity. NVMe support
has also been added. Env save is at the end of QSPI (4MB-8K).
A 40-pin header on the board can be used to extend the capabilities and
exposed interfaces of the Jetson Nano.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
Tom Warren [Tue, 17 Mar 2020 00:01:43 +0000 (17:01 -0700)]
t210: Adjust ramdisk_addr_r/fdt_addr_r to allow for large kernels
The L4T kernel is 32MB+, and can overwrite the ramdisk/fdt loaded
from extlinux.conf. Adjust the load addresses to fix this for now.
Using the calculated_env addresses table from T186 U-Boot is a
better fix, but it isn't working correctly on T210 U-Boot right now,
so this will do until I can fix it.
Tom Warren [Fri, 20 Mar 2020 21:33:00 +0000 (14:33 -0700)]
qspi: t210: Use dev_read calls to get FDT data like base, freq
This Tegra QSPI driver hadn't been brought up to date with how
DM drivers are fetching data from the FDT now, and was pulling
in bogus data for base, max freq, etc. Fixed ofdata_to_platdata
to work the same way it does in the tegra114 SPI driver, using
dev_read_ functions.
Tom Warren [Mon, 25 Nov 2019 21:43:50 +0000 (14:43 -0700)]
qspi: t210: Fix QSPI clock and tap delays
When claim_bus was setting the clock, it reset the QSPI controller,
which wipes out any tap delays set by previous bootloaders (nvtboot,
CBoot for example on Nano). Instead of doing that in claim_bus, which
gets called a lot, moved clock setting to probe(), and set tap delays
there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env
save works reliably again.
Tom Warren [Tue, 12 Nov 2019 20:17:37 +0000 (13:17 -0700)]
qspi: t210: Fix claim_bus's use of the wrong bus/device
claim_bus() is passed a udevice *dev, which is the bus device's parent.
In this driver, claim_bus assumed it was the bus, which caused the
'priv' info pointer to be wrong, and periph_id was incorrect. This in
turn caused the periph clock call to assign the wrong clock (PLLM
instead of PLLP0), which caused a kernel warning. I only saw the 'bad'
periph_id when enabling DEBUG due to an assert. Not sure how QSPI was
working w/this errant clock, but it was moot as QSPI wasn't active
unless you probed it, and that wasn't happening until I posted a patch
to enable env save to QSPI for Nano (coming soon).
According to the HW team, for some reason the normal clock select code
picks what appears to be a perfectly valid 375KHz SD card clock, based
on the CAR clock source and SDMMC1 controller register settings (CAR =
408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register
divisor of 16 = 375KHz). But the resulting SD card clock, as measured by
the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the
values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR
clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on
T210 when the requested clock is <= 400KHz. Note that as far as I can
tell, the other requests for clocks in the Tegra MMC driver result in
valid SD clocks.
Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tom Warren [Wed, 29 May 2019 16:30:01 +0000 (09:30 -0700)]
mmc: t210: Add autocal and tap/trim updates for SDMMC1/3
As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and
autocal values need to be set to condition the signals correctly before
talking to the SD-card. This is the same as what's being done in CBoot,
but it gets reset when the SDMMC1 HW is soft-reset during SD driver
init, so needs to be repeated here. Also set autocal and tap/trim for
SDMMC3, although no T210 boards use it for SD-card at this time.
Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tom Warren [Thu, 26 Mar 2020 22:59:14 +0000 (15:59 -0700)]
tegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all Jetson boards
This allows the user to set $serverip in the environment before
executing a DHCP request. If they do, U-Boot will use that IP rather
than using the IP in the DHCP response.
Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
Vishruth [Thu, 26 Mar 2020 22:20:43 +0000 (15:20 -0700)]
ARM: tegra: p2771-0000: enable PIE relocation
U-Boot is configured to build as position independent executable. Enable
relocation of RELA section required to work with different load
addresses.
Signed-off-by: Vishruth <vishruthj@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Peter Robinson <probinson@gmail.com>
Tom Warren [Fri, 27 Mar 2020 17:24:31 +0000 (10:24 -0700)]
i2c: t210: Add VI_I2C clock source support
Fix VI_I2C clock source type. Will be needed by VI_I2C driver.
Also added use of INTERNAL_ID macro in two places, needed to keep
the id returned to 8 bits.
Tom Warren [Thu, 26 Mar 2020 23:10:11 +0000 (16:10 -0700)]
t210: pinmux: Remove pinmux/GPIO init from T210 boards
T210 CBoot is now doing the full pinmux and GPIO init, based on the DTB
tables. Remove pinmux/GPIO init tables & code from all T210-based builds
below:
p2371-2180 aka TX1
p2371-0000
e2220-1170
p2571
Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
JC Kuo [Thu, 26 Mar 2020 23:10:09 +0000 (16:10 -0700)]
t210: do not enable PLLE and UPHY PLL HW PWRSEQ
This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.
Adds call to board_cleanup_before_linux to facilitate this.
Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
Jagan Teki [Thu, 2 Apr 2020 11:41:25 +0000 (17:11 +0530)]
video: rockchip: Support 4K resolution for rk3399, HDMI
The default resolution for rockchip display is 1920x1080
which failed to work on 4K HDMI out displays on rk3399.
So, mark the default resolution as 3480x2160 for rk3399
HDMI out.
This would work all the hdmi display resolutions till
4K.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
Jagan Teki [Thu, 2 Apr 2020 11:41:23 +0000 (17:11 +0530)]
rockchip: Enable pre console for rk3399
Enable pre console buffer for rk3399 platform.
This would help to capture the console messages prior to
the console being initialised. Enabling this would help
to capture all the console messages on video output source
like HDMI. So we can find the full console messages of
U-Boot proper on HDMI display when enabled it for RK3399
platform boards.
Buffer address used for pre console is 0x0f200000 which is
ram base plus 240MiB. right now the Allwinner SoC is using
similar computation.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
here, HDMI interface has endpoint 1 in rk3288 and 2 in rk3399.
The rockchip vop driver often depends on this determined endpoint
number and stored in vop_mode. So based on this vop_mode the bpp
and pin polarity would configure on detected display interface.
Since, the existing driver using rk3288 vop mode settings enabling
the same will result wrong display interface configuration for rk3399.
Add the patch for fixing these vop modes for rk3399.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
Jagan Teki [Thu, 2 Apr 2020 11:41:21 +0000 (17:11 +0530)]
clk: rk3399: Set empty for vopl assigned-clocks
During vidconsole probe, the device probe will try to
check whether the assigned clocks on that video console
node is initialized or not? and return an error if not.
But, unlike Linux U-Boot won't require to handle these
vopl assigned-clocks since core clocks are enough to
handle the video out to process.
So, mark them as empty in set_rate to satisfy clk_set_defaults
so-that probe happened properly.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
Tudor Ambarus [Fri, 20 Mar 2020 09:37:59 +0000 (09:37 +0000)]
spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses
This feature should not be enabled in release but can be useful for
developers who need to monitor register accesses at some specific places.
Helped me identify a bug in u-boot, by comparing the register accesses
from the u-boot driver with the ones from its linux variant.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
[jagan: use 16 bit array with tmp variable] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tudor Ambarus [Fri, 20 Mar 2020 09:37:59 +0000 (09:37 +0000)]
spi: atmel-quadspi: fix possible MMIO window size overrun
The sama5d2 QSPI controller memory space is limited to 128MB:
0x9000_00000-0x9800_00000/0XD000_0000--0XD800_0000.
There are nor flashes that are bigger in size than the memory size
supported by the controller: Micron MT25QL02G (256 MB).
Check if the address exceeds the MMIO window size. An improvement
would be to add support for regular SPI mode and fall back to it
when the flash memories overrun the controller's memory space.
Simon Glass [Wed, 18 Mar 2020 17:44:03 +0000 (11:44 -0600)]
fit_check_sign: Allow selecting the configuration to verify
This tool always verifies the default configuration. It is useful to be
able to verify a specific one. Add a command-line flag for this and plumb
the logic through.
Simon Glass [Wed, 18 Mar 2020 17:44:02 +0000 (11:44 -0600)]
image: Load the correct configuration in fit_check_sign
At present bootm_host_load_images() is passed the configuration that has
been verified, but ignores it and just uses the default configuration.
This may not be the same.
Update this function to use the selected configuration.
Simon Glass [Wed, 18 Mar 2020 17:44:01 +0000 (11:44 -0600)]
image: Check hash-nodes when checking configurations
It is currently possible to use a different configuration's signature and
thus bypass the configuration check. Make sure that the configuration node
that was hashed matches the one being checked, to catch this problem.
Also add a proper function comment to fit_config_check_sig() and make it
static.
Simon Glass [Wed, 18 Mar 2020 17:44:00 +0000 (11:44 -0600)]
test: vboot: Parameterise the test
This test is actually made up of five separate tests. Split them out so
that they appear as separate tests.
Unfortunately this restarts U-Boot multiple times which adds about a
second to the already-long vboot test, about 8 seconds total on my
machine. We could add a special 'teardown' test afterwards but if the
tests are executed out of order that would not work.
Changing test_vboot into a class causes it not to be discovered and makes
it different from all other tests.
Simon Glass [Wed, 18 Mar 2020 17:43:57 +0000 (11:43 -0600)]
image: Return an error message from fit_config_verify_sig()
This function only returns an error message sometimes. Update it to always
return an error message if one is available. This makes it easier to see
what went wrong.
Marek Vasut [Tue, 31 Mar 2020 17:51:34 +0000 (19:51 +0200)]
ARM: dts: stm32: Repair PMIC configuration on AV96
The core and vdd PMIC buck regulators were misconfigured, which caused
instability of the board and malfunction of high-speed interfaces, like
the RGMII. Configure the PMIC correctly to repair these problems. Also,
model the missing Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
Marek Vasut [Tue, 31 Mar 2020 17:51:29 +0000 (19:51 +0200)]
ARM: dts: stm32: Use DT alias for the configuration EEPROM
Use DT /aliases node to establish a stable phandle to the configuration
EEPROM. This permits the configuration EEPROM to be moved e.g. to a
different address or a different bus. Adjust the board code to handle
new phandle lookup.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
Marek Vasut [Tue, 31 Mar 2020 17:51:27 +0000 (19:51 +0200)]
ARM: dts: stm32: Repair SDMMC2 operation
The eMMC uses different pinmux for the top four data lines, use such
a pinmux, otherwise it takes a very long time until the test for 8bit
operation times out. And this is the correct pinmux per schematic too.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
Marek Vasut [Tue, 31 Mar 2020 17:51:25 +0000 (19:51 +0200)]
ARM: dts: stm32: Repair SDMMC1 operation on AV96
The SD uses different pinmux for the D123DIRline, use such a pinmux,
otherwise there is a pinmux collision on the AV96. Add missing SD
voltage regulator switch and enable SDR104 operation.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41d9d4
("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{};
became pins1{};pins2{};, however the SPL extras were not updated to reflect
that change. Fix this.
This fixes booting from SD1 X9 slot on the AV96 board.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Fixes: 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
Tom Rini [Tue, 31 Mar 2020 19:10:54 +0000 (15:10 -0400)]
Merge tag 'arc-last-minute-fixes-for-2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-arc
This last minute pull-request is intended to fix some drivers
when used on ARC boards. The problem was introduced by
https://gitlab.denx.de/u-boot/u-boot/-/commit/07906b3dad157bd58411664bcc6a2a7976d5e0a9
What happened while doing one pretty simple improvement to make
U-Boot port more flexible and portable (by switching accessors from
assembly-written to plain C version) we implicitly added 2 problems:
1. Downgraded accessors from being volatile which signalled to
the compiler that it's now possible to do all kinds of optimizations
which may easily include merge of subsequent byte reads/writes into
word operations. Which is OK for accessing mormal memory but
breaks operation of peripherals if we access its memory-mapped regs
in such a "creative" manner.
2. As a part of assembly-written implementation we had compiler barriers
in form of the following construction 'asm volatile("" : : : "memory")',
and we dropped it in C implemntation. This in its turn enabled compiler
to mess with instruction ordering. Guess what it gives us in the end :)
So with all that we had in some corner-cases veeery funny instruction flows
generated. And in particular it broke DW SPI functionality when we were
writing large amount of data. Funny enough our tests which were writing
small amount of data still worked and only by the chance we caught that
breakage and unrolled that quite interesting loop of unexpected
problems.
The road to hell is paved with good intentions. Amen :)
Eugeniy Paltsev [Mon, 30 Mar 2020 19:44:45 +0000 (22:44 +0300)]
ARC: IO: add MB for __raw_* memory accessors
We add memory barriers for __raw_readX / __raw_writeX accessors same
way as it is done for readX and writeX accessors as lots of U-boot
driver uses __raw_readX / __raw_writeX instead of proper accessor
with barrier.
It will save us from lot's of debugging in the future and it is OK
as U-Boot is not that performance oriented as real run-time
software like OS or user bare-metal app so we may afford being not
super fast as we only being executed once.
Eugeniy Paltsev [Mon, 30 Mar 2020 19:44:43 +0000 (22:44 +0300)]
ARC: IO: add volatile to accessors
We must use 'volatile' in C-version read/write IO accessors
implementation to avoid merging several reads (writes) into
one read (write), or optimizing them out by compiler.
Fixes commit 07906b3dad15 ("ARC: Switch to generic accessors")
Michal Simek [Thu, 26 Mar 2020 14:01:29 +0000 (15:01 +0100)]
net: macb: Fix incorrect write function name when MACB_ZYNQ is enabled.
When MACB_ZYNQ is enabled there is compilation warnings
drivers/net/macb.c: In function ‘_macb_init’:
drivers/net/macb.h:675:33: error: ‘MACB_DMACFG’ undeclared (first use in this function);
did you mean ‘MACB_MCF’?
writel((value), (port)->regs + MACB_##reg)
^~~~~
It has been caused by changing macros name by commit below.
Fixes: 6c636514d499 ("net: macb: sync header definitions as taken from Linux") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Rasmus Villemoes [Tue, 11 Feb 2020 15:20:25 +0000 (15:20 +0000)]
mpc8xxx_spi: implement real ->set_speed
Not all boards have the same CSB frequency, nor do every SPI slave
necessarily support running at 16.7 MHz. So implement ->set_speed;
that also allows using a smaller PM (i.e., 0) for slaves that do
support a higher speed.
Based on work by Klaus H. Sørensen.
Cc: Klaus H. Sorensen <khso@prevas.dk> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Rasmus Villemoes [Tue, 11 Feb 2020 15:20:25 +0000 (15:20 +0000)]
mpc8xxx_spi: always use 8-bit characters, don't read or write garbage
There are a few problems with the current driver.
First, it unconditionally reads from dout/writes to din whether or not
those pointers are NULL. So for example a simple "sf probe" ends up
writing four bytes at address 0:
Finally, when the bitlen is 24 mod 32 (e.g. requesting to read 3 or 7
bytes), the last three bytes and up being the wrong ones, since the
driver does a full 32 bit read and then shifts the wrong byte out:
Fix all of that by always using a character size of 8, and reject
transfers that are not a whole number of bytes. While it ends being
more work for the CPU, we're mostly bounded by the speed of the SPI
bus, and we avoid writing to the mode register in every loop.
Based on work by Klaus H. Sørensen.
Cc: Klaus H. Sorensen <khso@prevas.dk> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
projects / u-boot.git / log