Wolfgang Denk [Sun, 20 May 2012 19:31:26 +0000 (21:31 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (167 commits)
OMAP4/5: Change omap4_sdp, omap4_panda, omap5_evm maintainer
ARM: omap3: Add CONFIG_SPL_BOARD_INIT for CONFIG_SPL_MMC_SUPPORT
ARM: omap3: Set SPL stack size to 8KB, image to 54KB.
arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx
OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device Tree
omap4: do not enable auxiliary cores
omap4: do not enable fs-usb module
omap4: panda: disable uart2 pads during boot
igep00x0: change mpurate from 500 to auto
igep00x0: enable the use of a plain text file
tegra2: trivially enable 13 mhz crystal frequency
tegra: Enable keyboard for Seaboard
tegra: Switch on console mux and use environment for console
tegra: Add tegra keyboard driver
tegra: fdt: Add keyboard definitions for Seaboard
tegra: fdt: Add keyboard controller definition
tegra: Add keyboard support to funcmux
input: Add support for keyboard matrix decoding from an fdt
input: Add generic keyboard input handler
input: Add linux/input.h for key code support
fdt: Add fdtdec functions to read byte array
tegra: Enable LP0 on Seaboard
tegra: fdt: Add EMC data for Tegra2 Seaboard
tegra: i2c: Add function to find DVC bus
fdt: tegra: Add EMC node to device tree
tegra: Add EMC settings for Seaboard
tegra: Turn off power detect in board init
tegra: Set up warmboot code on Nvidia boards
tegra: Setup PMC scratch info from ap20 setup
tegra: Add warmboot implementation
tegra: Set up PMU for Nvidia boards
tegra: Add PMU to manage power supplies
tegra: Add EMC support for optimal memory timings
tegra: Add header file for APB_MISC register
tegra: Add tegra_get_chip_type() to detect SKU
tegra: Add flow, gp_padctl, fuse, sdram headers
tegra: Add crypto library for warmboot code
tegra: Add functions to access low-level Osc/PLL details
tegra: Move ap20.h header into arch location
Add AES crypto library
i2c: Add TPS6586X driver
Add abs() macro to return absolute value
fdt: Add function to return next compatible subnode
fdt: Add function to locate an array in the device tree
i.MX28: Avoid redefining serial_put[cs]()
i.MX28: Check if WP detection is implemented at all
i.MX28: Add battery boot components to SPL
i.MX28: Reorder battery status functions in SPL
i.MX28: Add LRADC init to i.MX28 SPL
i.MX28: Add LRADC register definitions
i.MX28: Shut down the LCD controller before reset
i.MX28: Add LCDIF register definitions
i.MX28: Implement boot pads sampling and reporting
i.MX28: Improve passing of data from SPL to U-Boot
M28EVK: Add SD update command
M28EVK: Implement support for new board V2.0
FEC: Abstract out register setup
MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged
i.MX28: Add delay after CPU bypass is cleared
spi: mxs: Allow other chip selects to work
spi: mxs: Introduce spi_cs_is_valid()
mx53loco: Remove unneeded gpio_set_value()
mx53loco: Add CONFIG_REVISION_TAG
mx53loco: Turn on VUSB regulator
mx53loco: Add mc34708 support and set mx53 frequency at 1GHz
pmic: dialog: Avoid name conflicts
imx: Add u-boot.imx as target for ARM9 i.MX SOCs
i.MX2: Include asm/types.h in arch-mx25/imx-regs.h
imx: usb: There is no such register
i.MX25: usb: Set PORTSCx register
imx: nand: Support flash based BBT
i.MX25: This architecture has a GPIO4 too
i.MX25: esdhc: Add mxc_get_clock infrastructure
i.MX6: mx6q_sabrelite: add SATA bindings
i.MX6: add enable_sata_clock()
i.MX6: Add ANATOP regulator init
mx28evk: add NAND support
USB: ehci-mx6: Fix broken IO access
M28: Scan only first 512 MB of DRAM to avoid memory wraparound
Revert "i.MX28: Enable additional DRAM address bits"
M28: Enable FDT support
mx53loco: Add support for 1GHz operation for DA9053-based boards
mx53loco: Allow to print CPU information at a later stage
mx5: Add clock config interface
imx-common: Factor out get_ahb_clk()
i.MX6Q: mx6qsabrelite: Add keypress support to alter boot flow
mx31pdk: Allow booting a zImage kernel
mx6qarm2: Allow booting a zImage kernel
mx6qsabrelite: Allow booting a zImage kernel
mx28evk: Allow booting a zImage kernel
m28evk: Allow to booting a dt kernel
mx28evk: Allow to booting a dt kernel
mx6qsabrelite: No need to set the direction for GPIO3_23 again
pmic: Add support for the Dialog DA9053 PMIC
MX53: mx53loco: Add SATA support
MX53: Add support to ESG ima3 board
SATA: add driver for MX5 / MX6 SOCs
MX53: add function to set SATA clock to internal
SATA: check for return value from sata functions
MX5: Add definitions for SATA controller
NET: fec_mxc.c: Add a way to disable auto negotiation
Define UART4 and UART5 base addresses
EXYNOS: Change bits per pixel value proper for u-boot.
EXYNOS: support TRATS board display function
LCD: support S6E8AX0 amoled driver based on EXYNOS MIPI DSI
EXYNOS: support EXYNOS MIPI DSI interface driver.
EXYNOS: support EXYNOS framebuffer and FIMD display drivers.
LCD: add data structure for EXYNOS display driver
EXYNOS: add LCD and MIPI DSI clock interface.
EXYNOS: definitions of system resgister and power management registers.
SMDK5250: fix compiler warning
misc:pmic:samsung Convert TRATS target to use MAX8997 instead of MAX8998
misc:pmic:max8997 MAX8997 support for PMIC driver
TRATS: modify the trats's configuration
ARM: Exynos4: ADC: Universal_C210: Enable LDO4 power line for ADC measurement
EXYNOS: Rename exynos5_tzpc structure to exynos_tzpc
arm: ea20: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
arm: cam_enc_4xx: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
cm-t35: add I2C multi-bus support
include/configs: Remove CONFIG_SYS_64BIT_STRTOUL
include/configs: Remove CONFIG_SYS_64BIT_VSPRINTF
omap3: Introduce weak misc_init_r
omap730p2: Remove empty misc_init_r
omap5912osk: Remove empty misc_init_r
omap4+: Remove CONFIG_ARCH_CPU_INIT
omap4: Remove CONFIG_SYS_MMC_SET_DEV
OMAP3: pandora: drop console kernel argument
OMAP3: pandora: revise GPIO configuration
...
Wolfgang Denk [Sun, 20 May 2012 19:20:50 +0000 (21:20 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-mmc
* 'master' of git://git.denx.de/u-boot-mmc:
ARM: SAMSUNG: support sdhci controller
mmc: support the sdhci instead of s5p_mmc for samsung-soc
mmc: add the quirk to use the sdhci for samsung-soc
mmc: sdhci: add the quirk for broken r1b response
i.MX28: Lower the amount of blocks transfered in one DMA cycle
mmc: fsl_esdhc: Poll until card is not busy anymore
include/mmc.h: remove struct mmc_csd
mmc: omap: handle controller errors properly
mmc: omap: improve stat wait message
mmc: omap: follow TRM procedure to power on cards
mmc:fix: Set mmc width according to MMC host capabilities
Andy Fleming [Wed, 9 May 2012 20:36:28 +0000 (20:36 +0000)]
Improve MAKEALL parallel builds
The patch that added parallel builds broke MAKEALL -l, so this
fixes that. At the same time, it improves the termination so
that it shuts down the build threads if you cancel the build.
Lastly, it removes a bunch of debug code.
Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Wolfgang Denk <wd@denx.de>
Andy Fleming [Wed, 25 Apr 2012 09:36:13 +0000 (09:36 +0000)]
Remove extra boards from LIST_ixp
pdnb3 and scpu are explicitly on LIST_ixp, even though they are
also specified in boards.cfg as having cpu ixp. This means that
they will be built twice when doing ./MAKEALL ixp, or ./MAKEALL arm.
This was pointless before, but actually breaks things if you launch
both builds at the same time, as they overwrite each other.
Signed-off-by: Andy Fleming <afleming@freescale.com>
The reason for above message is that when booting from MMC, I2C needs to
be initialized to talk with the TWL4030. On OMAP3 I2C is only
initalized in SPL if CONFIG_SPL_BOARD_INIT is set.
Cc: Thomas Weber <weber@corscience.de> Cc: Steve Sakoman <sakoman@gmail.com>
Original patch for Beagleboard is: Signed-off-by: Peter Meerwald <p.meerwald@bct-electronic.com>
Extended to cover all other boards: Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 8 May 2012 07:29:31 +0000 (07:29 +0000)]
ARM: omap3: Set SPL stack size to 8KB, image to 54KB.
With older toolchains it is possible to not fit entirely into the 45KB
that we had assigned to SPL. Adjust to allow for 8KB of stack (which
should be more than required) and 54KB of text/data.
Cc: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Thomas Weber <weber@corscience.de> Cc: Ilya Yanok <yanok@emcraft.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Vaibhav Hiremath <hvaibhav@ti.com>
Matt Porter [Mon, 7 May 2012 16:49:21 +0000 (16:49 +0000)]
arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx
In warm reset conditions on OMAP36xx/AM/DM37xx the rom code
incorrectly sets the DPLL4 clock input divider to /6.5 which
is an invalid value unless the input clock is 13MHz. When a JTAG
emulator is attached, a warm reset is necessary after the emulator
gains control of the process. This results in a loss of serial
output due to the invalid DPLL4 settings.
This patch fixes the issue by resetting the DPLL4 clock input
divider to /1 when the input clock is not 13MHz. AM/DM37x TRM
section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only
used when the input clock is 13MHz.
Jon Hunter [Tue, 1 May 2012 10:05:08 +0000 (10:05 +0000)]
OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device Tree
For OMAP4 boards, such as the panda-es, that have 1GB of memory the linux
kernel fails to locate the device tree blob on boot. The reason being is that
u-boot is copying the DT blob to the upper part of RAM when booting the kernel
and the kernel is unable to access the blob. By setting the fdt_high variable
to either 0xffffffff (to prevent the copy) or 0xac000000 (704MB boundary
of memory for OMAP4) the kernel is able to locate the DT blob and boot.
Based upon following patch by Dirk Behme set the fdt_high variable to allow
booting with device tree on OMAP4 boards.
"7e9603e i.mx6q: configs: Add fdt_high and initrd_high variables"
Cc: Sricharan R <r.sricharan@ti.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Tero Kristo [Wed, 25 Apr 2012 06:05:21 +0000 (06:05 +0000)]
omap4: do not enable auxiliary cores
Booting up these cores (dsp / ivahd / cortex-m3) is bad without
firmware running on them, and they will hang preventing any kind
of sleep transitions later on with the kernel.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: R Sricharan <r.sricharan@ti.com>
Tero Kristo [Wed, 25 Apr 2012 06:05:19 +0000 (06:05 +0000)]
omap4: panda: disable uart2 pads during boot
If uart2 is enabled during boot, spurious wifi chip transmission will
hang the module and it is impossible to recover from this situation
without hard reset. This will prevent any l4_per domain idle
transitions.
Using the new env import command it is possible to use plain text files instead
of script-images. Plain text files are much easier to handle.
E.g. If your boot.scr contains the following:
-----------------------------------
setenv dvimode 1024x768-16@60
run loaduimage
run mmcboot
-----------------------------------
you could create a file named uEnv.txt and use that instead of boot.scr:
-----------------------------------
dvimode=1024x768-16@60
uenvcmd=run loaduimage; run mmcboot
-----------------------------------
The variable uenvcmd (if existent) will be executed (using run) after uEnv.txt
was loaded. If uenvcmd doesn't exist the default boot sequence will be started,
therefore you could just use
-----------------------------------
dvimode=1024x768-16@60
-----------------------------------
as uEnv.txt because loaduimage and mmcboot is part of the default boot sequence
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
Add support for internal matrix keyboard controller for Nvidia Tegra
platforms. This driver uses the fdt decode function to obtain its key
codes.
Support for the Ctrl modifier is provided. The left and right ctrl keys are
dealt with in the same way.
This uses the new keyboard input library (drivers/input/input.c) to decode
keys and handle most of the common input logic. The new key matrix library
is also used to decode (row, column) key positions into key codes.
The intent is to make this driver purely about dealing with the hardware.
Key detection before the driver is loaded is supported. This key will be
picked up when the keyboard driver is initialized.
Modified by Bernie Thompson <bhthompson@chromium.org> and
Simon Glass <sjg@chromium.org> for device tree, input layer, key matrix
and various other things.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
input: Add support for keyboard matrix decoding from an fdt
Matrix keyboards require a key map to be set up, and must also deal with
key ghosting.
Create a keyboard matrix management implementation which can be leveraged
by various keyboard drivers. This includes code to read the keymap from
the FDT and perform debouncing.
Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Tue, 17 Apr 2012 09:01:30 +0000 (09:01 +0000)]
input: Add generic keyboard input handler
Add a module which understands converting key codes (or scan codes)
to ASCII characters. It includes FIFO support and can call back to
drivers to read new characters when its FIFO is empty.
Keycode maps are provided for un-modified, shift and ctrl keys.
The plan is to use this module where such mapping is required.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Jimmy Zhang [Tue, 10 Apr 2012 05:17:06 +0000 (05:17 +0000)]
tegra: Add EMC settings for Seaboard
Set Seaboard to optimal memory settings based on the SOC in use (T20 or T25).
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Wei Ni [Mon, 2 Apr 2012 13:18:58 +0000 (13:18 +0000)]
tegra: Turn off power detect in board init
Tegra core power rail has leakage voltage around 0.2V while system in
suspend mode. The source of the leakage should be coming from PMC power
detect logic for IO rails power detection.
That can be disabled by writing a '0' to PWR_DET_LATCH followed by writing '0'
to PWR_DET (APBDEV_PMC_PWR_DET_0).
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Jimmy Zhang [Mon, 2 Apr 2012 13:18:53 +0000 (13:18 +0000)]
tegra: Add PMU to manage power supplies
Power supplies must be adjusted in line with clock frequency. This code
provides a simple routine to set the voltage to allow operation at maximum
frequency.
- Split PMU code into separate TPS6586X driver
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Mon, 2 Apr 2012 13:18:50 +0000 (13:18 +0000)]
tegra: Add tegra_get_chip_type() to detect SKU
We want to know which type of chip we are running on - the Tegra
family has several SKUs. This can be determined by reading a
fuse register, so add this function to ap20.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Yen Lin [Mon, 2 Apr 2012 13:18:49 +0000 (13:18 +0000)]
tegra: Add flow, gp_padctl, fuse, sdram headers
These headers provide access to additional Tegra features.
flow - start/stop CPUs
sdram - parameters for SDRAM
fuse - access to on-chip fuses / security settings
gp_padctl - pad control and general purpose registers
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Mon, 2 Apr 2012 13:18:44 +0000 (13:18 +0000)]
i2c: Add TPS6586X driver
This power management chip supports battery charging and a large number
of power supplies. This initial driver only provides the ability to adjust
the two synchronous buck converters SM0 and SM1 in a stepwise manner.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Thu, 10 May 2012 11:37:35 +0000 (11:37 +0000)]
Add abs() macro to return absolute value
This macro is generally useful to make it available in common.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Tom Rini <trini@ti.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
Marek Vasut [Tue, 1 May 2012 11:09:47 +0000 (11:09 +0000)]
i.MX28: Shut down the LCD controller before reset
If the LCD controller is on before the CPU goes into reset, the traffic on LCDIF
data pins interferes with the BootROM's boot mode sampling. So shut the
controller down.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
Marek Vasut [Tue, 1 May 2012 11:09:44 +0000 (11:09 +0000)]
i.MX28: Improve passing of data from SPL to U-Boot
Pass memory size from SPL via structure located in SRAM instead of SCRATCH
registers. This allows passing more data about boot from SPL to U-Boot, like the
boot mode pads configuration.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
Stefano Babic [Wed, 9 May 2012 10:07:31 +0000 (12:07 +0200)]
MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged
After an update to the MX51 reference manual (Rev. 5), the
values of the PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH
are now clearly wrong:
"Bit 13:
High / Low Output Voltage Range. This bit selects the output voltage mode for
SD2_CMD. 0 High output voltage mode
1 Low output voltage mode"
The values are currently negated in code - fixed.
Reported-by: David Jander <david.jander@protonic.nl> Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Marek Vasut <marek.vasut@gmail.com> CC: David Jander <david.jander@protonic.nl> Acked-by: David Jander <david.jander@protonic.nl> Acked-by: Marek Vasut <marek.vasut@gmail.com>
Marek Vasut [Fri, 4 May 2012 01:32:50 +0000 (01:32 +0000)]
i.MX28: Add delay after CPU bypass is cleared
This solves issues when larger amount of DRAM is used, like 256MB.
Behave the same in case of CPU bypass as we do in case of EMI
bypass, but wait 15 ms. We need to wait until the clock domain
stabilizes.
This issue seemed to have been caused by not waiting after frobbing
with the CPU bypass, it was unrelated to memory, but had a direct
impact, causing trouble. This was yet another X-File of the
imx-bootlets, sigh. The conclusion is, trying a semi-random delay
(there is delay after the EMI bypass change), the issue is fixed.
Another possible explanation is that we do not do the "simple memory
test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of
the memory, while also outputing something on the serial port). This
might have caused the similar delay in the imx-bootlets and therefore
they didn't need to add this explicitly.
For now, this seems good fix enough, but to me, whole that memory
init code in imx-bootlets is completely flunked and it'd need deeper
investigation.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
Fabio Estevam [Tue, 8 May 2012 03:40:49 +0000 (03:40 +0000)]
mx53loco: Add CONFIG_REVISION_TAG
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information.
The kernel uses this data to distinguish between Dialog versus mc34708 based boards,
and also to distinguish between revA and revB of the mc34708 based boards.
Timo Ketola [Wed, 18 Apr 2012 22:55:34 +0000 (22:55 +0000)]
i.MX2: Include asm/types.h in arch-mx25/imx-regs.h
types.h must be included in imx-regs.h if one wants to include
imx-regs.h in a board configuration file. That for one's part is
necessary, if one wants to use addresses defined in imx-regs.h.
For example, fsl_esdhc.c needs CONFIG_SYS_FSL_ESDHC_ADDR defined and
a proper thing is to define it with IMX_MMC_SDHCx_BASE in board
configuration file. This patch fixes the build in that case.
Signed-off-by: Timo Ketola <timo@exertus.fi> Acked-by: Stefano Babic <sbabic@denx.de>
Timo Ketola [Wed, 18 Apr 2012 22:55:33 +0000 (22:55 +0000)]
imx: usb: There is no such register
The reference manual of i.MX25 (nor i.MX31) does not define such
register. This seems to access read only UH2_CAPLENGTH register (if
CONFIG_MXC_USB_PORT is zero).
Signed-off-by: Timo Ketola <timo@exertus.fi> Acked-by: Stefano Babic <sbabic@denx.de>
Timo Ketola [Wed, 18 Apr 2012 22:55:32 +0000 (22:55 +0000)]
i.MX25: usb: Set PORTSCx register
The USB controller in i.MX25 has a PORTSCx registers which should be
set. In this regard it is similar to the controller in i.MX31. As this
file is compiled only with i.MX25 and -31, #ifdef check can be removed.
Signed-off-by: Timo Ketola <timo@exertus.fi> Acked-by: Stefano Babic <sbabic@denx.de>
Dirk Behme [Wed, 2 May 2012 02:12:17 +0000 (02:12 +0000)]
i.MX6: Add ANATOP regulator init
Init the core regulator voltage to 1.2V. This is required for the correct
functioning of the GPU and when the ARM LDO is set to 1.225V. This is a
workaround to fix some memory clock jitter.
Note: This should be but can't be done in the DCD. The bootloader
prevents access to the ANATOP registers.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Jason Chen <b02280@freescale.com> CC: Jason Liu <r64343@freescale.com> CC: Ranjani Vaidyanathan <ra5478@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <festevam@gmail.com>
To get USB working again on the i.MX6, this patch fixes a bug introduced
with commit 522b2a0 "Add proper IO accessors for mx6 usb registers.".
At that occasion, I also added the missing __iomem directive.
Cc: Marek Vasut <marex@denx.de> CC: Fabio Estevam <festevam@gmail.com> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
Apparently, this commit got mainline only because of out-of-tree
port and causes breakage on board that is mainline. Revert.
Reason:
* The OOT board has 512MB of DRAM, enabling this additional address
line enabled it to work fine with 512MB of RAM.
* Every mainline port has max. 256MB of DRAM, therefore this revert
has no impact on any mainline port
* Though this caused a problem with new M28 board with 256MB of DRAM
where the chips are wired differently. The patch-to-be-reverted
caused the DRAM to behave like this:
Therefore to retain the current one-memory-init-rules-them-all situation,
revert this patch until another board emerges and will actually be pushed
mainline that needs different setup.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
mx53loco: Add support for 1GHz operation for DA9053-based boards
There are two types of mx53loco boards: initial boards were built with a Dialog
DA9053 PMIC and more recent version is based on a Freescale MC34708 PMIC.
Add DA9053 PMIC support and adjust the required voltages and clocks for running
the CPU at 1GHz.
Tested on both versions of mx53loco boards.
In the case of a MC34708-based board the CPU operating voltage remains at 800MHz.
mx53loco: Allow to print CPU information at a later stage
Print CPU information within board_late_init().
This is in preparation for adding 1GHz support, which requires programming a PMIC
via I2C. As I2C is only available after relocation, print the CPU information
later at board_late_init(), so that the CPU frequency can be printed correctly.
Add clock config interface support, so that we
can configure CPU or DDR clock in the later init
Signed-off-by: Jason Liu <jason.hui@linaro.org> Signed-off-by: Eric Miao <eric.miao@linaro.org> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
projects / u-boot.git / log