Hai Pham [Thu, 26 Jan 2023 20:01:48 +0000 (21:01 +0100)]
pinctrl: renesas: r8a7796: Add R8A77961 PFC support
R-Car M3-W+ (R8A77961) is pin compatible with R-Car M3-W (R8A77960),
which allows for both SoCs to share a driver.
Based on Linux commit 708c69e9eacc ("pinctrl: sh-pfc: r8a7796: Add
R8A77961 PFC support") and 74ce7a8044b0 ("pinctrl: renesas: r8a7796:
Optimize pinctrl image size for R8A774A1")
Parts picked from
pinctrl: renesas: Synchronize R-Car Gen2/Gen3 tables with Linux 5.18.3
- Add pin groups for the green and high8 subsets of the Video IN pins
- Add MediaLB pins
- Add bias support for various SoCs
- Share more pin group data, to reduce size and ease review
- Miscellaneous cleanups, fixes and improvements.
This contains port of Linux kernel commit 6210905586ae ("pinctrl: renesas: Add shorthand for reserved register fields")
to handle negative entries in GROUP() macros correctly.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This is only a copyright and SPDX identifier update, no
functional change.
The following script has been used for the synchronization:
$ for i in $(cd include/dt-bindings/clock/ ; ls -1 r8a*) ; do cp /linux-2.6/include/dt-bindings/clock/$i include/dt-bindings/clock/ ; done
$ for i in $(cd include/dt-bindings/power/ ; ls -1 r8a*) ; do cp /linux-2.6/include/dt-bindings/power/$i include/dt-bindings/power/ ; done
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Mario Kicherer [Wed, 1 Feb 2023 06:16:22 +0000 (14:16 +0800)]
armv7: ls102xa: make QSPI clock selection optional during SoC init
To improve startup times when booting from QSPI flash, the QSPI frequency
can be configured very early in the boot process [1] to reduce loading
times of U-Boot itself. This patch adds an option to disable setting the
frequency to a default value during SoC initialization.
Manoj Sai [Mon, 28 Nov 2022 11:45:31 +0000 (17:15 +0530)]
configs: imx8mp_evk: revert to old ram settings
The 'commit 864ac2cf383e ("board: imx8mp: Add Engicam
i.Core MX8M Plus EDIMM2.2 Starter Kit")' has changed the imx8mp evk ram
settings from 6GB ram to 2GB.
This changeset reverts the above change.
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reported-by : Peter Bergin <peter@berginkonsult.se> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Arnaud Ferraris [Thu, 15 Dec 2022 14:51:17 +0000 (15:51 +0100)]
imx8mq_pins: fix configuration for UART4 on ECSPI2 pads
When routing UART4 using the ECSPI2 pads, register
IOMUXC_UART4_RXD_SELECT_INPUT (offset 0x050C) should be changed only
when dealing with RX, as its name suggests.
Ye Li [Tue, 13 Dec 2022 04:08:02 +0000 (05:08 +0100)]
imx8: scu_api: sync sc_rm_is_pad_owned api change
SCFW has fixed a overflow issue in sc_rm_is_pad_owned API. This
requires u-boot to update API implementation, since it will cause
compatible issue. Otherwise all pad checking will have problem and
cause pad setting not continue.
Due to the compatible issue, the new u-boot only works with new
SCFW (API version: 1.21 and later).
old scfw + old u-boot: API overflow issue
old scfw + new u-boot, or new scfw + old u-boot: API compatible issue
new scfw + new u-boot: Working
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Jason Liu <Jason.hui.liu@nxp.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Adam Ford [Sat, 19 Nov 2022 19:30:08 +0000 (13:30 -0600)]
configs: imx8mn_beacon_fspi: Add config for booting from QSPI
The imx8mn-beacon SOM has a QSPI part on it connected to the
FlexSPI controller. Add a defconfig option which supports
booting from the QSPI NOR flash instead of sd/mmc.
Tim Harvey [Fri, 11 Nov 2022 16:03:07 +0000 (08:03 -0800)]
board: gateworks: venice: poll I2C lines to wait for GSC firmware
In some situations the GSC firmware where the EEPROM containing the
model and DRAM configuration may not be ready by the time the SoC
is ready to talk to it over I2C.
Instead of a hard delay, poll the I2C lines to wait until they are
released to avoid the I2C drivers 'Arbitation lost' error message.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Tom Rini [Tue, 31 Jan 2023 15:15:39 +0000 (10:15 -0500)]
Merge tag 'u-boot-amlogic-20230131' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- jethub j100: add rescue boot from microSD
- move meson sm command to cmd/meson and add efusedump sub-command
- switch dwc2 otg to DM for G12A, GXL & AXG
- Add new boards:
- Odroid Go Ultra
- Odroid-N2L
Max Krummenacher [Mon, 30 Jan 2023 12:39:06 +0000 (13:39 +0100)]
ARM: arm: colibri-imx6ull-emmc: fix emmc access
Synchronizing the device tree with linux introduced a regression.
The U-Boot specific dtsi mustn't override the alias settings for
the eMMC/SD interfaces.
Without this U-Boot cannot access the eMMC and boot the kernel.
Fixes: c21b61bff15 ("colibri-imx6ull/-emmc: synchronise device tree with linux") Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Implement basic PSCI provider to let OS turn CPU cores off and on,
power off and restart the system and determine PSCI version. This
is sufficient to remove the need for the ATF BL31 blob altogether.
To make use of this functionality, active the following Kconfig options:
# CONFIG_PSCI_RESET is not set
CONFIG_ARMV8_MULTIENTRY=y
CONFIG_ARMV8_SET_SMPEN=y
CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y
CONFIG_ARMV8_EA_EL3_FIRST=y
CONFIG_ARMV8_PSCI=y
CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
CONFIG_ARMV8_SECURE_BASE=0x970000
CONFIG_ARM_SMCCC=y
CONFIG_SYS_HAS_ARMV8_SECURE_BASE=y
Marek Vasut [Thu, 22 Dec 2022 00:46:42 +0000 (01:46 +0100)]
arm: imx: imx8m: Program CSU and TZASC if PSCI provider
In case U-Boot is the PSCI provider, it is necessary to correctly
program CSU and TZASC registers. Those are poorly documented, so
push in the correct values.
Marek Vasut [Thu, 22 Dec 2022 00:46:41 +0000 (01:46 +0100)]
arm: imx: imx8m: Define trampoline location if PSCI provider
The common code used to bring up secondary cores requires a final
jump location to be stored in some sort of memory location, define
this memory location to be the start of OCRAM, since it is available.
Marek Vasut [Thu, 22 Dec 2022 00:46:40 +0000 (01:46 +0100)]
arm: imx: imx8m: Map RAM as NS if PSCI provider
In case U-Boot is a PSCI provider, map RAM explicitly as NS,
otherwise secondary cores crash with SError when attempting
to access RAM mapped as secure in EL2.
Marek Vasut [Thu, 22 Dec 2022 00:46:38 +0000 (01:46 +0100)]
arm: imx: imx8m: Only use ROM pointers if not PSCI provider
The ROM pointers are in fact populated by the ATF BL31 blob, in case
U-Boot itself if the PSCI provider, there is no ATF BL31 blob, hence
ignore the ROM pointers.
Marek Vasut [Thu, 22 Dec 2022 00:46:37 +0000 (01:46 +0100)]
arm: dts: imx8m: Require ATF BL31 blob only if not PSCI provider
In case U-Boot itself if the PSCI provider on i.MX8M, do not
require the ATF BL31 blob, as at that point the blob is useless
and would interfere with U-Boot operation.
Marek Vasut [Thu, 22 Dec 2022 00:46:36 +0000 (01:46 +0100)]
arm: imx: Drop custom lowlevel_init
The custom lowlevel_init implementation is no longer necessary, since
it is responsible for routing and trapping SErrors in U-Boot in EL2,
which is implemented in common code since commit: 6c7691edd55 ("armv8: Always unmask SErrors")
Marek Vasut [Thu, 22 Dec 2022 00:46:35 +0000 (01:46 +0100)]
arm: psci: Fix RESET2 hook
The RESET2 hook is a PSCI v1.1 functionality, rename the macro accordinly.
Add missing handler for the RESET2 hook, so it can be implemented by U-Boot.
They need to be kept so that the mmc cards are in the right order.
Without the aliases, u-boot reports:
MMC: FSL_SDHC: 2, FSL_SDHC: 3
With the aliases, u-boot reports:
MMC: FSL_SDHC: 0, FSL_SDHC: 1
The upstream linux device tree does not contain the same aliases than
u-boot (It keeps the devices order with /dev/mmcblk2 and /dev/mmcblk3).
Because this board has been using different aliases in u-boot
and linux, a imx6q-sabrelite-u-boot.dtsi file is added to be
automatically included in imx6q-sabrelite.dts.
This way, linux and u-boot each keep their own aliases and there
is no breakage on current installations.
This should never be done for new boards as we want to keep linux and
u-boot with the same aliases as much as possible.
This patch is only necessary to avoid breaking existing setups.
The introduction of CONFIG_FSL_QSPI_AHB_FULL_MAP as default in:
def88bce094e ("spi: fsl_qspi: Support to use full AHB space on i.MX")
broke the SPI NAND read access on the Kontron SL i.MX6UL/ULL boards.
Reading data from the flash returns garbage instead of the actual
content. Fix this for now by disabling the introduced option.
In the long run this should be fixed globally.
Fixes: def88bce094e ("spi: fsl_qspi: Support to use full AHB space on i.MX") Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
John Keeping [Thu, 19 Jan 2023 12:56:12 +0000 (12:56 +0000)]
power: act8846_pmic: fix number of registers
The highest register on ACT8846 is 0xf5, so set the number of registers
to 0xf6, ensuring that the pmic read/write commands are able to access
all of the supported registers (and many that are not valid, since the
register space is quite sparse).
Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Add support for HS400 in mode2timing array.
Add a quirk for Versal NET platform to indicate that HS400 is supported
through bit63 of capability register.
mmc: sdhci: Check and call config_dll callback functions
Check if the low level driver supports config_dll callback function and
call it if it does. Call with dll disable before calling set_clock and
with dll enable after it.
mmc: zynq_sdhci: Add support for eMMC5.1 for Versal NET platform
Add support for eMMC 5.1 for Versal NET platform
- Add new compatible string(xlnx,versal-net-5.1-emmc).
- Add CONFIG_ARCH_VERSAL_NET condition wherever required.
- Add DLL and Delay Chain mode support
- Add input and output tap delays for eMMC.
- Add Strobe select tap for HS400 mode.
Marek Vasut [Thu, 5 Jan 2023 14:19:08 +0000 (15:19 +0100)]
cmd: mmc: Expand bkops handling
Add more capable "bkops" command which allows enabling and disabling both
manual and automatic bkops. The existing 'mmc bkops-enable' subcommand is
poorly named to cover all the possibilities, hence the new-ish subcommand.
Note that both commands are wrappers around the same common code.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Ye Li [Wed, 18 Jan 2023 09:31:15 +0000 (17:31 +0800)]
ARM: dts: imx8ulp-evk: Fix iomuxc issue
The property fsl,mux_mask is deleted by commit ed7bda5 (imx8ulp:
synchronise device tree with linux). This causes the pinctrl
driver not work on 8ULP, so fail to print any log.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
dts: imx8mp-rsb3720: modify configrations to load fip into memory
The changes of commit 6a21c695213b ("arm: dts: imx8mp: add of-list
support to common imx8mp-u-boot.dtsi") breaks the loading of the fip.
This commit fixes the break by modify the configuration properly.
Loic Poulain [Thu, 12 Jan 2023 17:19:50 +0000 (18:19 +0100)]
serial: mxc: Wait for TX completion before reset
The u-boot console may show some corrupted characters when
printing in board_init() due to reset or baudrate change
of the UART (probe) before the TX FIFO has been completely
drained.
To fix this issue, and in case UART is still running, we now
try to flush the FIFO before proceeding to UART reinitialization.
For this we're waiting for Transmitter Complete bit, indicating
that the FIFO and the shift register are empty.
flushing has a 4ms timeout guard, which is normally more than
enough to consume the FIFO @ low baudrate (9600bps).
Add aliases for the RTCs on the board and on the SoC. This ensures that
the primary RTC is always the one on the board that has a buffered supply
and maximum accuracy.
This is a direct port of the pending commit from linux-next.
The i.MX 8M Mini SoC does incorporate an additional M-Core. To be able
to load it with a firmware, enable bootaux command as other Toradex
modules also have it enabled to be consistent.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Marek Vasut [Tue, 13 Dec 2022 04:46:07 +0000 (05:46 +0100)]
ARM: imx: bootaux: Fix LTO -Wlto-type-mismatch
Commit 56c2dbdabab5 ("imx: bootaux: cleanup code") introduces the
following LTO related warning:
"
arch/arm/mach-imx/imx_bootaux.c:24:31: warning: type of ‘hostmap’ does not match original declaration [-Wlto-type-mismatch]
24 | const __weak struct rproc_att hostmap[] = { };
| ^
arch/arm/mach-imx/imx8m/soc.c:1590:24: note: array types have different bounds
1590 | const struct rproc_att hostmap[] = {
| ^
arch/arm/mach-imx/imx8m/soc.c:1590:24: note: ‘hostmap’ was previously declared here
../aarch64-linux-gnu/bin/ld: warning: u-boot has a LOAD segment with RWX permissions
"
This is because the weak empty array of structures "hostmap" is eventually
replaced by non-empty array of structures with different number of elements.
Fix this by avoiding weak variable size array, instead use a weak function
which returns single pointer to the array.
Fixes: 56c2dbdabab5 ("imx: bootaux: cleanup code") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Marek Vasut [Tue, 13 Dec 2022 04:46:06 +0000 (05:46 +0100)]
ARM: imx: bootaux: Fix macro misuse
There are no CONFIG_{TOOLS_,SPL_,TPL_,}IMX8M macros, nor is there one for
ARM64. Use plain IS_ENABLED(CONFIG_IMX8M) and IS_ENABLED(CONFIG_ARM64) to
avoid expanding the {TOOLS_,SPL_,TPL_,} part.
Fixes: 56c2dbdabab5 ("imx: bootaux: cleanup code") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Marek Vasut [Sun, 11 Dec 2022 20:17:14 +0000 (21:17 +0100)]
ARM: imx: Factor common code out of Data Modul i.MX8M Mini eDM SBC
Pull common.c into common subdirectory of the board file,
since this code can be reused by other Data Modul SBCs.
Drop the include of lpddr4_timing.h, which is unneeded.
Marek Vasut [Sun, 11 Dec 2022 20:16:36 +0000 (21:16 +0100)]
ARM: imx: Drop board side icache enable on Data Modul i.MX8M Mini eDM SBC
The icache is enabled in common architecture code since commit: 2fa763baa1c ("ARM: imx: Enable instruction cache early on on i.MX8M")
Drop the board side duplicate code.
Fabio Estevam [Sat, 10 Dec 2022 21:31:19 +0000 (18:31 -0300)]
imx6qdl-sabresd: Pass mmc alias
Originally, the mmc aliases node was present in imx6qdl-sabresd.dtsi.
After the sync with Linux in commit d0399a46e7cd ("imx6dl/imx6qdl:
synchronise device trees with linux"), the aliases node is gone as
the upstream version does not have it.
This causes a regression in which the SD card cannot be found anymore.
Fix it by passing the alias node in the u-boot.dtsi file to
restore the original behaviour where the SD card (esdhc3) was
mapped to mmc1.
Fixes: d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with linux") Reported-by: Carlos Rafael Giani <dv@pseudoterminal.org> Signed-off-by: Fabio Estevam <festevam@denx.de>
Decode ECSPI boot device in env_get_location() from i.MX8M ROMAPI tables.
This is necessary to correctly identify env is in SPI NOR when the system
boots from SPI NOR attached to ECSPI.
This reinstates change from commit: e26d0152d61 ("ARM: imx: Decode ECSPI env location from i.MX8M ROMAPI tables")
which has been dropped in commit: b0a284a7c94 ("imx: move get_boot_device to common file")
Fixes: b0a284a7c94 ("imx: move get_boot_device to common file") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
Marek Vasut [Fri, 9 Dec 2022 19:35:47 +0000 (20:35 +0100)]
ARM: imx: Remove PMIC reset configuration from board files
The PCA9450 reset configuration can now be performed by the PCA9450 PMIC
driver itself, remove the hard-coded variant from board code and let the
PMIC driver perform this task using one-liner:
```
$ sed -i '/set WDOG_B_CFG to cold reset/,+2 d' $(git grep -l PCA9450_RESET_CTRL.*0xA1 board/)
```
Venice and i.MX93 EVK required slight manual fix up.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Marek Vasut [Fri, 9 Dec 2022 19:35:46 +0000 (20:35 +0100)]
pmic: pca9450: Make warm reset on WDOG_B assertion
The default configuration of the PMIC behavior makes the PMIC
power cycle most regulators on WDOG_B assertion. This power
cycling causes the memory contents of OCRAM to be lost.
Some systems neeeds some memory that survives reset and
reboot, therefore this patch is created.
The implementation is taken almost verbatim from Linux commit 2364a64d0673f ("regulator: pca9450: Make warm reset on WDOG_B assertion")
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Mikhail Ilin [Wed, 23 Nov 2022 10:59:49 +0000 (13:59 +0300)]
tools: imx8image: Fix handle leak
The handle "fd" was created in imx8image.c:249 by calling the "fopen"
function and is lost in imx8image.c:282.
Should close the 'fd' file descriptor before exiting the
parse_cfg_file(image_t *param_stack, char *name) function.
Fixes: a2b96ece5be1 ("tools: add i.MX8/8X image support") Signed-off-by: Mikhail Ilin <ilin.mikhail.ol@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Mikhail Ilin [Wed, 23 Nov 2022 10:48:44 +0000 (13:48 +0300)]
tools: imx8mimage: Fix handle leak
The handle "fd" was created in imx8mimage.c:178 by calling
the "fopen" function and is lost in imx8mimage.c:210.
Should close the 'fd' file descriptor before exiting
the parse_cfg_file(char *name) function.
Mikhail Ilin [Tue, 22 Nov 2022 09:34:26 +0000 (12:34 +0300)]
tools: imximage: Fix check array index
The struct dcd_v1_t is initialized to MAX_HW_CFG_SIZE_V1 (60)
structs 'dcd_type_addr_data_t', so the indexes to use on its elements
are [0,59]. But on line 478, the variable 'length' can take on the value
60, which applies to array overflow: cd_v1->addr_data[length].type Thus,
it is necessary to tighten the check on the 'size' variable on line 463.
Fixes: 0b0c6af38738 ("Prepare v2020.01") Signed-off-by: Mikhail Ilin <ilin.mikhail.ol@gmail.com>
[why]
TPL is not mandatory for not all Rockchip SoCs, some SoCs like
RK356x, and RK3588 still use mainline u-boot without TPL as
their ddr init programs are accessed via binaries provided by
Rockchip instead of ddr source code.
Marking TPL build makes it not able to build u-boot.itb on
RK356x targets so revert this so that it can build an SPL build
that would support all across Rockchip platforms.
projects / u-boot.git / log