Stefan Brüns [Sun, 31 Dec 2017 22:21:17 +0000 (23:21 +0100)]
patman: Unquote output from get_maintainer.pl
get_maintainer.pl quotes names which it considers unsafe, i.e. anything
containing [^a-zA-Z0-9_ \-]. This confuses patman, it will duplicate
addresses which are also in Series-to/cc. Strip the quotes.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Mario Six [Wed, 20 Dec 2017 08:52:12 +0000 (09:52 +0100)]
drivers: core: Add translation in live tree case
The function dev_read_addr calls ofnode_get_addr_index in the live tree
case, which does not apply bus translations to the address read from the
device tree. This results in illegal addresses on boards that rely on
bus translations being applied.
Fix this situation by applying bus translations in the live tree case as
well.
Signed-off-by: Mario Six <mario.six@gdsys.cc> Tested-by: Stephen Warren <swarren@nvidia.com>
Tuomas Tynkkynen [Thu, 11 Jan 2018 14:11:24 +0000 (16:11 +0200)]
ARM: Document AArch64 version of qemu-arm
It's mostly obvious, except that QEMU is annoying and requires an
explicit '-cpu cortex-a57' (or some other 64-bit core) to actually run
in 64-bit mode.
While at it, remove the references to setting the ARCH environment
variable; that is not used in U-Boot.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Tom Rini <trini@konsulko.com>
Tuomas Tynkkynen [Thu, 11 Jan 2018 14:11:23 +0000 (16:11 +0200)]
ARM: qemu-arm: Add support for AArch64
This adds support for '-machine virt' on AArch64. This is rather simple:
we just add TARGET_QEMU_ARM_xxBIT to select a few different Kconfig
symbols, provide the ARMv8 memory map from the board file and add a new
defconfig based on the 32-bit defconfig.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Tom Rini <trini@konsulko.com>
Andrew F. Davis [Tue, 9 Jan 2018 20:33:54 +0000 (14:33 -0600)]
arm: mach-omap2: Remove secure certificate name printing
The signing certificate name is always 15 chars long, but need not be
null terminated. One solution is then to use printf precision modifiers
to only print this many chars ("%.15s"), but tiny printf does not support
this, so lets just drop printing the cert name for now.
Madan Srinivas [Tue, 9 Jan 2018 20:32:41 +0000 (14:32 -0600)]
arm: am33xx: security: Fix size calculation on header
Fix the size calculation in the verify boot. The header size
should be subtracted from the image size, not be assigned to
the image size.
Fixes: 0830d72bb9f8 ("arm: am33xx: security: adds auth support for encrypted images") Signed-off-by: Madan Srinivas <madans@ti.com> Signed-off-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Derald D. Woods [Sun, 7 Jan 2018 05:10:06 +0000 (23:10 -0600)]
ARM: omap3: evm: Add kernel image loading from UBIFS and EXT4
This commit adds UBIFS_NAND to BOOT_TARGET_DEVICES. This will
allow the kernel zImage to be loaded from '/boot/zImage' in UBIFS
(ubi0:rootfs).
Additionally update the *_MMC devices to also load kernel image from
the MMC 0:2 EXT4 file system.
DISTRO_DEFAULTS Setup
=====================
[primary] Check MMC 0:1 for /extlinux/extlinux.conf and boot
[fallback 1] Check MMC 0:2 /boot/zImage and run mmcbootz
[fallback 2] Check MMC 0:2 /boot/uImage and run mmcboot
[fallback 3] Check NAND UBIFS /boot/zImage and run nandbootubifs
[fallback 4] Check NAND partitions and run nandboot
The following "extlinux.conf" can be used to load images in the
top-level of the MMC 0:1 FAT partition.
Tom Rini [Wed, 3 Jan 2018 14:23:14 +0000 (09:23 -0500)]
GPIO: pca953x: Rework to not include commands in SPL
The command portion of the GPIO driver can only be used in full SPL so
re-work to guard the command related portions and mark it as static.
Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
The message
"** %s shorter than offset + len **\n"
may be interesting when debugging but it does not indicate an
error.
So we should not write it if we are not in debug mode.
Fixes: 7a3e70cfd88c fs/fs.c: read up to EOF when len would read past EOF Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Derald D. Woods [Fri, 29 Dec 2017 16:37:31 +0000 (10:37 -0600)]
ARM: dts: omap3-beagle{-xm}: Add support for BeagleBoard
This commit adds OMAP3 BeagleBoard devicetree files from
Linux v4.15-rc5. This includes standard OMAP34XX board revisions as
well as the 'xM' which is OMAP36XX.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Lokesh Vutla [Fri, 29 Dec 2017 06:17:55 +0000 (11:47 +0530)]
board: ti: am574x-idk: Update pinmux using latest PMT
Update the board pinmux for AM574x-IDK board using latest PMT[1] and the
board files named am574x_idk_v1p3b_sr2p0 that were auto generated on
13th October, 2017 by "Ahmad Rashed <a-rashed@ti.com>".
Lokesh Vutla [Fri, 29 Dec 2017 06:17:51 +0000 (11:47 +0530)]
arm: dra762: Add support for device package identification
DRA762 comes in two packages:
- ABZ: Pin compatible package with DRA742 with DDR@1333MHz
- ACD: High performance(OPP_PLUS) package with new IPs
Both the above packages uses the same IDCODE hence needs to
differentiate using package information in DIE_ID_2.
Add support for the same. Also update clock, ddr, emif information.
Lokesh Vutla [Fri, 29 Dec 2017 06:17:50 +0000 (11:47 +0530)]
cmd: ti: Generalize cmd_ddr3 command
Keystone and DRA7 based TI platforms uses same
EMIF memory controller. cmd_ddr3 command is customized
for keystone platforms, make it generic so that it can
be re used for DRA7 platforms.
Lokesh Vutla [Fri, 29 Dec 2017 06:17:47 +0000 (11:47 +0530)]
arm: emif-common: Add ecc specific emif registers
This is a slight difference in emif_ddr_phy_status register offsets for
DRA7xx EMIF and older versions. And ecc registers are available only
in DRA7xx EMIC. Add support for this difference and ecc registers.
Felix Brack [Thu, 28 Dec 2017 17:06:50 +0000 (18:06 +0100)]
dt-bindings: leds: adopt Linux PCA9532 binding constants
I'm working on a v2 patch to add support for a board named pdu001. Its
Linux DTS file uses the include file added by this patch. To keep Linux
and U-Boot DTS files in sync U-Boot requires a copy of this file,
although there is no driver for NXP's PCA9532 i2c LED driver chip (yet).
Lokesh Vutla [Thu, 28 Dec 2017 15:10:01 +0000 (20:40 +0530)]
arm: am33xx: Avoid writing into reserved DPLL divider
DPLL DRR doesn't have an M4 divider. But the clock driver is trying
to configure M4 divider as 4(writing into a reserved register).
Fixing it by making M4 divider as -1.
Reported-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Thu, 28 Dec 2017 15:10:00 +0000 (20:40 +0530)]
tools: omapimage: Fix mismatch of image size in header
The size field in GP header that is expected by ROM is size of the
image + size of the header. But omapimage tool is updating size
as image size + 2 * header size. Remove this extra header size bytes.
Rex Chang [Thu, 28 Dec 2017 15:09:59 +0000 (20:39 +0530)]
board: ti: K2G FC SoC 1GHz and DDR3 1066 MT/s support
Added support for K2G EVM with FlipChip SoC of which
ARM/DDR3 runs at 1GHz/1066 MT/s. The patch is also
backward compatible with old revision EVM and EVM
with WireBond SoC. Their ARM/DDR3 run at 600MHz/800 MT/s.
The new SoC supports 2 different speeds at 1GHz and 600MHz.
Modyfied the CPU Name to show which SoC is used in the EVM.
Modified the DDR3 configuration to reflect New SoC supports
2 different CPU and DDR3 speeds, 1GHz/1066MT and 600MHz/800MT.
Added new inline function board_it_k2g_g1() for the new FlipChip 1GHz,
and set the u-boot env variable board_name accordingly.
Modified findfdt script in u-boot environment variable to include new k2g board type.
Signed-off-by: Rex Chang <rchang@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Vignesh R [Tue, 12 Dec 2017 11:44:27 +0000 (17:14 +0530)]
board: ti: dra7xx: Select MCAN instead of DCAN on DRA76 EVM
MCAN can be accessed via DCAN1 or DCAN2. Determining which DCAN instance
to use if any at all is done through
CTRL_CORE_CONTROL_SPARE_RW.SEL_ALT_MCAN. Since general pinmuxing is
handled in U-boot. Handle this additional pinmuxing requirement in U-boot
to ensure that MCAN is used by default via the DCAN1 pins.
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
[fcooper@ti.com: Update commit message and use DCAN1 not DCAN2 for MCAN] Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
mmc: omap_hsmmc: Fix incorrect bit operations for disabling a bit
omap_hsmmc driver uses "|" in a couple of places for disabling a bit.
While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a
_mask_ argument to take care of resetting a bit), it's incorrectly used
for resetting flags in "omap_hsmmc_send_cmd".
Fix it here by using "&= ~()" to reset a bit.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
mmc: omap_hsmmc: Enable Auto command (CMD12) enable
Instead of sending STOP TRANSMISSION command from MMC core, enable
the auto command feature so that the Host Controller issues CMD12
automatically when last block transfer is completed.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
The omap hsmmc host controller can have the ADMA2 feature. It brings better
read and write throughput.
On most SOC, the capability is read from the hl_hwinfo register. On OMAP3,
DMA support is compiled out.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Chris Packham [Thu, 18 Jan 2018 04:16:10 +0000 (17:16 +1300)]
ddr: marvell: update ddr controller init and freq
Update the calculation for tWR and tPD. This improves the DDR refresh
interval and brings the initialization into line with the binary blobs
currently being supplied by Marvell.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 18 Jan 2018 04:16:09 +0000 (17:16 +1300)]
ddr: marvell: update additional ODT setting
The RD_SAMPLE_DELAY field is 5 bits so it needs to be masked with 0x1f
instead of 0xf. Rather than checking the read sample delay for all DDR
chip selects use the values for the chip selects that are actually
configured. Finally continue searching for the max_phase value even if the
current read_sample is the same as the max_read_sample.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 18 Jan 2018 04:16:07 +0000 (17:16 +1300)]
ddr: marvell: only assert M_ODT[0] on write for a single CS
When using only a single DDR chip select only assert M_ODT[0] on write.
Do not assert it on read and do not assert M_ODT[1] at all. Also set
tODT_OFF_WR to 0x9 which contradicts the recommendation from the
functional spec but is what Marvell's binary training blob does and
seems to give better results when ODT is active during writes.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Alexey Brodkin [Fri, 19 Jan 2018 13:13:51 +0000 (16:13 +0300)]
ARC: devboards: Allow huge uImages (up to 128 MiB)
Even though in production uImage usually is quite small as
it contains just Linux kernel image during development it might
be pretty convenient to have root-FS built into the same image.
That makes uImage much larger but given on our dev platforms we have
quite a lot of DDR (> 512 MiB) we may afford loading huge uImages.
Eugeniy Paltsev [Tue, 16 Jan 2018 18:52:25 +0000 (21:52 +0300)]
ARC: Invalidate instruction and data caches early on boot
This is useful to make sure no stale data exists in caches after bootloaders.
The worst thing could be some lines of cache were locked in a bootloader
for example during DDR recalibration and never unlocked. This may lead
to really unpredictable issues later down the line.
Eugeniy Paltsev [Tue, 16 Jan 2018 16:30:17 +0000 (19:30 +0300)]
ARC: HSDK: Hang on panic
As HSDK is a development board it is better to hang on panic instead of
reset the board when panic occurs. That way we preserve a state of HW
for possibility to do post-mortem debug via JTAG.
Eugeniy Paltsev [Tue, 16 Jan 2018 16:20:28 +0000 (19:20 +0300)]
ARC: Cache: Disable IOC by default
We'd like to keep IOC HW at the same state as t is right after reset when we
start Linux kernel so there will be no re-configuration of IOC on the go.
The point is U-Boot doesn't benefit a lot from IOC as it doesn't do a
lot of DMA operations especially on multiple cores simultaneously.
At the same time re-configuration of IOC in run-time might become quite
a tricky experience because we need to make sure there're no DMA
trannsactions in flight otherwise unexpected consequencses might affect
us much later and debugging those kinds of issues will be a real
nightmare.
That said let's make our life easier a little bit.
Eugeniy Paltsev [Tue, 16 Jan 2018 16:20:26 +0000 (19:20 +0300)]
ARC: ARCv2: Cache: Fixed operation without IOC
Previous SLC management implementation is broken. Seems like it was
never sufficiently tested probably because most of the time IOC was used
instead (i.e. no manual cache operations were done).
Now if we disable IOC in U-boot we'll get a lot of errors while using
DMA-enabled peripherals.
This time we fix it by substitution of broken per-line SLC operations
region operations as it is done in the Linux kernel (we took it from
v4.14 which is the latest stable as of today).
Among other things this implementation might be a bit faster because
instead of iteration over each and every cache line we're taking care
about entire region in one go.
Main changes:
* Replaced __slc_line_op (per line operations) by __slc_rgn_op
(region operations).
* Reworked __slc_entire_op to get rid of __after_slc_op and
__before_slc_op functions.
Note flush fix (flush only instead of flush-n-inv when OP_FLUSH is
used, see [1] for more details) is already incorporated here.
* Added SLC invalidation to invalidate_icache_all().
* Added (start >= end) check to invalidate_dcache_range() and
flush_dcache_range() as some buggy drivers pass region start == end.
* Added read-out of MMU BCR so we may know if PAE40 exists in HW and then
act on a particular AUX regs accordingly.
omap: Update the base address of the MMC controllers
Align the base address defined in header files with the base address used
in the DTS. This will facilitate the introduction of the DMA support.
Of all HSMMC users, only omap3 doesn't have the 0x100 reserved region at
the top. This region will be used to determine if the controller supports
DMA transfers
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
projects / u-boot.git / log