Harvey Chapman [Tue, 26 Feb 2013 17:57:14 +0000 (17:57 +0000)]
nand: adjust erase/read/write partition/chip size for bad blocks
Adjust the sizes calculated for whole partition/chip operations by
removing the size of bad blocks so we don't try to erase/read/write
past a partition/chip boundary.
Scott Wood [Tue, 26 Feb 2013 13:00:50 +0000 (13:00 +0000)]
nand/fsl_elbc: detect page size at runtime
This avoids needing a separate U-Boot config when some revisions
of a board have small-page NAND and other revisions have large-page
NAND (except for NAND SPL targets).
CONFIG_FSL_ELBC_FMR is removed -- it was never used nor documented, and
it gets in the way of this change.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Doug Anderson [Tue, 30 Apr 2013 10:22:00 +0000 (10:22 +0000)]
fdt_support: Use CONFIG_NR_DRAM_BANKS if defined
It appears that there are some cases where we have more than 4 banks
of memory. Use CONFIG_NR_DRAM_BANKS if it's defined to handle this.
This will take up a little extra stack space (64 bytes extra if we go
up to 8 banks), but that seems OK.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Doug Anderson [Tue, 17 Jan 2012 09:37:41 +0000 (09:37 +0000)]
bootm: Avoid 256-byte overflow in fixup_silent_linux()
This makes fixup_silent_linux() use malloc() to allocate its
working space, meaning that our maximum kernel command line
should only be limited by malloc(). Previously it was silently
overflowing the stack.
Note that nothing about this change increases the kernel's maximum
command line length. If you have a command line that is >256
bytes it's up to you to make sure that kernel can handle it.
Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
Kuo-Jung Su [Mon, 6 May 2013 20:32:51 +0000 (20:32 +0000)]
mmc: update Faraday FTSDC010 for rw performance
Faraday FTSDC010 is a MMC/SD host controller.
Although there is already a driver in current u-boot release,
which is modified from eSHDC and contributed by Andes Tech.
Its performance is too terrible on Faraday A36x SoC platforms,
so I turn to implement this new version of driver which is
10+ times faster than the old one.
It's carefully designed to be compatible with Andes chips,
so it should be safe to replace it.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Ying Zhang [Thu, 9 May 2013 23:00:36 +0000 (23:00 +0000)]
drivers/mmc: move spl_mmc.c to common/spl
The mpc85xx repuires a special layout on the memory device that is
connected to the eSDHC controller interface. But the file spl_mmc.c
didn't handle this specfic case, there needs a special treatmen, in
the powerpc drictory. So, there is no longer to keep spl_mmc.c on
mpc85xx, CONFIG_SPL_FRAMEWORK is not set.
When CONFIG_SPL_MMC_SUPPORT is set and CONFIG_SPL_FRAMEWORK is not
set, there was an error in drivers/mmc/spl_mmc.c:
drivers/mmc/libmmc.o:(.got2+0x8): undefined reference to `spl_image'.
Now, the solution is to move the file "spl_mmc.c" to directory "common/spl".
Shaohui Xie [Mon, 25 Mar 2013 07:39:38 +0000 (07:39 +0000)]
T4240/eth: fix SGMII card PHY address
QSGMII card assumed to be used by default, but if SGMII card is used,
it will use different PHY address, but we don't know which card is used
until we access PHY on the card. So we check the card type slot by slot,
if we can read a PHY ID by reading a SGMII PHY address on a slot, then
the slot must have a SGMII card pluged, we mark all ports on that slot,
and fix dts to use the SGMII card PHY address when doing dts fixup
for the marked ports.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Only clear IRE bit in qixis brdcfg5 register and keep other bits
unchanged.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Mon, 25 Mar 2013 07:39:35 +0000 (07:39 +0000)]
powerpc/mpc8xxx: Allow board file to override DDR address assignment
This gives boards flexibility to assign other than default addresses to each
DDR controller. For example, DDR controler 2 can have 0 as the base and DDR
controller 1 has higher memory.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Shaohui Xie [Mon, 25 Mar 2013 07:39:31 +0000 (07:39 +0000)]
net/phy: add VSC8574 support
The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Shengzhou Liu [Mon, 25 Mar 2013 07:39:28 +0000 (07:39 +0000)]
t4240qds/eth: fixup ethernet for t4240qds
1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address settings.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Mon, 25 Mar 2013 07:33:31 +0000 (07:33 +0000)]
powerpc: Add T4160QDS
T4160QDS shares the same platform as T4240QDS. T4160 is a low power
version of T4240, with eight e6500 cores, two DDR3 controllers, and
slightly different SerDes protocols.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Mon, 25 Mar 2013 07:33:29 +0000 (07:33 +0000)]
powerpc/mpc85xx: Add T4160 SoC
T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Roy Zang [Mon, 25 Mar 2013 07:33:23 +0000 (07:33 +0000)]
T4/USB: Add USB 2.0 UTMI dual phy support
T4240 internal UTMI phy is different comparing to previous UTMI PHY
in P3041.
This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for
T4240.
The phy timing is very sensitive and moving the phy enable code to
cpu_init.c will not work.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Mon, 25 Mar 2013 07:33:21 +0000 (07:33 +0000)]
powerpc/mpc85xx: Fix portal setup
Missing nodes of crypto, pme, etc in device tree is not a fatal error.
Setting up the qman portal should skip the missing node and continue
to finish the rest.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Mon, 25 Mar 2013 07:33:19 +0000 (07:33 +0000)]
powerpc/t4240qds: Update DDR timing table
Update the timing table to support more rank density, based on the theory
that similar density DIMMs have similar clock adjust and write level start
timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron
MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Roy Zang [Mon, 25 Mar 2013 07:33:18 +0000 (07:33 +0000)]
T4/SerDes: correct the SATA index
Lane H on SerDes4 should be SATA2 instead of SATA1
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Shaohui Xie [Mon, 25 Mar 2013 07:33:17 +0000 (07:33 +0000)]
Fman/t4240: some fix for 10G XAUI
1. fix 10G mac offset by plus 8;
2. add second 10G port info for FM1 & FM2 when init ethernet info;
3. fix 10G lanes name to match lane protocol table;
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Roy Zang [Mon, 25 Mar 2013 07:33:15 +0000 (07:33 +0000)]
T4/serdes: fix the serdes clock frequency
Reverse the bit sequence to set and display serdes clock frequency
correctly. The correct bit maps in BRDCFG2 are
0 1 2 3 4 5 6 7
S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0]
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Andy Fleming [Mon, 25 Mar 2013 07:33:14 +0000 (07:33 +0000)]
e6500: Move L1 enablement after L2 enablement
The L1 D-cache on e6500 is write-through. This means that it's not
considered a good idea to have the L1 up and running if the L2 is
disabled. We don't actually *use* the L1 until after the L2 is
brought up on e6500, so go ahead and move the L1 enablement after
that code is done.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Andy Fleming [Mon, 25 Mar 2013 07:33:10 +0000 (07:33 +0000)]
powerpc/mpc85xx: Add definitions for HDBCR registers
Makes it a bit easier to see if we've properly set them. While
we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually
use those definitions.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Simon Glass [Wed, 8 May 2013 08:06:06 +0000 (08:06 +0000)]
sparc: Use image_setup_linux() instead of local code
Sparc only really sets up the ramdisk, but we should still use
image_setup_linux() so that setup is common across all architectures
that use the FDT.
Cover-letter
Introduce a common image_setup_linux() function
This series continues the work to tidy up the image code. Each
architecture has its own code for setting up ready for booting linux.
An attempt is made here to unify these in a single image_setup_linux()
function.
The part of the image code that deals with FDT is split into image-fdt.c
and a few tweaks are added to make FIT images more viable in SPL.
END Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 May 2013 08:06:03 +0000 (08:06 +0000)]
arm: Use image_setup_linux() instead of local code
Use the common FDT setup function that is now available in image. Move
the FDT-specific code to a new bootm-fdt.c and remove unused headers
from bootm.c.
Simon Glass [Wed, 8 May 2013 08:06:02 +0000 (08:06 +0000)]
arm: Refactor bootm to reduce #ifdefs
With fewer #ifdefs the code is more readable and more of the code is
compiled for all boards. Add defines in the header file to control
what features are enabled, and then use if() instead of #ifdef.
Simon Glass [Wed, 8 May 2013 08:06:01 +0000 (08:06 +0000)]
image: Add device tree setup to image library
This seems to be a common function for several architectures, so create
a common function rather than duplicating the code in each arch.
Also make an attempt to avoid introducing #ifdefs in the new code, partly
by removing useless #ifdefs around function declarations in the image.h
header.
Simon Glass [Wed, 8 May 2013 08:05:59 +0000 (08:05 +0000)]
image: Add CONFIG_FIT_SPL_PRINT to control FIT image printing in SPL
This code is very large, and in SPL it isn't always useful to print
out image information (in fact there might not even be a console
active). So disable this feature unless this option is set.
Simon Glass [Wed, 8 May 2013 08:05:57 +0000 (08:05 +0000)]
mkimage: Put FIT loading in function and tidy error handling
The fit_handle_file() function is quite long - split out the part that
loads and checks a FIT into its own function. We will use this
function for storing public keys into a destination FDT file.
The error handling is currently a bit repetitive - tidy it.
Simon Glass [Tue, 7 May 2013 06:12:01 +0000 (06:12 +0000)]
image: Rename fit_add_hashes() to fit_add_verification_data()
We intend to add signatures to FITs also, so rename this function so that
it is not specific to hashing. Also rename fit_image_set_hashes() and
make it static since it is not used outside this file.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de>
Simon Glass [Tue, 7 May 2013 06:11:57 +0000 (06:11 +0000)]
image: Rename fit_image_check_hashes() to fit_image_verify()
This is the main entry point to the FIT image verification code. We will
be using it to handle image verification with signatures, so rename the
function.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de>
Simon Glass [Tue, 7 May 2013 06:11:51 +0000 (06:11 +0000)]
image: Move timestamp #ifdefs to header file
Rather than repeat the line
#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || \
defined(USE_HOSTCC)
everywhere, put this in a header file and #define IMAGE_ENABLE_TIMESTAMP
to either 1 or 0. Then we can use a plain if() in most code and avoid
the #ifdefs.
The compiler's dead code elimination ensures that the result is the same.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
Simon Glass [Tue, 7 May 2013 06:11:48 +0000 (06:11 +0000)]
bootstage: Don't build for HOSTCC
We don't measure boot timing on the host, or with SPL, so use both
conditions in the bootstage header. This allows us to avoid using
conditional compilation around bootstage_...() calls. (#ifdef)
Simon Glass [Tue, 7 May 2013 06:11:47 +0000 (06:11 +0000)]
hash: Add a way to calculate a hash for any algortihm
Rather than needing to call one of many hashing algorithms in U-Boot,
provide a function hash_block() which handles this, and can support all
available hash algorithms.
Once we have md5 supported within hashing, we can use this function in
the FIT image code.
Doug Anderson [Wed, 17 Apr 2013 16:13:41 +0000 (16:13 +0000)]
bootstage: Copy bootstage strings post-relocation
Any pointers to name strings that were passed to bootstage_mark_name()
pre-relocation should be copied post-relocation so that they don't get
trashed as the original location of U-Boot is re-used for other
purposes.
This change introduces a new API call that should be called from
board_init_r() after malloc has been initted on any board that uses
bootstage.
Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 17 Apr 2013 16:13:39 +0000 (16:13 +0000)]
x86: Re-enable PCAT timer 2 for beeping
While we don't want PCAT timers for timing, we want timer 2 so that we can
still make a beep. Re-purpose the PCAT driver for this, and enable it in
coreboot.
Simon Glass [Wed, 17 Apr 2013 16:13:37 +0000 (16:13 +0000)]
x86: Remove old broken timer implementation
Tidy up some old broken and unneeded implementations. These are not used
by coreboot or anything else now.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Michael Spang <spang@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
Simon Glass [Wed, 17 Apr 2013 16:13:35 +0000 (16:13 +0000)]
x86: Rationalise kernel booting logic and bootstage
The 'Starting linux' message appears twice in the code, but both call
through the same place. Unify these and add calls to bootstage to
mark the occasion.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Michael Spang <spang@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
Simon Glass [Wed, 17 Apr 2013 16:13:33 +0000 (16:13 +0000)]
x86: Declare global_data pointer when it is used
Several files use the global_data pointer without declaring it. This works
because the declaration is currently a NOP. But still it is better to
fix this so that x86 lines up with other archs.
projects / u-boot.git / log