]> git.dujemihanovic.xyz Git - u-boot.git/log
u-boot.git
2 years agoboard: hpe: gxp: add HPE GXP soc support
Nick Hawkins [Wed, 8 Jun 2022 21:21:37 +0000 (16:21 -0500)]
board: hpe: gxp: add HPE GXP soc support

Add basic support for the HPE GXP SoC. Reset the EHCI controller at
boot.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2 years agospi: gxp_spi: Add GXP SPI controller driver
Nick Hawkins [Wed, 8 Jun 2022 21:21:36 +0000 (16:21 -0500)]
spi: gxp_spi: Add GXP SPI controller driver

The GXP supports 3 separate SPI interfaces to accommodate the system
flash, core flash, and other functions. The SPI engine supports variable
clock frequency, selectable 3-byte or 4-byte addressing and a
configurable x1, x2, and x4 command/address/data modes. The memory
buffer for reading and writing ranges between 256 bytes and 8KB. This
driver supports access to the core flash.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2 years agotimer: gxp: Add HPE GXP timer support
Nick Hawkins [Wed, 8 Jun 2022 21:21:35 +0000 (16:21 -0500)]
timer: gxp: Add HPE GXP timer support

Add support for the HPE GXP SOC timer. The GXP supports several different
kinds of timers but for the purpose of this driver there is only support
for the General Timer. The timer has a 1us resolution and is 56 bits.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2 years agoARM: hpe: gxp: add core support
Nick Hawkins [Wed, 8 Jun 2022 21:21:34 +0000 (16:21 -0500)]
ARM: hpe: gxp: add core support

The GXP is the HPE BMC SoC that is used in the majority
of current generation HPE servers. Traditionally the asic will
last multiple generations of server before being replaced.

Info about SoC:

HPE GXP is the name of the HPE Soc. This SoC is used to implement many BMC
features at HPE. It supports ARMv7 architecture based on the Cortex A9
core. It is capable of using an AXI bus to whicha memory controller is
attached. It has multiple SPI interfaces to connect boot flash and BIOS
flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple
i2c engines to drive connectivity with a host infrastructure. There
currently are no public specifications but this process is being worked.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2 years agocmd/misc: Stop using a function pointer
Tom Rini [Wed, 22 Jun 2022 20:08:56 +0000 (16:08 -0400)]
cmd/misc: Stop using a function pointer

Currently, enabling CMD_MISC gives:
cmd/misc.c:67:25: warning: assignment to 'int (*)(struct udevice *, int,  void *, int)' from incompatible pointer type 'int (*)(struct udevice *, int,  const void *, int)' [-Wincompatible-pointer-types]

Because 'misc_read' takes a void * and 'misc_write' takes a const void
*, both of which make sense for their operation.  Given there's one
place we make use of the function pointer, just call read or write
directly for the operation we're called with.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoarm: add support to corstone1000 platform
Rui Miguel Silva [Wed, 11 May 2022 09:55:41 +0000 (10:55 +0100)]
arm: add support to corstone1000 platform

Corstone1000 is a platform from arm, which includes pre
verified Corstone SSE710 sub-system that combines Cortex-A and
Cortex-M processors [0].

This code adds the support for the Cortex-A35 implementation
at host side, it contains also the necessary bits to support
the Corstone 1000 FVP (Fixed Virtual Platform) [1] and also the
FPGA MPS3 board implementation of this platform. [2]

0: https://developer.arm.com/documentation/102360/0000
1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
2: https://developer.arm.com/documentation/dai0550/c/

Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agocmd: load: add load command for memory mapped
Rui Miguel Silva [Wed, 11 May 2022 09:55:40 +0000 (10:55 +0100)]
cmd: load: add load command for memory mapped

cp.b is used a lot as a way to load binaries to memory and execute
them, however we may need to integrate this with the efi subsystem to
set it up as a bootdev.

So, introduce a loadm command that will be consistent with the other
loadX commands and will call the efi API's.

ex: loadm $kernel_addr $kernel_addr_r $kernel_size

with this a kernel with CONFIG_EFI_STUB enabled will be loaded and
then subsequently booted with bootefi command.

Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agoARM: dts: omap3-devkit8000: Fix CONFIG_DM_ETH warning
Anthoine Bourgeois [Thu, 2 Jun 2022 20:27:08 +0000 (22:27 +0200)]
ARM: dts: omap3-devkit8000: Fix CONFIG_DM_ETH warning

Add the missing ethernet node in u-boot dts.

Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
2 years agoARM: dts: omap3-devkit8000: Fix CONFIG_DM_I2C warning
Anthoine Bourgeois [Thu, 2 Jun 2022 20:27:07 +0000 (22:27 +0200)]
ARM: dts: omap3-devkit8000: Fix CONFIG_DM_I2C warning

Seems that u-boot can't probe i2c bus at 2.6Mhz speed, so lower
the speed to the default value 100Khz.

v2: fix i2c1 frequency in the root omap3-u-boot.dtsi include.

Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
2 years agoARM: dts: omap3-devkit8000: Add support for Devkit8000
Anthoine Bourgeois [Thu, 2 Jun 2022 20:27:06 +0000 (22:27 +0200)]
ARM: dts: omap3-devkit8000: Add support for Devkit8000

This commit adds OMAP3 BeagleBoard devicetree files from Linux
v5.16.0.
This commit fixes CONFIG_DM_MMC warning.

v3: patch clean-up

Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
2 years agoMerge branch 'master' into next
Tom Rini [Mon, 20 Jun 2022 18:40:59 +0000 (14:40 -0400)]
Merge branch 'master' into next

Merge in v2022.07-rc5.

2 years agoPrepare v2022.07-rc5
Tom Rini [Mon, 20 Jun 2022 18:30:36 +0000 (14:30 -0400)]
Prepare v2022.07-rc5

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoconfigs: Resync with savedefconfig
Tom Rini [Mon, 20 Jun 2022 12:13:12 +0000 (08:13 -0400)]
configs: Resync with savedefconfig

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoMerge tag 'u-boot-stm32-20220620' of https://source.denx.de/u-boot/custodians/u-boot...
Tom Rini [Mon, 20 Jun 2022 12:09:24 +0000 (08:09 -0400)]
Merge tag 'u-boot-stm32-20220620' of https://source.denx.de/u-boot/custodians/u-boot-stm into next

- Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards
- Activate livetree for stm32mp15 DHSOM boards

2 years agoMerge tag 'fsl-qoriq-2022-6-20-v2' of https://source.denx.de/u-boot/custodians/u...
Tom Rini [Mon, 20 Jun 2022 12:08:29 +0000 (08:08 -0400)]
Merge tag 'fsl-qoriq-2022-6-20-v2' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next

Layerscape:
 add sfp driver
 Kconfig cleanup
 sl28 board update
 support hdp firmware loading
powerpc:
 dts update for p2020
 p1_p2_rdb_pc board update
 fsl_esdhc fallback to 1-bit mode support

2 years agoboard: sl28: rename include guard macro
Michael Walle [Mon, 30 May 2022 21:02:10 +0000 (23:02 +0200)]
board: sl28: rename include guard macro

Avoid name clashes with an include file on board level.

Signed-off-by: Michael Walle <michael@walle.cc>
2 years agoboard: sl28: support 8 GiB memory
Michael Walle [Mon, 30 May 2022 21:02:09 +0000 (23:02 +0200)]
board: sl28: support 8 GiB memory

The board supports up to 8 GiB memory. The memory is soldered on the
board but the configuration is equivalent to a dual chip select, dual
rank DIMM module.

Signed-off-by: Michael Walle <michael@walle.cc>
2 years agoboard: sl28: remove unneeded ddr config parameter
Michael Walle [Mon, 30 May 2022 21:02:08 +0000 (23:02 +0200)]
board: sl28: remove unneeded ddr config parameter

config_2 doesn't need to be set to zero because that is already the
default value.

Signed-off-by: Michael Walle <michael@walle.cc>
2 years agoboard: sl28: set CPO value
Michael Walle [Mon, 30 May 2022 21:02:07 +0000 (23:02 +0200)]
board: sl28: set CPO value

With a 8GiB memory board, it seems that the "very unlikely event" of a
DDR initialization with non-optimal values are not really that unlikely.
It happens in about every other reboot. As described in erratum
A-009942, preset the DEBUG_28 register with an optimal value. The value
iself depends on the memory configuration of the board, but the used
value seems to work well for all variants.

Signed-off-by: Michael Walle <michael@walle.cc>
2 years agoarmv8: layerscape: add missing RCW source defines
Michael Walle [Mon, 30 May 2022 21:02:05 +0000 (23:02 +0200)]
armv8: layerscape: add missing RCW source defines

A board might need to get the source of the RCW word, which is also the
boot source in most cases.

These defines are taken from the LS1028A and I expect they are the same
across the SoCs with the same chassis, after all, there was already a
reset source for NOR flash.

Signed-off-by: Michael Walle <michael@walle.cc>
2 years agopowerpc: bootm: Fix sizes in memory adjusting warning
Pali Rohár [Thu, 26 May 2022 12:36:03 +0000 (14:36 +0200)]
powerpc: bootm: Fix sizes in memory adjusting warning

Old size is stored in size variable and new size is in bootm_size variable.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agoboard: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h
Pali Rohár [Thu, 26 May 2022 08:52:27 +0000 (10:52 +0200)]
board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h

Code for changing boot source is platform generic and can be used by any
P1* and P2* compatible RDB board. Not only by boards which use config
header file p1_p2_rdb_pc.h.

So move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros
for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.

This allows to use code for resetting board and rebooting to other boot
source also by other boards in future.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agopowerpc: dts: p2020: Define PMC node
Pali Rohár [Tue, 24 May 2022 11:24:59 +0000 (13:24 +0200)]
powerpc: dts: p2020: Define PMC node

Copy definition of PMC node from upstream Linux kernel P2020 dts files.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agommc: fsl_esdhc: Add new config option for default fallback mode
Pali Rohár [Wed, 11 May 2022 18:27:13 +0000 (20:27 +0200)]
mmc: fsl_esdhc: Add new config option for default fallback mode

Currently default fallback SDHC mode is 1-bit. Add new config option
CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH to allow specifying default fallback
mode. This is useful e.g. for SPL builds which loads other parts from SD
card during boot process.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2 years agommc: fsl_esdhc: Set fallback mode to 1-bit
Pali Rohár [Wed, 11 May 2022 18:27:12 +0000 (20:27 +0200)]
mmc: fsl_esdhc: Set fallback mode to 1-bit

8-bit mode is not supported by SD cards and on P2020 are four SDHC pins
shared with SPI (so if P2020 board have also SPI then only 4-bit SDHC mode
is provided). So 8-bit SDHC mode is really bad default.

When max bus width is not provided then set mode to 1-bit. This mode is
supported by all cards, so it is the best option for fallback mode.

Also P2020 bootrom sets mode to 1-bit when booting from SD/MMC card.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2 years agols1028a: hdp: Add config support for HDP firmware loading
Alison Wang [Tue, 10 May 2022 10:29:10 +0000 (18:29 +0800)]
ls1028a: hdp: Add config support for HDP firmware loading

This patch adds config support for HDP firmware loading on LS1028A.

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2 years agopowerpc: mpc85xx: Set default SYS_IMMR value for P1/P2 CPUs
Pali Rohár [Mon, 2 May 2022 16:29:25 +0000 (18:29 +0200)]
powerpc: mpc85xx: Set default SYS_IMMR value for P1/P2 CPUs

This reduce usage of per-board custom settings.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agomtd: rawnand: fsl_elbc: Fix DM support in DTS code path
Pali Rohár [Mon, 2 May 2022 16:28:08 +0000 (18:28 +0200)]
mtd: rawnand: fsl_elbc: Fix DM support in DTS code path

For proper DM support it is required to fill also mtd->dev member.
Otherwise DM would not see nand device at all.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agopowerpc: mmu: Fix FSL_BOOKE_MAS2() macro
Pali Rohár [Sun, 1 May 2022 17:17:35 +0000 (19:17 +0200)]
powerpc: mmu: Fix FSL_BOOKE_MAS2() macro

Effective page number mask for MAS2 register is stored in macro MAS2_EPN.

Fixes: 2146cf56821c ("Reworked FSL Book-E TLB macros to be more readable")
Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agopowerpc: fsl_law: Add definition for first PCIe target interface
Pali Rohár [Sun, 1 May 2022 15:45:58 +0000 (17:45 +0200)]
powerpc: fsl_law: Add definition for first PCIe target interface

Header file asm/fsl_law.h already provides correct definition for second
and third PCIe controller (LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3). But
is missing definition for the first PCIe controller (LAW_TRGT_IF_PCIE_1).

Note that existing definition for LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3
are slightly complicated, but are really correct for P2020 platform.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agoboard: freescale: p1_p2_rdb_pc: Implement board_reset()
Pali Rohár [Sun, 1 May 2022 12:23:14 +0000 (14:23 +0200)]
board: freescale: p1_p2_rdb_pc: Implement board_reset()

Do board reset via CPLD's system reset register.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agoboard: freescale: p1_p2_rdb_pc: Enable TDM function only for P1010
Pali Rohár [Sun, 1 May 2022 12:20:48 +0000 (14:20 +0200)]
board: freescale: p1_p2_rdb_pc: Enable TDM function only for P1010

TDM function is supported only on P1010. P2020 does not have PMUXCR_TDM_ENA
register, so do not enable it.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agopowerpc: mpc85xx: Fix compilation with CONFIG_WDT
Pali Rohár [Thu, 28 Apr 2022 11:31:43 +0000 (13:31 +0200)]
powerpc: mpc85xx: Fix compilation with CONFIG_WDT

When CONFIG_WDT is enabled then non-DM watchdog code cannot be used due to
conflicting functions like watchdog_reset(). So disable compilation of
mpc85xx watchdog_reset() function when CONFIG_WDT is enabled.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agopowerpc: dts: p2020: Define ecm, memory and guts nodes
Pali Rohár [Wed, 27 Apr 2022 14:05:01 +0000 (16:05 +0200)]
powerpc: dts: p2020: Define ecm, memory and guts nodes

Copy definition of these nodes from upstream Linux kernel P2020 dts files.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agopowerpc: dts: p2020: Define DMA nodes
Pali Rohár [Wed, 27 Apr 2022 14:05:00 +0000 (16:05 +0200)]
powerpc: dts: p2020: Define DMA nodes

Copy definition of DMA nodes from upstream Linux kernel P2020 dts files.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agopowerpc: dts: p2020: Define crypto node
Pali Rohár [Wed, 27 Apr 2022 14:04:59 +0000 (16:04 +0200)]
powerpc: dts: p2020: Define crypto node

Copy definition of crypto node from upstream Linux kernel P2020 dts files.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agopowerpc: dts: p2020: Define MPIC nodes
Pali Rohár [Wed, 27 Apr 2022 14:04:58 +0000 (16:04 +0200)]
powerpc: dts: p2020: Define MPIC nodes

Copy definition of MPIC nodes from upstream Linux kernel P2020 dts files.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agoARM: layerscape: Use ARCH_LS104?A insead of TARGET_LS104?ARDB
Sean Anderson [Tue, 26 Apr 2022 18:31:49 +0000 (14:31 -0400)]
ARM: layerscape: Use ARCH_LS104?A insead of TARGET_LS104?ARDB

These frequency calculations depend on the RCW format, which is not
dependent on any particular board. Switch to using ARCH symbols instead
of TARGET.

This whole function could probably use less ifdefs, but for now just do
a minimal conversion.

Fixes: 24cb6f2295 ("fsl-layerscape: Add fsl_esdhc peripheral clock support")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2 years agoarch: layerscape: Add SFP binding
Sean Anderson [Fri, 22 Apr 2022 18:34:20 +0000 (14:34 -0400)]
arch: layerscape: Add SFP binding

This adds an SFP binding for the processors it is present on. I have
only tested this for the LS1046A.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2 years agoARM: dts: ls1021a: update the clockgen node
Sean Anderson [Fri, 22 Apr 2022 18:34:19 +0000 (14:34 -0400)]
ARM: dts: ls1021a: update the clockgen node

QorIQ platforms now use different clock bindings. Although we don't use
the device tree for clocks on this platform, it is helpful to sync it
because then the bindings will more closely match Linux. Additionally,
it allows for using more clock fractions (such as platform/4).

This corresponds to Linux commit b6f5e7019391 ("ARM: dts: ls1021a:
update the clockgen node").

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2 years agoarm: layerscape: Add sfp driver
Sean Anderson [Fri, 22 Apr 2022 18:34:18 +0000 (14:34 -0400)]
arm: layerscape: Add sfp driver

This adds a driver for the Security Fuse Processor (SFP) present on
LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the
Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and
other "security" related fuses. Similar devices (sharing the same name)
are present on other processors, but for the moment this just supports
the LS2 variants.

The mirror registers are loaded during power-on reset. All mirror
registers must be programmed or read at once. Because of this, `fuse
prog` will program all fuses, even though only one might be specified.
To prevent accidentally burning through all your fuse programming cycles
with something like `fuse prog 0 0 A B C D`, we limit ourselves to one
programming cycle per reset. Fuses are numbered based on their address.
The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc.

The TA_PROG_SFP supply must be enabled when programming fuses, but must
be disabled when reading them. Typically this supply is enabled by
inserting a jumper or by setting a register in the board's FPGA. I've
also added support for using a regulator. This could be helpful for
automatically issuing the FPGA write, or for toggling a GPIO controlling
the supply.

I suggest using the following procedure for programming:

1. Override the fuses you wish to program
   => fuse override 0 2 A B C D
2. Inspect the values and ensure that they are what you expect
   => fuse sense 0 2 4
3. Enable TA_PROG_SFP
4. Issue a program command using OSPR0 as a dummy. Since it contains the
   write-protect bit you will usually want to write it last anyway.
   => fuse prog 0 0 0
5. Disable TA_PROG_SFP
6. Read back the fuses and ensure they are correct
   => fuse read 0 2 4

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2 years agoMerge tag 'efi-2022-07-rc5-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Tom Rini [Sun, 19 Jun 2022 15:30:29 +0000 (11:30 -0400)]
Merge tag 'efi-2022-07-rc5-2' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2020-07-rc5-2

Documentation:

* man-pages for booti and printenv

UEFI

* correct return value for printenv -e command
* initialize console size late

2 years agoefi_loader: initialize console size late
Heinrich Schuchardt [Tue, 14 Jun 2022 06:02:03 +0000 (08:02 +0200)]
efi_loader: initialize console size late

If CONFIG_VIDEO_DM=n we query the display size from the serial console.
Especially when using a remote console the response can be so late that
it interferes with autoboot.

Only query the console size when running an EFI binary.

Add debug output showing the determined console size.

Reported-by: Fabio Estevam <festevam@gmail.com>
Fixes: a57ad20d07e8 ("efi_loader: split efi_init_obj_list() into two stages")
Fixes: a9bf024b2933 ("efi_loader: disk: a helper function to create efi_disk objects from udevice")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Fabio Estevam <festevam@denx.de>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
2 years agotest: work around for EFI terminal size probing
Heinrich Schuchardt [Sun, 19 Jun 2022 12:02:18 +0000 (14:02 +0200)]
test: work around for EFI terminal size probing

When the UEFI sub-system is initialized it sends an escape sequence to the
serial console to determine the terminal size. This stops the
run_command_list() function of the console emulation from recognizing the
U-Boot command line prompt.

Add a 'print -e' command as first command in the command list to work
around this issue.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2 years agocmd: correct return value for printenv -e
Heinrich Schuchardt [Sun, 19 Jun 2022 11:36:48 +0000 (13:36 +0200)]
cmd: correct return value for printenv -e

If printenv -e is executed and the specified variable is not found, the
return value $? of the command should be 1 (false).

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2 years agodoc: man-page for the printenv command
Heinrich Schuchardt [Sun, 19 Jun 2022 11:59:22 +0000 (13:59 +0200)]
doc: man-page for the printenv command

Privide a man-page for the printenv command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2 years agodoc: man-page for bootz command
Heinrich Schuchardt [Sat, 11 Jun 2022 06:23:31 +0000 (08:23 +0200)]
doc: man-page for bootz command

Provide a man-page for the bootz command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2 years agoMerge tag 'u-boot-stm32-20220617' of https://source.denx.de/u-boot/custodians/u-boot-stm
Tom Rini [Fri, 17 Jun 2022 13:41:11 +0000 (09:41 -0400)]
Merge tag 'u-boot-stm32-20220617' of https://source.denx.de/u-boot/custodians/u-boot-stm

- Fix the stm32prog command for stm32mp platform
- Add stm32mp15x DHCOR based DRC Compact board

2 years agoMerge commit '32e0379143b433e29d76404f5f4c279067e48853' of https://github.com/tienfon...
Tom Rini [Fri, 17 Jun 2022 13:35:28 +0000 (09:35 -0400)]
Merge commit '32e0379143b433e29d76404f5f4c279067e48853' of https://github.com/tienfong/uboot_mainline

2 years agoMerge branch '2022-06-16-assorted-bugfixes'
Tom Rini [Fri, 17 Jun 2022 13:13:50 +0000 (09:13 -0400)]
Merge branch '2022-06-16-assorted-bugfixes'

- A wide array of regression fixes and minor updates

2 years agostm32mp1: fix reference for STMicroelectronics
Patrick Delaunay [Fri, 20 May 2022 16:38:10 +0000 (18:38 +0200)]
stm32mp1: fix reference for STMicroelectronics

Replace reference to the correct name STMicroelectronics

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoconfigs: stm32mp: cleanup the stm32mp15 file
Patrick Delaunay [Wed, 15 Jun 2022 17:41:48 +0000 (19:41 +0200)]
configs: stm32mp: cleanup the stm32mp15 file

Remove STM32_SYSRAM_END and clean the comments in stm32mp15_common.h file
after moving some CONFIG to Kconfig: CONFIG_SYS_CBSIZE,
CONFIG_SPL_MAX_FOOTPRINT, CONFIG_SYS_SPL_MALLOC_START and
CONFIG_SYS_SPL_MALLOC_SIZE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agostm32mp: stpmic1: remove the debug unit request by debugger
Patrick Delaunay [Wed, 1 Jun 2022 16:33:40 +0000 (18:33 +0200)]
stm32mp: stpmic1: remove the debug unit request by debugger

Depending on backup register value, U-Boot SPL maintains the debug unit
powered-on for debugging purpose; only BUCK1 is required for powering
the debug unit, so revert the setting for all the other power lanes,
except BUCK3 that has to be always on.

To be functional this patch requires a modification in the debugger
,openocd for example, to update the STM32MP15 backup register when it is
required to debug SPL after reset. After deeper analysis this behavior
will be never supported in tools so the associated code, will be never
used and the associated code can be removed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoARM: stm32: activate OF_LIVE for DHSOM
Patrick Delaunay [Mon, 6 Jun 2022 14:04:16 +0000 (16:04 +0200)]
ARM: stm32: activate OF_LIVE for DHSOM

Activate the live DT with CONFIG_OF_LIVE to reduce the DT parsing
time.

Tested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoboard: dhelectronics: stm32mp1: convert to livetree
Patrick Delaunay [Mon, 6 Jun 2022 14:04:15 +0000 (16:04 +0200)]
board: dhelectronics: stm32mp1: convert to livetree

Replace call to fdt_*() functions and access to gd->fdt_blob
with call to ofnode_*() functions to support a live tree.

Tested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoboard: engicam: stm32mp1: convert to livetree
Patrick Delaunay [Thu, 19 May 2022 07:07:30 +0000 (09:07 +0200)]
board: engicam: stm32mp1: convert to livetree

Replace gd->fdt_blob access with fdt_getprop() function to the
function ofnode_get_property() to support a live tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoboard: stm32mp1: convert to livetree
Patrick Delaunay [Thu, 19 May 2022 07:07:29 +0000 (09:07 +0200)]
board: stm32mp1: convert to livetree

Replace gd->fdt_blob access with fdt_getprop() function to the
function ofnode_get_property() to support a live tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agomisc: stm32mp13: introduce STM32MP13 RCC driver
Patrick Delaunay [Thu, 19 May 2022 15:56:46 +0000 (17:56 +0200)]
misc: stm32mp13: introduce STM32MP13 RCC driver

Add the MISC RCC driver for STM32MP13, and bind it to the RCC reset
driver, required for initial support.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Change-Id: Ida11c15462caf140f87b1e3239efa2b8a689acb9

2 years agoclk: Add directory for STM32 clock drivers
Patrick Delaunay [Thu, 19 May 2022 15:56:45 +0000 (17:56 +0200)]
clk: Add directory for STM32 clock drivers

Add a directory in drivers/clk to regroup the clock drivers for all
STM32 Soc with CONFIG_ARCH_STM32 (MCUs with cortex M) or
CONFIG_ARCH_STM32MP (MPUs with cortex A).

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Acked-by: Sean Anderson <seanga2@gmail.com>
Change-Id: I955af307963f732167396f0157a30cf2fc91f150

2 years agostm32mp: fdt: update etzpc for STM32MP13x
Patrick Delaunay [Mon, 9 May 2022 15:13:22 +0000 (17:13 +0200)]
stm32mp: fdt: update etzpc for STM32MP13x

Add support of STM32MP13x the ETZPC part of fdt.c

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: If2777fbf66b8525a2a447056780aaa04e6b0a9a0

2 years agostm32mp: fdt: update etzpc for STM32MP15x
Patrick Delaunay [Mon, 9 May 2022 15:13:21 +0000 (17:13 +0200)]
stm32mp: fdt: update etzpc for STM32MP15x

Introduce STM32MP15 function and defines to prepare the
STM32MP13 introduction.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I909b205e73dcf207e0216aae5905c3c52472020e

2 years agodoc: st: stm32mp1: add STM32MP13x support
Patrick Delaunay [Fri, 20 May 2022 16:24:54 +0000 (18:24 +0200)]
doc: st: stm32mp1: add STM32MP13x support

Add in U-Boot documentation the quick instruction to
setup the STMicroelectronics STM32MP13x boards.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoconfigs: add stm32mp13 defconfig
Patrick Delaunay [Fri, 20 May 2022 16:24:53 +0000 (18:24 +0200)]
configs: add stm32mp13 defconfig

Add a initial config for STM32M13x SOC family, using the stm32mp135f-dk
device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoarm: dts: stm32mp: add stm32mp13 device tree for U-Boot
Patrick Delaunay [Fri, 20 May 2022 16:24:52 +0000 (18:24 +0200)]
arm: dts: stm32mp: add stm32mp13 device tree for U-Boot

Compile the device tree of STM32MP13x boards and add the needed
U-Boot add-on.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agommc: stm32_sdmmc2: make reset property optional
Patrick Delaunay [Fri, 20 May 2022 16:24:51 +0000 (18:24 +0200)]
mmc: stm32_sdmmc2: make reset property optional

Although not recommended, the reset property could be made optional.
This way the driver will probe even if no reset property is provided
in an sdmmc node in DT. This reset is already optional in Linux.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoram: stm32mp1: add support of STM32MP13x
Patrick Delaunay [Fri, 20 May 2022 16:24:50 +0000 (18:24 +0200)]
ram: stm32mp1: add support of STM32MP13x

Add support for new compatible "st,stm32mp13-ddr" to manage the
DDR sub system (Controller and PHY) in STM32MP13x SOC:
- only one AXI port
- support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2)

The STM32MP15x SOC have 2 AXI ports and 32 bits support.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoboard: stm32pm1: add stm32mp13 board support
Patrick Delaunay [Fri, 20 May 2022 16:24:49 +0000 (18:24 +0200)]
board: stm32pm1: add stm32mp13 board support

Add stm32mp15x prefix to all STM32MP15x board specific functions,
this patch is a preliminary step for STM32MP13x support.

This patch also adds the RCC probe to avoid circular access with
usbphyc probe as clk provider.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoddr: altera: soc64: Integer fix overflow that caused DDR size mismatched
Dinesh Maniyam [Wed, 1 Jun 2022 10:49:02 +0000 (18:49 +0800)]
ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched

Convert the constant integer to 'phys_size_t' to avoid overflow
when calculating the SDRAM size.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2 years agodrivers: cache: ncore: Disable snoop filter
Dinesh Maniyam [Wed, 1 Jun 2022 07:57:25 +0000 (15:57 +0800)]
drivers: cache: ncore: Disable snoop filter

There is hardware bug in NCORE CCU IP and it is causing an issue in the
coherent directory tracking of outstanding cache lines.
The workaround is disabling snoop filter.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2 years agoarm: dts: socfpga: stratix10: Add freeze controller node
Dinesh Maniyam [Tue, 31 May 2022 08:15:17 +0000 (16:15 +0800)]
arm: dts: socfpga: stratix10: Add freeze controller node

The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2 years agoarm: dts: socfpga: agilex: Add freeze controller node
Dinesh Maniyam [Tue, 31 May 2022 08:05:56 +0000 (16:05 +0800)]
arm: dts: socfpga: agilex: Add freeze controller node

The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2 years agoarch: arm: socfpga: timer_s10: Override udelay for secure section
Dinesh Maniyam [Wed, 1 Jun 2022 07:54:59 +0000 (15:54 +0800)]
arch: arm: socfpga: timer_s10: Override udelay for secure section

Override __udelay() as 'always inlined' function so that PSCI code
run in '__secure' section can call this delay function as well.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2 years agopinctrl: stm32: add support of STM32MP135
Patrick Delaunay [Fri, 20 May 2022 16:24:48 +0000 (18:24 +0200)]
pinctrl: stm32: add support of STM32MP135

Add support for "st,stm32mp135-pinctrl" for STM32MP13x

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoarm: stm32mp: support 2 MAC address for STM32MP13
Patrick Delaunay [Fri, 20 May 2022 16:24:47 +0000 (18:24 +0200)]
arm: stm32mp: support 2 MAC address for STM32MP13

Add support of several MAC address in OTP (3 32bits OTP word for
2 MAC address) for SOCs in  STM32MP13x family: STM32MP133 and STM32MP135.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoarm: stm32mp: add support of STM32MP13x
Patrick Delaunay [Fri, 20 May 2022 16:24:46 +0000 (18:24 +0200)]
arm: stm32mp: add support of STM32MP13x

Introduce the code in mach-stm32mp and the configuration file
stm32mp13_defconfig for the new STM32MP family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoarm: stm32mp: add CONFIG_STM32MP15_PWR
Patrick Delaunay [Fri, 20 May 2022 16:24:45 +0000 (18:24 +0200)]
arm: stm32mp: add CONFIG_STM32MP15_PWR

Add config CONFIG_STM32MP15_PWR to handle the
access to regulators managed by the PWR driver defined in
pwr_regulator.c

This driver is only used in U-Boot by STM32MP15x family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoarm: stm32mp: add sub config Kconfig.15x
Patrick Delaunay [Fri, 20 May 2022 16:24:44 +0000 (18:24 +0200)]
arm: stm32mp: add sub config Kconfig.15x

Add sub Kconfig for each SOC in the STM32 CPU family.

It is a preliminary step to introduce a new SOC in the STM32MP family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoarm: stm32mp: add choice for STM32MP SOC family
Patrick Delaunay [Fri, 20 May 2022 16:24:43 +0000 (18:24 +0200)]
arm: stm32mp: add choice for STM32MP SOC family

Add mandatory choice for SOC support in ARCH_STM32MP.

This patch is a preliminary step for new SOC introduction
in STM32MP family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoarm: stm32mp: move code for STM32MP15x
Patrick Delaunay [Fri, 20 May 2022 16:24:42 +0000 (18:24 +0200)]
arm: stm32mp: move code for STM32MP15x

Move code and defines only needed for CONFIG_STM32MP15x in stm32mp15x.c
when low level init without TFABOOT is supported.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoarm: stm32mp: move the get_otp helper function in bsec
Patrick Delaunay [Fri, 20 May 2022 16:24:41 +0000 (18:24 +0200)]
arm: stm32mp: move the get_otp helper function in bsec

As the get_otp() helper function in bsec are common for all STM32MP family,
move this function in bsec driver

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoconfigs: stm32mp1: move SUPPORT_SPL in STM32MP15x
Patrick Delaunay [Fri, 20 May 2022 16:24:40 +0000 (18:24 +0200)]
configs: stm32mp1: move SUPPORT_SPL in STM32MP15x

The SPL is only supported by STM32MP15x not by all the
SOC with STM32MP arch.
Only TFABOOT is supported in next products.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoARM: dts: stm32: add STM32MP13 SoCs support
Patrick Delaunay [Fri, 20 May 2022 16:24:39 +0000 (18:24 +0200)]
ARM: dts: stm32: add STM32MP13 SoCs support

Add initial support of STM32MP13 family based on v5.18-rc2

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoARM: dts: stm32: Add DHCOR based DRC Compact board
Marek Vasut [Mon, 13 Jun 2022 09:55:21 +0000 (11:55 +0200)]
ARM: dts: stm32: Add DHCOR based DRC Compact board

Add DT for DH DRC Compact unit, which is a universal controller device.
The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD
card slot, eMMC and SDIO Wi-Fi.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoARM: dts: stm32: Add alternate pinmux for SPI2 pins
Marek Vasut [Mon, 13 Jun 2022 09:55:20 +0000 (11:55 +0200)]
ARM: dts: stm32: Add alternate pinmux for SPI2 pins

Add another mux option for SPI2 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoARM: dts: stm32: Add alternate pinmux for CAN1 pins
Marek Vasut [Mon, 13 Jun 2022 09:55:19 +0000 (11:55 +0200)]
ARM: dts: stm32: Add alternate pinmux for CAN1 pins

Add another mux option for CAN1 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoARM: dts: stm32: Add alternate pinmux for UART5 pins
Marek Vasut [Mon, 13 Jun 2022 09:55:18 +0000 (11:55 +0200)]
ARM: dts: stm32: Add alternate pinmux for UART5 pins

Add another mux option for UART5 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoARM: dts: stm32: Add alternate pinmux for UART4 pins
Marek Vasut [Mon, 13 Jun 2022 09:55:17 +0000 (11:55 +0200)]
ARM: dts: stm32: Add alternate pinmux for UART4 pins

Add another mux option for UART4 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoARM: dts: stm32: Add alternate pinmux for UART3 pins
Marek Vasut [Mon, 13 Jun 2022 09:55:16 +0000 (11:55 +0200)]
ARM: dts: stm32: Add alternate pinmux for UART3 pins

Add another mux option for UART3 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agostm32mp: stm32prog: fix the last character of dfu_alt_add third parameter
Patrick Delaunay [Thu, 16 Jun 2022 16:37:59 +0000 (18:37 +0200)]
stm32mp: stm32prog: fix the last character of dfu_alt_add third parameter

The third parameter of dfu_alt_add(), the string description of alternate,
is build in stm32prog_alt_add() with a unnecessary character ';' at the
end of the string.

This separator was required in the first implementation of
dfu_alt_add() but is no more needed in the current implementation;
this separator is managed only in dfu_config_interfaces() which call
dfu_alt_add() for this parameter without this separator.

And since the commit 53b406369e9d ("DFU: Check the number of arguments
and argument string strictly"), this added character cause an error when
the stm32prog command is executed because the third parameter of
dfu_alt_add() must be a string with a numerical value; 's' must be NULL
in the result of call in dfu_fill_entity_mmc():
  third_arg = simple_strtoul(argv[2], &s, 0);

Fixes: 53b406369e9d ("DFU: Check the number of arguments and argument string strictly")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agonet: Fix discuss discard typo
Marek Vasut [Sun, 1 May 2022 16:43:55 +0000 (18:43 +0200)]
net: Fix discuss discard typo

Replace discuss with discard, that is what happens with packet with
incorrect checksum. Fix the typo.

Fixes: 4b37fd146bb ("Convert CONFIG_UDP_CHECKSUM to Kconfig")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
2 years agotools: binman: install btool
Peng Fan [Tue, 14 Jun 2022 10:42:07 +0000 (18:42 +0800)]
tools: binman: install btool

btool is needed after install binman to system.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2 years agoboard: ti: am335x: eth_cpsw should depend on CONFIG_NET
Corentin LABBE [Tue, 14 Jun 2022 08:44:07 +0000 (08:44 +0000)]
board: ti: am335x: eth_cpsw should depend on CONFIG_NET

The origin of this patch is the breaking of am335x-hs boot
due to commit e41651fffda7 ("dm: Support parent devices with of-platdata")
HS boards have less SRAM for SPL and so this commit increased memory usage beyond am335x limit.
This commit added 10 driver binding pass and am335x boot only if one pass is done.
SPL try to do more than one pass due to eth_cpsw failing.
Since HS SPL does not need network (and NET is already disabled in config),
the easiest fix is to "remove" eth_cpsw from SPL by testing if NET is enabled.

Signed-off-by: Corentin LABBE <clabbe@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Andrew Davis <afd@ti.com>
2 years agoarmv8: always use current exception level for TCR_ELx access
Andre Przywara [Mon, 13 Jun 2022 23:11:10 +0000 (00:11 +0100)]
armv8: always use current exception level for TCR_ELx access

Currently get_tcr() takes an "el" parameter, to select the proper
version of the TCR_ELx system register.
This is problematic in case of the Apple M1, since it runs with
HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout,
and we get the wrong version.

For U-Boot's purposes the only sensible choice here is the current
exception level, and indeed most callers treat it like that, so let's
remove that parameter and read the current EL inside the function.
This allows us to check for the E2H bit, and pretend it's EL1 in this
case.

There are two callers which don't care about the EL, and they pass 0,
which looks wrong, but is irrelevant in these two cases, since we don't
use the return value there. So the change cannot affect those two.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2 years agoarm64: dts: imx8mq-kontron-pitx-imx8m-u-boot.dtsi: disable assigned clocks
Heiko Thiery [Sat, 11 Jun 2022 06:09:04 +0000 (08:09 +0200)]
arm64: dts: imx8mq-kontron-pitx-imx8m-u-boot.dtsi: disable assigned clocks

With the move to use DM_CLK the boards uart stops working. The used
properties are not supported by the imx8mq clock driver. Thus
the correct baudrate cannot be selected. Remove this properties here and
the board can start with working uart. Keep it in the main dts because
linux handles these porperties fine.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
2 years agousb: host: ehci-generic: Make resets and clocks optional
Andre Przywara [Tue, 7 Jun 2022 23:42:22 +0000 (00:42 +0100)]
usb: host: ehci-generic: Make resets and clocks optional

The generic EHCI binding does not *require* resets and clocks
properties, and indeed for instance the Allwinner A20 SoCs does not
need or define any resets in its DT.

Don't easily give up if clk_get_bulk() or reset_get_bulk() return an
error, but check if that is due to the DT simply having no entries for
either of them.

This fixes USB operation on all boards with an Allwinner A10 or A20 SoC,
which were reporting an error after commit ba96176ab70e2999:
=======================
Bus usb@1c14000: ehci_generic usb@1c14000: Failed to get resets (err=-2)
probe failed, error -2
=======================

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agofs/squashfs: sqfs_read: Prevent arbitrary code execution
Miquel Raynal [Thu, 9 Jun 2022 14:02:06 +0000 (16:02 +0200)]
fs/squashfs: sqfs_read: Prevent arbitrary code execution

Following Jincheng's report, an out-of-band write leading to arbitrary
code execution is possible because on one side the squashfs logic
accepts directory names up to 65535 bytes (u16), while U-Boot fs logic
accepts directory names up to 255 bytes long.

Prevent such an exploit from happening by capping directory name sizes
to 255. Use a define for this purpose so that developers can link the
limitation to its source and eventually kill it some day by dynamically
allocating this array (if ever desired).

Link: https://lore.kernel.org/all/CALO=DHFB+yBoXxVr5KcsK0iFdg+e7ywko4-e+72kjbcS8JBfPw@mail.gmail.com
Reported-by: Jincheng Wang <jc.w4ng@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Jincheng Wang <jc.w4ng@gmail.com>
2 years agoodroid_xu3: Fix board environment variable
Tom Rini [Wed, 8 Jun 2022 18:30:14 +0000 (14:30 -0400)]
odroid_xu3: Fix board environment variable

When migrating CONFIG_CONS_INDEX to Kconfig, on this platform we changed
what "board" evaluated to in the environment.  This in turn meant that
we would no longer try and find the correct fdtfile via the normal
distro boot logic.  Fix this by overriding board in the default
environment, as done on other platforms where CONFIG_SYS_BOARD is not
what we want to be in the board environment variable.

Fixes: f76750d11133 ("Convert CONFIG_CONS_INDEX et al to Kconfig")
Reported-by: Gabriel Hojda <ghojda@yo2urs.ro>
Tested-by: Gabriel Hojda <ghojda@yo2urs.ro>
Signed-off-by: Tom Rini <trini@konsulko.com>
2 years ago.gitignore: add files produced by b4
Andrey Zhizhikin [Tue, 7 Jun 2022 08:13:00 +0000 (10:13 +0200)]
.gitignore: add files produced by b4

b4 utility [1] is introduced by Linux Kernel developers and used to
fetch patches and patch series from lore.kernel.org and is proven
to be useful for U-Boot development. Detailed usage of the tool can be
read under post from the original author [2].

This tool fetches files from the list and populates the source folder
with additional files (*.cover and *.mbx) which are not ignored by git
and shown as newly added files.

Add those file patterns into .gitignore file, so they can be safely
skipped during changes attestation.

Link: [1]: https://pypi.org/project/b4/
Link: [2]: https://people.kernel.org/monsieuricon/introducing-b4-and-patch-attestation
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agoarch: arm: mach-k3: am642_init: bring back MCU_PADCFG_MMR1 unlock
Christian Gmeiner [Thu, 12 May 2022 06:21:01 +0000 (08:21 +0200)]
arch: arm: mach-k3: am642_init: bring back MCU_PADCFG_MMR1 unlock

Without this register unlock it is not possible to configure the
pinmux used for mcu spi0.

Fixes: 92e46092f2 ("arch: arm: mach-k3: am642_init: Probe ESM nodes")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2 years agoUpdate email address and company name
Christophe Leroy [Thu, 12 May 2022 14:21:53 +0000 (16:21 +0200)]
Update email address and company name

This patch updates my email address and company name.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>