Haiying Wang [Wed, 16 Jan 2008 22:12:12 +0000 (17:12 -0500)]
FSL: Fix common EEPROM_data structure definition
- Fix EEPROM_data structure definition according to System EEPROM Data Format.
- Read MAC addresses from EEPROM to ethXaddr before saving ethXaddr to
bd->bi_ethaddr.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Ben Warren [Thu, 17 Jan 2008 03:37:35 +0000 (22:37 -0500)]
Add support for a Freescale non-CPM SPI controller
This patch adds support for the SPI controller found on Freescale PowerPC
processors such as the MCP834x family. Additionally, a new config option,
CONFIG_HARD_SPI, is added for general purpose SPI controller use.
Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Matthias Fuchs [Thu, 17 Jan 2008 06:45:05 +0000 (07:45 +0100)]
net: add 'ethrotate' environment variable
[PATCH] net: add 'ethrotate' environment variable
This patch replaces the buildtime configuration option
CONFIG_NET_DO_NOT_TRY_ANOTHER through the 'ethrotate' runtime
configuration veriable. See README.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Niklaus Giger [Wed, 16 Jan 2008 17:39:20 +0000 (18:39 +0100)]
ppc4xx: Netstal HCU4 board: added various fixes and POST
- Moved some common code to netstal/common/nm_bsp.c.
- sdram initialisation goes go netstal/common/fixed_sdram.c.
- Added support for POST.
- Stylistic cleanups (multi-line comments/ enforce 80 colomn width)
Niklaus Giger [Thu, 17 Jan 2008 11:53:56 +0000 (12:53 +0100)]
ppc4xx: netstal/common define routines used by all boards
Added some routines used by all Netstal boards:
- nm_bsp.c: - nm_show_print and
- common_misc_init_r
- set_params_for_sw_install. Very specific code to handle our SW
installation procedure
- fixed_sdram.c: Common routines for HCU4 (and upcoming) MCU25 boards
to handle sdram initialization.
- nm.h: Common header
Niklaus Giger [Wed, 16 Jan 2008 17:39:18 +0000 (18:39 +0100)]
ppc4xx: Netstal HCU5 board: added various fixes and POST
- Moved some common code to nestal/common/nm_bsp.c.
- Added support for the vxWorks EDR.
- Enable trace for Lauterbach, if present.
- Added support for POST.
- Stylistic cleanups (multi-line comments/ enforce 80 colomn width)
Kumar Gala [Thu, 17 Jan 2008 04:38:34 +0000 (22:38 -0600)]
85xx: Reworked initial processor init
Reworked the initial processor initialzation sequence:
* introduced cpu_early_init_f that is run in address space 1 (AS=1)
* Moved TLB/LAW and CCSR init into cpu_early_init_f()
* Reworked initial asm code to do most of the core init before TLBs
The main reasons for these changes are to allow handling of 36-bit phys
addresses in the future and some of the issues that will exist when we
do that.
There are a few caveats on what can be initialized via the LAW and TLB
static tables:
* TLB entry 14/15 can't be initialized via the TLB table
* any LAW that covers the implicit boot window (4G-8M to 4G) must map to
the code that is currently executing.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 17 Jan 2008 04:33:22 +0000 (22:33 -0600)]
85xx: Introduce new tlb API
Add a set of functions to manipulate TLB entries:
* set_tlb() - write a tlb entry
* invalidate_tlb() - invalidate a tlb array
* disable_tlb() - disable a variable size tlb entry
* init_tlbs() - setup initial tlbs based on static table
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 16 Jan 2008 16:04:42 +0000 (10:04 -0600)]
85xx: Use proper defines for PCI addresses
We should be using the _MEM_PHYS for LAW and TLB setup and not _MEM_BASE.
While _MEM_BASE & _MEM_PHYS are normally the same, _MEM_BASE should only
be used for configuring the PCI ATMU.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
drivers/net/rtl8139.c: rx_status should be le32_to_cpu(rx_status).
rx_status on the memory is basically in LE, but needs to be handled in CPU
endian. le32_to_cpu() takes up this mission. Even if on the sane hardware,
it'll work fine.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Cc: Masami Komiya <mkomiya@sonare.it> Cc: Lucas Jin <lucasjin@gmail.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
"to = (currticks() + RTL_TIMEOUT)" has possibilities to wrap around. If it
does, the condition "(currticks() < to)" becomes invalid and immediately
leads to tx timeout error. This patch introduces the fine-graded udely(10)
loops to ease the impact of wrapping around.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Cc: Masami Komiya <mkomiya@sonare.it> Cc: Lucas Jin <lucasjin@gmail.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Joakim Tjernlund [Wed, 16 Jan 2008 08:40:41 +0000 (09:40 +0100)]
Remove annoying debug printout for PHY less boards.
PHY less board prints out lots of "read wrong ...":
read wrong value : mii_id 3,mii_reg 2, base e0102320
read wrong value : mii_id 3,mii_reg 3, base e0102320
UEC: PHY is Generic MII (ffffffff)
read wrong value : mii_id 3,mii_reg 4, base e0102320
read wrong value : mii_id 3,mii_reg 0, base e0102320
read wrong value : mii_id 3,mii_reg 1, base e0102320
read wrong value : mii_id 3,mii_reg 1, base e0102320
read wrong value : mii_id 3,mii_reg 5, base e0102320
read wrong value : mii_id 3,mii_reg 1, base e0102320
read wrong value : mii_id 3,mii_reg 1, base e0102320
read wrong value : mii_id 3,mii_reg 5, base e0102320
FSL UEC0: Full Duplex
FSL UEC0: Speed 100BT
FSL UEC0: Link is up
Using FSL UEC0 device
Make this printout depend on UEC_VERBOSE_DEBUG and
remove its definition in uec_phy.c
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Kim Phillips [Tue, 15 Jan 2008 20:11:00 +0000 (14:11 -0600)]
net: reduce boot latency on QE UEC based boards
actually polling for PHY autonegotiation to finish enables us to remove the
5 second boot prompt latency present on QE based boards.
call to qe_set_mii_clk_src in init_phy, and mv call to init_phy from
uec_initialize to uec_init by Joakim Tjernlund; autonegotiation wait
code shamelessly stolen from tsec driver.
also rm unused CONFIG_RMII_MODE code.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
TSEC driver: Change MDIO support to allow access to any PHYs on the MDIO bus
The current TSEC driver limits MDIO access to the devices that have been configured as attached
to a TSEC MAC. This patch allows access to any PHY device on the MDIO bus through the 'mii' commands.
Signed-off-by: Michael Firth <michael.firth@bt.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Kim Phillips [Wed, 16 Jan 2008 06:38:05 +0000 (00:38 -0600)]
Add support for the MPC837xERDB
MPC837xERDB board support includes:
* DDR2 330MHz hardcoded (soldered on the board)
* Local Bus NOR Flash
* I2C, UART and RTC
* eTSEC RGMII (TSEC0 - RTL8211B with MII;
* TSEC1 - VSC7385 local bus, hardcoded, requires seperate firmware
* load)
Signed-off-by: Kevin Lam <kevin.lam@freescale.com> Signed-off-by: Joe D'Abbraccio <joe.d'abbraccio@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Kim Phillips [Wed, 16 Jan 2008 18:06:16 +0000 (12:06 -0600)]
mpc83xx: add support for more system clock performance controls
System registers that are modified are the Arbiter Configuration
Register (ACR), the System Priority Control Register (SPCR), and the
System Clock Configuration Register (SCCR).
Signed-off by: Michael F. Reiss <Michael.F.Reiss@freescale.com>
Signed-off by: Joe D'Abbraccio <ljd015@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
James Yang [Wed, 16 Jan 2008 17:58:08 +0000 (11:58 -0600)]
FSL: Generalize PIXIS reset command parsing.
Before, the order of arguments to the pixis_reset
command needed to be supplied in a hard-coded order.
Generalize the command parsing to allow any order.
Signed-off-by: James Yang <james.yang@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com>
Jon Loeliger [Tue, 15 Jan 2008 19:42:41 +0000 (13:42 -0600)]
FSL: Convert board/freescale/common/Makefile to use CONFIG_
Convert the board/freescale/common/Makefile to use
CONFIG_* options to select which files to conditionally
compile into the board/freescale/common library rather
than conditionally compiling entire files.
Now handles::
CONFIG_FSL_PIXIS
CONFIG_FSL_DIU_FB
CONFIG_PQ_MDS_PIB
CONFIG_ID_EEPROM is introduced until CFG_ID_EEPROM is gone.
Kim Phillips [Tue, 15 Jan 2008 15:51:12 +0000 (09:51 -0600)]
mpc83xx: clean up mpc8360emds.c warnings
mpc8360emds.c: In function 'ft_board_setup':
mpc8360emds.c:327: warning: assignment makes pointer from integer without a cast
mpc8360emds.c:329: warning: passing argument 2 of 'fdt_getprop' makes integer from pointer without a cast
mpc8360emds.c:334: warning: passing argument 2 of 'fdt_setprop' makes integer from pointer without a cast
mpc8360emds.c:341: warning: assignment makes pointer from integer without a cast
mpc8360emds.c:343: warning: passing argument 2 of 'fdt_getprop' makes integer from pointer without a cast
mpc8360emds.c:348: warning: passing argument 2 of 'fdt_setprop' makes integer from pointer without a cast
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Poonam Aggrwal [Mon, 14 Jan 2008 04:11:14 +0000 (09:41 +0530)]
Changes in uboot DDR configuration for MPC8313eRDB
These changes were identified by HighSmith Bill ,Mazzyar and Joseph for
DDR configuration in u-boot code. Some are related to performance, some
affect stability and some correct few basic errors in the current
configuration.
The changes have been tested and found to give better memory latency
figures on MPC8313eRDB.LMBench figures prove it.
The changes are:
- CS0_CONFIG[ AP_n_EN] is changed from 1 to 0
(this may improve performance for application with many read
or write to open pages).
- CS0_CONFIG[ODT_WR_CFG] is currently changed from 100 to
001 (activating all the CS when only one is used may cause
unwanted noise on the system)
- TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 8clks (based on
Tras=45ns)
- TIMING_CFG_1[REFREC] changed from 21 clks to 18clks.
- TIMING_CFG_2[AL] value changed from 0 setting to 1 clk to
comply with the 3 ODT clk requirements)
- TIMING_CFG_2[CPO] was set to a reserved value, changed to RL+3/4.
- TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 6clks.
- DDR_SDRAM_MODE[AL]changed from 0 to 1.
- DDR_SDRAM_MODE[WRREC] changed from 1 clk to 3 clks.
- DDR_SDRAM_INTERVAL[REFINT] is changed from 0x0320 to 0x0510.
- DDR_SDRAM_INTERVAL[BSTOPRE] is changed from 0x64 to 0x0500.
Jerry Van Baren [Sat, 12 Jan 2008 18:24:14 +0000 (13:24 -0500)]
Enable the isdram command on the MPC8360EMDS board
The isdram command prints out decoded information the "serial presence
detect" (SPD) chip on the SDRAM SIMMs. This can be very helpful when
debugging memory configuration problems.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Dave Liu [Fri, 11 Jan 2008 10:48:24 +0000 (18:48 +0800)]
mpc83xx: Add the support for MPC8315ERDB board
The features list:
- Boot from NOR Flash
- DDR2 266MHz hardcoded configuration
- Local bus NOR Flash R/W operation
- I2C, UART, MII and RTC
- eTSEC0/1 support
- PCI host
Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Larry Johnson [Tue, 15 Jan 2008 19:35:58 +0000 (14:35 -0500)]
ppc4xx: Refactor ECC POST for AMCC Denali core
The ECC POST reported intermittent failures running after power-up on
the Korat PPC440EPx board. Even when the test passed, the debugging
output occasionally reported additional unexpected ECC errors.
This refactoring has three main objectives: (1) minimize the code
executed with ECC enabled during the tests, (2) add more checking of the
results so any unexpected ECC errors would cause the test to fail, and
(3) use synchronization (only) where required by the processor.
David Saada [Tue, 15 Jan 2008 08:40:24 +0000 (10:40 +0200)]
QE UEC: Extend number of supported UECs to 4
This patch extends the number of supported UECs to 4. Note that the
problem of QE thread resources exhaustion is resolved by setting the
correct number of QE threads according to Ethernet type (GBE or FE).
Signed-off-by: David Saada <david.saada@ecitele.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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