]> git.dujemihanovic.xyz Git - u-boot.git/log
u-boot.git
2 years agoarm64: zynqmp: Add PHY description for SGMII on vck190 SC
Michal Simek [Wed, 11 May 2022 09:52:52 +0000 (11:52 +0200)]
arm64: zynqmp: Add PHY description for SGMII on vck190 SC

SGMII requires phy to be configured. The support for this has been added to
Linux and U-Boot already that's why also describe the phy via DT. Clock is
coming from si5332 chip (output 1) 125MHz which is only one GT line use on
this board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8ad8d0c2fc9690cc90f95feddf87b0e94a685a43.1652262769.git.michal.simek@amd.com
2 years agoRevert "arm64: zynqmp: Add zynqmp firmware specific DT nodes"
T Karthik Reddy [Wed, 11 May 2022 09:52:51 +0000 (11:52 +0200)]
Revert "arm64: zynqmp: Add zynqmp firmware specific DT nodes"

This reverts commit 50a6bd000f94832658f42fb01b9aaf9e39a52004.

As zynqmp mini emmc does not rely on firmware, remove firmware related
device tree modes from zynqmp mini emmc dts files.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e69b30d82b0307c563fe72630d9172e53964aeda.1652262769.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Add dmas, gpu, rtc, watchdogs and opp nodes for SOM
Michal Simek [Wed, 11 May 2022 09:52:50 +0000 (11:52 +0200)]
arm64: zynqmp: Add dmas, gpu, rtc, watchdogs and opp nodes for SOM

There are couple of IPs which are enabled in origin HW design which are
missing in SOM dt. Add them to match default setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/901401beacbea5931fc18cde20c157e5978a7023.1652262769.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Add pwm-fan node and fix ttc0 pwm-cells property
Vishal Patel [Wed, 11 May 2022 09:52:49 +0000 (11:52 +0200)]
arm64: zynqmp: Add pwm-fan node and fix ttc0 pwm-cells property

Add pwm-fan node to control fan through hwmon and change
pwm-cells property to 3 to allow fancontrol utility to
function correctly.

Signed-off-by: Vishal Patel <vishal.patel@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/21b4dfce3e45136a468974ea3dedca03320e27b8.1652262769.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Add power domain description for PL
Michal Simek [Wed, 11 May 2022 09:52:48 +0000 (11:52 +0200)]
arm64: zynqmp: Add power domain description for PL

PL has own power domain which is not described in DT. That's why add it
there by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b38e2ea95dab434bc007f9ed6c438c68149744bf.1652262769.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Fix opp-table-cpu
Michal Simek [Wed, 11 May 2022 09:52:47 +0000 (11:52 +0200)]
arm64: zynqmp: Fix opp-table-cpu

OPP table name now should start with "opp-table" and OPP entries
shouldn't contain commas and @ signs in accordance to the new schema
requirement.

The same change was done in Linux by commit c6d4a8977598 ("ARM: tegra:
Rename CPU and EMC OPP table device-tree nodes"), commit ffbe853a3f5a
("ARM: dts: sunxi: Fix OPPs node name") or commit b7072cc5704d ("arm64:
dts: qcom: qcs404: Rename CPU and CPR OPP tables").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a1176349448df35127dbac15c1eeb2229505bae7.1652262769.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Add gpio labels for modepin
Michal Simek [Wed, 11 May 2022 09:52:46 +0000 (11:52 +0200)]
arm64: zynqmp: Add gpio labels for modepin

Using labels helps with better identifications of chips.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/15b0f68077fb3c86d438caf8562de87367361c60.1652262769.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Add mode-pin GPIO controller DT node
Piyush Mehta [Wed, 11 May 2022 09:52:45 +0000 (11:52 +0200)]
arm64: zynqmp: Add mode-pin GPIO controller DT node

Add mode-pin GPIO controller DT node in zynqmp.dtsi and also setup default
reset-gpios property for usb which is default Xilinx setup.

Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f2a1f6f541c41075ea36062857031bfc28d6d303.1652262769.git.michal.simek@amd.com
2 years agoarm64: zynqmp: zynqmp-sm-k26-revA: Fix DP PLL configuration
Neal Frager [Mon, 16 May 2022 14:02:19 +0000 (16:02 +0200)]
arm64: zynqmp: zynqmp-sm-k26-revA: Fix DP PLL configuration

This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som.

The Linux DP driver expects the DP to be using the following PLL config:
  - DP video PLL should use the VPLL (0x0)
  - DP audio PLL should use the RPLL (0x3)
  - DP system time clock PLL should use RPLL (0x3)

Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.
Register 0xFD1A007C configures the DP system time clock PLL.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com
2 years agophy: zynqmp: Increase timeout value to 10ms
Ashok Reddy Soma [Tue, 10 May 2022 13:12:34 +0000 (07:12 -0600)]
phy: zynqmp: Increase timeout value to 10ms

Observing psgtr pll timeouts with some usb hubs and devices behind it.
Increase timeout to 10ms to take care of it.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220510131234.2650-1-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoarm64: zynqmp: Set qspi tx-buswidth to 4
Amit Kumar Mahapatra [Tue, 10 May 2022 14:33:01 +0000 (16:33 +0200)]
arm64: zynqmp: Set qspi tx-buswidth to 4

In all the ZynqMP boards dts files tx-buswidth is by default set to 1. Due
to this the framework only issues 1-1-1 write commands to the GQSPI driver.
But the GQSPI controller is capable of handling 1-4-4 write commands, so
updated the tx-buswidth to 4 in ZynqMP boards dts files. This would enable
the spi-nor framework to issue 1-4-4 write commands instead of 1-1-1. This
will increase the tx data transfer rate, as now the tx data will be
transferred on four lines instead on single line.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ad61199f55e5e00f29de6206d9d1872a52a7657e.1652193179.git.michal.simek@amd.com
2 years agoxilinx: zynqmp: Do not guard SPL_FS_LOAD_PAYLOAD_NAME by SDHCI driver
Michal Simek [Tue, 10 May 2022 14:23:02 +0000 (16:23 +0200)]
xilinx: zynqmp: Do not guard SPL_FS_LOAD_PAYLOAD_NAME by SDHCI driver

CONFIG_SPL_FS_LOAD_PAYLOAD_NAME is used by set_dfu_alt_info() for string
generation. It doesn't depend on SDHCI because the same file can be stored
to other non volatile memories like qspi.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/97434e122c6f8f042330b60d3e8de4c31f3e3f93.1652192580.git.michal.simek@amd.com
Link: https://lore.kernel.org/r/718de136c68c9a76fc7b4e536a727f401b05bfb9.1652702625.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Fix split mode reset functionality
Neal Frager [Wed, 4 May 2022 07:12:26 +0000 (09:12 +0200)]
arm64: zynqmp: Fix split mode reset functionality

This patch fixes two issues in the set_r5_reset function.

1. When in split mode, the lpd_amba_rst bit should only be set when
both r5 cpu cores are in reset. Otherwise, if one r5 core is still
running, setting the lpd_amba_rst bit will cause an error for the
running core. The set_r5_reset function has been modified to check
if the other r5 core is still running before setting the lpd_amba_rst
bit.

2. The cpu_disable function was always assuming that the r5 cores
are in split mode when resetting either core 4 or 5. This is
incorrect for lockstep functionality. This patch adds a function
check_r5_mode to handle the cpu_disable function correctly for
the r5 cores by checking the mode and handling the reset appropriately.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d99cbd7f2394ac055ef27457298f554ff0747ba7.1651648344.git.michal.simek@amd.com
2 years agoarm64: zynqmp: zynqmp-zcu102-revA: Fix DP PLL configuration
Neal Frager [Thu, 5 May 2022 08:55:51 +0000 (10:55 +0200)]
arm64: zynqmp: zynqmp-zcu102-revA: Fix DP PLL configuration

This patch fixes the DP audio and video PLL configurations for the
zynqmp-zcu102-revA evaluation board.

The Linux DP driver expects the DP to be using the following PLL config:
  - DP video PLL should use the VPLL (0x0)
  - DP audio PLL should use the RPLL (0x3)

Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b2eb87758e0cd4844e1754da8c58fce58d9cf683.1651740949.git.michal.simek@amd.com
2 years agoarm64: zynqmp: zynqmp-zcu106-revA: Fix DP PLL configuration
Neal Frager [Thu, 5 May 2022 08:56:29 +0000 (10:56 +0200)]
arm64: zynqmp: zynqmp-zcu106-revA: Fix DP PLL configuration

This patch fixes the DP audio and video PLL configurations
for the zynqmp-zcu106-revA evaluation board.

The Linux DP driver expects the DP to be using the following PLL config:
  - DP video PLL should use the VPLL (0x0)
  - DP audio PLL should use the RPLL (0x3)

Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/62538b4a04dee28a6fc8ac5b85f8c845a5a76aa4.1651740988.git.michal.simek@amd.com
2 years agoarm64: zynqmp: zynqmp-zcu106-rev1.0: Fix DP PLL configuration
Neal Frager [Tue, 10 May 2022 14:18:42 +0000 (16:18 +0200)]
arm64: zynqmp: zynqmp-zcu106-rev1.0: Fix DP PLL configuration

This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-rev1.0 evaluation board.

The Linux DP driver expects the DP to be using the following PLL config:
  - DP video PLL should use the VPLL (0x0)
  - DP audio PLL should use the RPLL (0x3)

Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ae42ad6185418713a473660c8d15903299af7764.1652192319.git.michal.simek@amd.com
2 years agommc: zynq_sdhci: Add weak function prototype
T Karthik Reddy [Wed, 27 Apr 2022 08:27:12 +0000 (10:27 +0200)]
mmc: zynq_sdhci: Add weak function prototype

zynqmp_pm_is_function_supported() which checks feature support on som,
which is implemented in firmware_zynqmp.c driver. As mini configuration
does not use firmware driver, so create a weak function to avoid
compilation error on zynqmp mini configuration.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/c60655a509956b8fc3a81671a7dc51157f3973db.1651048030.git.michal.simek@xilinx.com
2 years agoRevert "arm64: xilinx: Set CONFIG_ZYNQMP_FIRMWARE config for mini emmc"
T Karthik Reddy [Wed, 27 Apr 2022 08:30:45 +0000 (10:30 +0200)]
Revert "arm64: xilinx: Set CONFIG_ZYNQMP_FIRMWARE config for mini emmc"

This reverts commit 122ca834f2f4a9d70abeece3d1ff200a3556ab24.

Disable CONFIG_ZYNQMP_FIRMWARE config from zynqmp & versal mini emmc
defconfig files, as mini emmc does not use any firmware.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/f73a50980d3af894f1e86cfc98742dbdec573760.1651048242.git.michal.simek@xilinx.com
2 years agoxilinx: Handle board_get_usable_ram_top(0) properly
Michal Simek [Fri, 29 Apr 2022 09:52:27 +0000 (11:52 +0200)]
xilinx: Handle board_get_usable_ram_top(0) properly

board_get_usable_ram_top() was designed for getting the top most location
for U-Boot allocation that's why function itself supports via total_size
parameter to find out where the right location for U-Boot is.
But function itself is also reused by different (EFI) which is passing
total_size as 0 to find out where the usable ram top is. For this case
doesn't make sense (a waste time) to call any lmb functions.
That's why simply return gd->ram_top.

And gd->ram_top is filled already based on previous call for U-Boot iself.
The same solution is also used by stm32mp by commit 92b611e8b003 ("stm32mp:
correctly handle board_get_usable_ram_top(0)") and commit c8510e397fad
("stm32mp: Fix board_get_usable_ram_top()").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/44470619e74f3e480b70deac24578e3e0d5c907e.1651225945.git.michal.simek@amd.com
2 years agosoc: xilinx: zynqmp: fix out of bounds array access
Michal Simek [Wed, 20 Apr 2022 07:39:04 +0000 (09:39 +0200)]
soc: xilinx: zynqmp: fix out of bounds array access

The call to xilinx_pm_request requires an array of a larger size.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/5f1409de285d7454af171a54e5f115da9d82c44e.1650440343.git.michal.simek@xilinx.com
2 years agosoc: xilinx: versal: fix out of bounds array access
Jorge Ramirez-Ortiz [Sat, 16 Apr 2022 18:15:30 +0000 (20:15 +0200)]
soc: xilinx: versal: fix out of bounds array access

The call to xilinx_pm_request requires an array of a larger size.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Link: https://lore.kernel.org/r/20220416181530.2311155-1-jorge@foundries.io
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2 years agoMerge branch '2022-05-11-Kconfig-cleanups-etc'
Tom Rini [Wed, 11 May 2022 17:27:44 +0000 (13:27 -0400)]
Merge branch '2022-05-11-Kconfig-cleanups-etc'

- Migrate CONFIG_MTD_CONCAT to Kconfig, use CONFIG_VAL/IS_ENABLED in
  more places, rename SPL_LEGACY_IMAGE_SUPPORT to
  SPL_LEGACY_IMAGE_FORMAT and update some related dependencies for TI
  platforms.

2 years agoMakefile: update warning about CONFIG_OF_EMBED
Ralph Siemsen [Thu, 28 Apr 2022 19:52:59 +0000 (15:52 -0400)]
Makefile: update warning about CONFIG_OF_EMBED

Update the diagnostic message with revised location of document, which
changed in 3e9fddfc4f1 ("doc: Move devicetree control doc to rST")

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
2 years agoboard_r: use IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) in board_init_r()
Ovidiu Panait [Mon, 2 May 2022 15:34:56 +0000 (18:34 +0300)]
board_r: use IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) in board_init_r()

Drop CONFIG_NEEDS_MANUAL_RELOC ifdefs in board_init_r() and use
IS_ENABLED() instead. Also, use the MANUAL_RELOC() macro to update the
initcall pointers.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2 years agoConvert CONFIG_MTD_CONCAT to Kconfig
Chris Packham [Tue, 3 May 2022 09:24:57 +0000 (21:24 +1200)]
Convert CONFIG_MTD_CONCAT to Kconfig

This converts the following to Kconfig:
  CONFIG_MTD_CONCAT

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agocommon/console.c: use CONFIG_VAL() with PRE_CON_BUF_* variables
Rasmus Villemoes [Tue, 3 May 2022 12:37:39 +0000 (14:37 +0200)]
common/console.c: use CONFIG_VAL() with PRE_CON_BUF_* variables

There is currently no support for PRE_CONSOLE_BUFFER in SPL, but if
and when that gets implemented, one would almost certainly want to use
a different address and/or size for the buffer (e.g., U-Boot proper
might specify an address in DRAM and a generous buffer, while SPL
would be much more constrained).

So a prerequisite for adding SPL_PRE_CONSOLE_BUFFER is to make the
code use SPL_-specific values. No functional change.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2 years agoboot: Kconfig: Enable FIT processing by default on TI secure devices
Andrew Davis [Wed, 4 May 2022 20:52:28 +0000 (15:52 -0500)]
boot: Kconfig: Enable FIT processing by default on TI secure devices

TI secure devices chain-of-trust depends on FIT image processing,
enable it by default on these devices. This also reduces the delta
between the secure and non-secure defconfig files.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agoboot: Kconfig: Disable non-FIT loading for TI secure devices
Andrew Davis [Wed, 4 May 2022 20:52:27 +0000 (15:52 -0500)]
boot: Kconfig: Disable non-FIT loading for TI secure devices

Non-FIT image loading support should be disabled for TI secure
devices as the image handlers for those image types do not follow
our secure boot checks.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agospl: Force disable non-FIT loading for TI secure devices
Andrew Davis [Wed, 4 May 2022 20:52:26 +0000 (15:52 -0500)]
spl: Force disable non-FIT loading for TI secure devices

Booting of non-FIT images bypass our chain-of-trust boot flow,
these options should not be allowed when high security is set.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agospl: Rename Kconfig SPL_LEGACY_IMAGE_SUPPORT to SPL_LEGACY_IMAGE_FORMAT
Andrew Davis [Wed, 4 May 2022 20:52:25 +0000 (15:52 -0500)]
spl: Rename Kconfig SPL_LEGACY_IMAGE_SUPPORT to SPL_LEGACY_IMAGE_FORMAT

This matches what this support is called in the non-SPL case. The postfix
_SUPPORT is redundant as enabling Kconfig options implies support.
With this we can use CONFIG_IS_ENABLED() as needed.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agoMerge tag 'u-boot-stm32-20220510' of https://source.denx.de/u-boot/custodians/u-boot-stm
Tom Rini [Tue, 10 May 2022 19:28:02 +0000 (15:28 -0400)]
Merge tag 'u-boot-stm32-20220510' of https://source.denx.de/u-boot/custodians/u-boot-stm

Add new STM32 MCU boards and Documentation
STM32 programmer improvements
video: support several LTDC HW versions and fix data enable polarity
board: fix stboard error message, consider USB cable connected when boot device is USB
configs: stm32mp1: set console variable for extlinux.conf
configs: stm32mp1: add support for baudrate higher than 115200 for ST-Link
ARM: stm32mp: Fix Silicon version handling and ft_system_setup()
phy: stm32-usbphyc: Add DT phy tuning support
arm: dts: stm32mp15: alignment with v5.18
ram: Conditionally enable ASR
mach-stm32mp: psci: retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend
configs: Use TFTP_TSIZE on DHSOM and STMicroelectronics boards
ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM
pinctrl: stm32: rework GPIO holes management

2 years agoMerge tag 'i2c-2022-07' of https://source.denx.de/u-boot/custodians/u-boot-i2c
Tom Rini [Tue, 10 May 2022 13:52:00 +0000 (09:52 -0400)]
Merge tag 'i2c-2022-07' of https://source.denx.de/u-boot/custodians/u-boot-i2c

i2c changes for 2022.07

- i2c: ihs: intel: Fix typo in comments
  Patch from Michal

- misc: atsha204a: Add support for atsha204 chip
  from Pali

2 years agomisc: Fix always compiling MISC even for SPL/TPL
Sean Anderson [Fri, 22 Apr 2022 20:11:37 +0000 (16:11 -0400)]
misc: Fix always compiling MISC even for SPL/TPL

We should only build support for misc if the appropriate SPL/TPL symbol
is defined. To ease the transition, make SPL/TPL_MISC default to MISC.
This is necessary because many drivers don't specify their dependencies
properly. These defaults can be removed once all drivers depend on the
appropriate config.

Fixes: aaba703fd0 ("spl: misc: Allow misc drivers in SPL and TPL")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
[trini: Add VPL_MISC symbol, handle like SPL/TPL_MISC]
Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agodoc: Add documentation for STM32 MCUs
Patrice Chotard [Wed, 27 Apr 2022 11:54:01 +0000 (13:54 +0200)]
doc: Add documentation for STM32 MCUs

Add documentation for STM32 MCUs (F4, F7 and H7 series).

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoconfigs: stm32746g-eval: Add stm32746g-eval_spl_defconfig
Patrice Chotard [Wed, 27 Apr 2022 11:54:00 +0000 (13:54 +0200)]
configs: stm32746g-eval: Add stm32746g-eval_spl_defconfig

Add stm32746g-eval_spl_defconfig for stm32746g evaluation board to
build SPL.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoconfigs: stm32746g-eval: Add stm32746g-eval_defconfig
Patrice Chotard [Wed, 27 Apr 2022 11:53:59 +0000 (13:53 +0200)]
configs: stm32746g-eval: Add stm32746g-eval_defconfig

Add stm32746g-eval_defconfig for stm32746g evaluation board to
build U-Boot proper.

Full board description can be found here :
https://www.st.com/en/evaluation-tools/stm32746g-eval.html

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoconfigs: stm32f746-disco: use CONFIG_DEFAULT_DEVICE_TREE as fdtfile
Patrice Chotard [Wed, 27 Apr 2022 11:53:58 +0000 (13:53 +0200)]
configs: stm32f746-disco: use CONFIG_DEFAULT_DEVICE_TREE as fdtfile

As stm32f46-disco, stm32f769-disco and stm32746g-eval are very similar
except their respective device tree file. These 3 boards uses the same
TARGET_STM32F746_DISCO flag (so same include/configs/stm32f746-disco.h
and same board file board/st/stm32f746-disco/stm32f746-disco.c)

To be able to compile these 3 boards, replace the hard-coded device-tree
name in include/configs/stm32f746-disco.h by CONFIG_DEFAULT_DEVICE_TREE
which is set in each board defconfig file with the correct value.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoboard: stm32f746-disco: Fix dram_init() in none SPL config
Patrice Chotard [Wed, 27 Apr 2022 11:53:57 +0000 (13:53 +0200)]
board: stm32f746-disco: Fix dram_init() in none SPL config

Replace CONFIG_SUPPORT_SPL by CONFIG_SPL_BUILD to allow
dram_init() execution when using none SPL defconfig
(stm32f746-disco_defconfig).

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoconfigs: stm32f746-disco: Migrate SPL flags to defconfig
Patrice Chotard [Wed, 27 Apr 2022 11:53:56 +0000 (13:53 +0200)]
configs: stm32f746-disco: Migrate SPL flags to defconfig

Migrate SPL flags to stm32f746-disco_spl_defconfig

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoconfigs: stm32f769-disco: Migrate SPL flags to defconfig
Patrice Chotard [Wed, 27 Apr 2022 11:53:55 +0000 (13:53 +0200)]
configs: stm32f769-disco: Migrate SPL flags to defconfig

Migrate SPL flags to stm32f769-disco_spl_defconfig

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoconfigs: stm32f769-disco: Add stm32f769-disco_defconfig
Patrice Chotard [Wed, 27 Apr 2022 11:53:54 +0000 (13:53 +0200)]
configs: stm32f769-disco: Add stm32f769-disco_defconfig

Add stm32f769-disco_defconfig for stm32f769 discovery board to
build U-Boot proper.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoconfigs: stm32f769-disco: Rename stm32f769-disco_defconfig to stm32f769-disco_spl_def...
Patrice Chotard [Wed, 27 Apr 2022 11:53:53 +0000 (13:53 +0200)]
configs: stm32f769-disco: Rename stm32f769-disco_defconfig to stm32f769-disco_spl_defconfig

The current stm32f769-disco_defconfig file supports SPL, rename it to
stm32f769-disco_spl_defconfig to reflect the supported configuration.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoconfigs: stm32f746-disco: Add stm32f746-disco_defconfig
Patrice Chotard [Wed, 27 Apr 2022 11:53:52 +0000 (13:53 +0200)]
configs: stm32f746-disco: Add stm32f746-disco_defconfig

Add stm32f746-disco_defconfig for stm32f746 discovery board to
build U-Boot proper.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoconfigs: stm32f746-disco: Rename stm32f746-disco_defconfig to stm32f746-disco_spl_def...
Patrice Chotard [Wed, 27 Apr 2022 11:53:51 +0000 (13:53 +0200)]
configs: stm32f746-disco: Rename stm32f746-disco_defconfig to stm32f746-disco_spl_defconfig

The current stm32f746-disco_defconfig file supports SPL, rename it to
stm32f746-disco_spl_defconfig to reflect the supported configuration.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoconfigs: stm32f746-disco: Concatenate spl and u-boot binaries
Patrice Chotard [Wed, 27 Apr 2022 11:53:50 +0000 (13:53 +0200)]
configs: stm32f746-disco: Concatenate spl and u-boot binaries

This allows to concatenate spl and u-boot binaries together.
Previously, both binaries has to be flashed separately at the correct
offset (spl at offset 0 and u-boot at offset 0x8000).
With this patch, only one binary is generated (u-boot-with-spl.bin)
and has to be copied in flash at offset 0 using openocd for example
or simply copied in exported mass storage.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoclk: stm32mp1: Add missing newline
Marek Vasut [Fri, 22 Apr 2022 10:40:39 +0000 (12:40 +0200)]
clk: stm32mp1: Add missing newline

Add missing newline to this debug message, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoboard: st: stm32mp1: Consider USB cable connected when boot device is USB
Patrice Chotard [Fri, 22 Apr 2022 07:39:18 +0000 (09:39 +0200)]
board: st: stm32mp1: Consider USB cable connected when boot device is USB

Always consider USB cable is connected when USB boot device is detected.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agophy: stm32-usbphyc: stm32-usbphyc: Add DT phy tuning support
Patrice Chotard [Fri, 22 Apr 2022 07:39:00 +0000 (09:39 +0200)]
phy: stm32-usbphyc: stm32-usbphyc: Add DT phy tuning support

Add support of phy-tuning properties for sm32-usbphyc's phy tuning
aligned with v5.15 kernel bindings.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agogpio: stm32_gpio: Rework GPIO hole management
Patrice Chotard [Fri, 22 Apr 2022 07:38:31 +0000 (09:38 +0200)]
gpio: stm32_gpio: Rework GPIO hole management

On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank
Example:
  If GPIO bank have 16 GPIO pins [0-15].
  In particular SoC's package case, some GPIO bank can have less GPIO pins:
    - [0-10] => 11 pins;
    - [2-7] => 6 pins.

Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management")
proposed a first implementation by not counting GPIO "inside" hole. GPIO
are not displaying correctly using gpio or pinmux command when GPIO holes
are located at the beginning of GPIO bank.

To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges
struct to indicate if a GPIO is mapped or not. GPIO uclass offers several
GPIO functions ("input", "output", "unused", "unknown" and "func"), use
"unknown" GPIO function to indicate that a GPIO is not mapped.

stm32_offset_to_index() is no more needed and removed.

This must be reflected using the "gpio" command to indicate to user
that a particular GPIO is not mapped (marked as "unknown") as shown below:

Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins
mapped):
GPIOI0          : unknown
GPIOI1          : unknown
GPIOI2          : analog
GPIOI3          : analog
GPIOI4          : alt function 0 push-pull pull-down
GPIOI5          : alt function 0 push-pull pull-down
GPIOI6          : alt function 0 push-pull pull-down
GPIOI7          : analog
GPIOI8          : unknown
GPIOI9          : unknown
GPIOI10         : unknown
GPIOI11         : unknown
GPIOI12         : unknown
GPIOI13         : unknown
GPIOI14         : unknown
GPIOI15         : unknown

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agopinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins
Patrice Chotard [Fri, 22 Apr 2022 07:38:30 +0000 (09:38 +0200)]
pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins

GPIOF_UNKNOWN becomes a valid pin muxing information to indicate
that a pin is not mapped.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agopinctrl: pinctrl_stm32: Update pinmux_mode definition
Patrice Chotard [Fri, 22 Apr 2022 07:38:29 +0000 (09:38 +0200)]
pinctrl: pinctrl_stm32: Update pinmux_mode definition

pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c
So reuse the same gpio_func_t enum value

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2 years agoARM: stm32: Use CONFIG_TFTP_TSIZE on STMicroelectronics boards
Patrick Delaunay [Thu, 5 May 2022 12:21:32 +0000 (14:21 +0200)]
ARM: stm32: Use CONFIG_TFTP_TSIZE on STMicroelectronics boards

Long TFTP transfers lead to a wall of # characters on UART, which in
the end may slow down the transfer itself. Use CONFIG_TFTP_TSIZE to
print progress in fewer # characters.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI
Marek Vasut [Wed, 4 May 2022 12:50:04 +0000 (14:50 +0200)]
ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI

The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3
in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant
which has extra Empirion DCDC converter in front of the 1V8 IO supply, or
outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter.

The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily
high input voltage to the Empirion DCDC converter, so move it into matching
DTSI to stop confusing users.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoARM: stm32: Use CONFIG_TFTP_TSIZE on DHSOM
Marek Vasut [Sun, 1 May 2022 16:43:29 +0000 (18:43 +0200)]
ARM: stm32: Use CONFIG_TFTP_TSIZE on DHSOM

Long TFTP transfers lead to a wall of # characters on UART, which in
the end may slow down the transfer itself. Use CONFIG_TFTP_TSIZE to
print progress in fewer # characters.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM
Marek Vasut [Sun, 1 May 2022 16:43:28 +0000 (18:43 +0200)]
ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM

The DHCOM does ship with KS8851 with 1.5 kiB packet buffer. The DHSOM
may be extended with other MAC options connected to FMC2 bus, like the
DM9000, wih similar limitations. Use default CONFIG_TFTP_BLOCKSIZE of
1468 Bytes instead of 1536 Bytes, which always avoids overflowing the
packet buffers of such limited MACs, which leads to e.g. TFTP timeouts.
This also avoids receiving a short packet fragment at the end of each
TFTP block, which led to reduced performance.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agostm32mp: psci: Retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend
Marek Vasut [Tue, 26 Apr 2022 14:38:05 +0000 (16:38 +0200)]
stm32mp: psci: Retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend

The SoC seems to lose the values of MCUDIVR, PLL3CR, PLL4CR, RCC_MSSCKSELR
during suspend/resume cycle, cache them and reinstate their values on resume.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoram: stm32mp1: Conditionally enable ASR
Marek Vasut [Tue, 26 Apr 2022 14:37:41 +0000 (16:37 +0200)]
ram: stm32mp1: Conditionally enable ASR

Enable DRAM ASR, auto self-refresh, conditionally, based on DT PWRCTL
register bits. While ASR does save considerable amount of power at
runtime automatically, it also causes LTDC underruns on large panels.
Let user select whether or not ASR is required or not, generally ASR
should be enabled on portable and battery operated devices.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoarm: dts: stm32mp15: alignment with v5.18
Patrick Delaunay [Tue, 26 Apr 2022 13:38:05 +0000 (15:38 +0200)]
arm: dts: stm32mp15: alignment with v5.18

Device tree alignment with Linux kernel v5.18-rc2:
- ARM: dts: stm32: Add support for the emtrion emSBC-Argon
  (only the pincontrol part)
- ARM: dts: stm32: Drop duplicate status okay from DHCOM gpioc node
- ARM: dts: stm32: add st,stm32-sdmmc2 compatible on stm32mp151
- ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15
- ARM: dts: stm32: use exti 19 as main interrupt to support RTC wakeup on
  stm32mp157
- ARM: dts: stm32: add DMA configuration to UART nodes on stm32mp151
- ARM: dts: stm32: keep uart4 behavior on *
- ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoARM: stm32mp: correctly handle Silicon revision
Patrick Delaunay [Fri, 15 Apr 2022 13:00:43 +0000 (15:00 +0200)]
ARM: stm32mp: correctly handle Silicon revision

Handle correctly the silicon revision = REV_ID[15:0] of Device Version
and the associated device marking, A to Z on STMicroelectronics STM32MP
SOCs.

This patch prepare the introduction of next STM32MP family,
with STM32MP13x Rev.Z for REV_ID = 1.1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoARM: stm32mp: skip ft_system_setup when the soc node is absent
Patrick Delaunay [Fri, 15 Apr 2022 12:43:23 +0000 (14:43 +0200)]
ARM: stm32mp: skip ft_system_setup when the soc node is absent

The function ft_system_setup shouldn't return an error when the
/soc node is absent in the provided device tree but just skip the
updates.

This patch solves an issue when the U-Boot pytest is executed on board.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoconfigs: stm32mp1: Add support for baudrates higher than 115200 for st-link
Patrick Delaunay [Fri, 15 Apr 2022 12:31:55 +0000 (14:31 +0200)]
configs: stm32mp1: Add support for baudrates higher than 115200 for st-link

On STMicroelectronics boards, the UART can reliably go up to
2000000 bauds when connected to the on-board ST-LINK-V2 for STM32MP15

Unfortunately U-Boot will fall back to 115200 unless higher rates are
declared via CONFIG_SYS_BAUDRATE_TABLE.

This patch add the support of higher baudrates on STMicroelectronics
boards with ST-LINK.

Cc: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoconfigs: stm32mp1: set the console variable for extlinux.conf
Patrick Delaunay [Fri, 15 Apr 2022 12:31:54 +0000 (14:31 +0200)]
configs: stm32mp1: set the console variable for extlinux.conf

Set the environment variable "console", used in extlinux.conf file when it
is generated by YOCTO distribution with:

UBOOT_EXTLINUX_CONSOLE ??= "console=${console},${baudrate}"

With these 2 variables, U-Boot give dynamically the used console and
baudrate in the Linux kernel bootargs.

For the STMicroelectronics boards, the used console is ttySTM0.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agoboard: st: common: fix the error messages in stboard command
Patrick Delaunay [Fri, 15 Apr 2022 09:46:50 +0000 (11:46 +0200)]
board: st: common: fix the error messages in stboard command

Add missing \n at the end of the error trace

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agovideo: stm32: stm32_ltdc: support several hardware versions
Yannick Fertre [Wed, 6 Apr 2022 08:41:35 +0000 (10:41 +0200)]
video: stm32: stm32_ltdc: support several hardware versions

Register mapping & pixel formats depend on version of ltdc
display controller.

Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agovideo: stm32: stm32_ltdc: fix data enable polarity
Yannick FERTRE [Wed, 6 Apr 2022 08:37:42 +0000 (10:37 +0200)]
video: stm32: stm32_ltdc: fix data enable polarity

Wrong DISPLAY_FLAGS used to set the data enable polarity.

Signed-off-by: Yannick FERTRE <yannick.fertre@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agostm32mp: stm32prog: handle flashlayout without STM32 image header
Patrick Delaunay [Mon, 28 Mar 2022 17:25:33 +0000 (19:25 +0200)]
stm32mp: stm32prog: handle flashlayout without STM32 image header

Accept flashlayout without header in alternate 0, to simplify
the support of stm32prog command with dfu-util.

By default the flashlayout file size is the size of the received binary,
provided with the offset in the DFU alternate.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agostm32mp: stm32prog: handle U-Boot script in flashlayout alternate
Patrick Delaunay [Mon, 28 Mar 2022 17:25:32 +0000 (19:25 +0200)]
stm32mp: stm32prog: handle U-Boot script in flashlayout alternate

Update the stm32prog command to allow the reception of U-Boot script in
the FlashLayout alternate during the first USB enumeration.

This patch is aligned with the last TF-A behavior: the Flashlayout
is now loaded by U-Boot; it is no more present at STM32_DDR_BASE when
the stm32prog is launched after a serial boot, on UART or on USB.

The received script must be a U-Boot legacy image, no more need to add
a stm32image header.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agostm32mp: stm32prog: handle interruption during the first enumeration
Patrick Delaunay [Mon, 28 Mar 2022 17:25:31 +0000 (19:25 +0200)]
stm32mp: stm32prog: handle interruption during the first enumeration

When an interruption is received during the first USB enumeration
used to received the FlashLayout, with handle ctrl-c, the second
enumeration is not needed and the result for stm32prog_usb_loop
is false (reset is not needed).

This patch avoids the need of a second ctrl to interrupt the command
stm32prog.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agostm32mp: stm32prog: add support of UUID for FIP partition
Patrick Delaunay [Mon, 28 Mar 2022 17:25:30 +0000 (19:25 +0200)]
stm32mp: stm32prog: add support of UUID for FIP partition

Add support of UUID for FIP parttion, required by Firmware update
support in TF-A:
- UUID TYPE for FIP partition: 19d5df83-11b0-457b-be2c-7559c13142a5
- "fip-a" partition UUID: 4fd84c93-54ef-463f-a7ef-ae25ff887087
- "fip-b" partition UUID: 09c54952-d5bf-45af-acee-335303766fb3

This check is done with a new partition type "FIP" associated
at the FIP UUID.

The A/B partition UUID is detected by the partition name:
"fip-a", "fip-b".

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agostm32mp: stm32prog: add support of STM32IMAGE version 2
Patrick Delaunay [Mon, 28 Mar 2022 17:25:29 +0000 (19:25 +0200)]
stm32mp: stm32prog: add support of STM32IMAGE version 2

Add support of new header for the STM32IMAGE version V2
in command stm32prog command for STM32MP13x family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agostm32mp: stm32prog: add TEE support in stm32prog command
Patrick Delaunay [Mon, 28 Mar 2022 17:25:28 +0000 (19:25 +0200)]
stm32mp: stm32prog: add TEE support in stm32prog command

When OP-TEE is used, the SMC for BSEC management are not
available and the PTA provisioning for OTP must be used.

U-Boot opens the session to this PTA and use it for OTP
access.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agostm32mp: stm32prog: add CONFIG_CMD_STM32PROG_OTP
Patrick Delaunay [Mon, 28 Mar 2022 17:25:27 +0000 (19:25 +0200)]
stm32mp: stm32prog: add CONFIG_CMD_STM32PROG_OTP

Add a configuration flag CONFIG_CMD_STM32PROG_OTP to enable the support of
OTP update in stm32prog command.

This new configuration allows to deactivate this feature for security reason
and it is a preliminary step for support of OPT update with the OP-TEE
provisioning TA.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agostm32mp: stm32prog: fix comment
Patrick Delaunay [Mon, 28 Mar 2022 17:25:26 +0000 (19:25 +0200)]
stm32mp: stm32prog: fix comment

Fix "partition" in comment.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2 years agomisc: atsha204a: Add support for atsha204 chip
Pali Rohár [Tue, 5 Apr 2022 12:49:08 +0000 (14:49 +0200)]
misc: atsha204a: Add support for atsha204 chip

atsha204 chip is predecessor of atsha204a chip. Current U-Boot driver
atsha204a-i2c.c can use both atsha204 and atsha204a chips because it does
not call specific functions to just one of these chips.

So just add compatible string for atsha204.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2 years agodoc: Add device-tree-bindings for atsha204 and atsha204a
Pali Rohár [Thu, 28 Apr 2022 18:58:28 +0000 (20:58 +0200)]
doc: Add device-tree-bindings for atsha204 and atsha204a

Document trivial bindings for atsha204 and atsha204a.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2 years agoi2c: ihs: intel: Fix typo in comments (actual)
Michal Simek [Tue, 19 Apr 2022 13:01:31 +0000 (15:01 +0200)]
i2c: ihs: intel: Fix typo in comments (actual)

s/actucal/actual/g

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2 years agoMerge branch '2022-05-09-TI-platform-updates'
Tom Rini [Mon, 9 May 2022 17:40:35 +0000 (13:40 -0400)]
Merge branch '2022-05-09-TI-platform-updates'

- Assorted minor TI platform updates

2 years agoARM: dts: k3-am642-sk-u-boot: add PMIC node
Neil Armstrong [Wed, 27 Apr 2022 11:28:12 +0000 (13:28 +0200)]
ARM: dts: k3-am642-sk-u-boot: add PMIC node

The E4 revision of the AM64 SKEVM embeds a TPS65219 PMIC,
this adds the PMIC node with the required regulators voltages.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2 years agoconfig: enable TPS65219 for am64x_evm_a53 boards
Neil Armstrong [Wed, 27 Apr 2022 11:28:11 +0000 (13:28 +0200)]
config: enable TPS65219 for am64x_evm_a53 boards

The E4 revision of the AM64 SKEVM embeds a TPS65219 PMIC,
this enables the necessary options to load and control the
PMIC regulators.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2 years agoregulator: add driver for the TPS65219 BUCK & LDO regulators
Neil Armstrong [Wed, 27 Apr 2022 11:28:10 +0000 (13:28 +0200)]
regulator: add driver for the TPS65219 BUCK & LDO regulators

The TPS65219 I2S PMIC features 3 Buck converters and 4 linear regulators,
2 GPOs, 1 GPIO, and 3 multi-function-pin.

This adds the driver for the Buck converters & linear regulators.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2 years agopower: add driver for the TPS65219 PMIC
Neil Armstrong [Wed, 27 Apr 2022 11:28:09 +0000 (13:28 +0200)]
power: add driver for the TPS65219 PMIC

The TPS65219 I2S PMIC features 3 Buck converters and 4 linear regulators,
2 GPOs, 1 GPIO, and 3 multi-function-pin.

This adds the PMIC driver, loading the regulator sub-nodes.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2 years agoNokia RX-51: Convert to CONFIG_DM_SERIAL
Pali Rohár [Wed, 13 Apr 2022 19:34:14 +0000 (21:34 +0200)]
Nokia RX-51: Convert to CONFIG_DM_SERIAL

For CONFIG_DM_SERIAL it is required to increase CONFIG_SYS_MALLOC_F_LEN as
default value is not enough for memory hungry CONFIG_DM_SERIAL code.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Merlijn Wajer <merlijn@wizzup.org>
2 years agoNokia RX-51: Enable CONFIG_SUPPORT_RAW_INITRD
Pali Rohár [Mon, 9 May 2022 13:00:47 +0000 (15:00 +0200)]
Nokia RX-51: Enable CONFIG_SUPPORT_RAW_INITRD

This enable booting of Debian systems which use raw initrd image (instead
of uInitrd created by mkimage). This change increase size of u-boot.bin
binary by just 64 bytes.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agoam335x, guardian: Drop non DM_I2C code
Gireesh Hiremath [Wed, 4 May 2022 11:02:58 +0000 (11:02 +0000)]
am335x, guardian: Drop non DM_I2C code

On this platform DM_I2C and SPL_DM_I2C enabled.
Remove legacy code.

Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agoconfigs: am335x_guardian: Enable DM_I2C
Gireesh Hiremath [Wed, 4 May 2022 11:02:57 +0000 (11:02 +0000)]
configs: am335x_guardian: Enable DM_I2C

Move from I2C legacy to the DM I2C version

Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agoARM: dts: am335x: guardian: switch to AM33XX_PADCONF
Gireesh Hiremath [Wed, 4 May 2022 11:02:56 +0000 (11:02 +0000)]
ARM: dts: am335x: guardian: switch to AM33XX_PADCONF

switch the pin definitions from AM33XX_IOPAD to AM33XX_PADCONF macro

Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agoPrepare v2022.07-rc2
Tom Rini [Mon, 9 May 2022 16:49:31 +0000 (12:49 -0400)]
Prepare v2022.07-rc2

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoMerge tag 'efi-2022-07-rc3-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Tom Rini [Sun, 8 May 2022 15:31:48 +0000 (11:31 -0400)]
Merge tag 'efi-2022-07-rc3-2' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2022-07-rc3-2

UEFI:
* Fix build errors due to
  - using sed with non-standard extension for regular expression
  - target architecture not recognized for CROSS_COMPILE=armv7a-*
  - CONFIG_EVENT not selected
* add sha384/512 on certificate revocation

Others:
* factor out the user input handling in bootmenu command

2 years agoMerge branch '2022-05-06-assorted-updates'
Tom Rini [Sun, 8 May 2022 15:29:50 +0000 (11:29 -0400)]
Merge branch '2022-05-06-assorted-updates'

- Drop "linux,phandle" setting code, it's very long obsolete.
- Add ability to fix broken GPT via backup GPT.

2 years agotest/py: Add more test cases for rejecting an EFI image
Ilias Apalodimas [Fri, 6 May 2022 12:36:01 +0000 (15:36 +0300)]
test/py: Add more test cases for rejecting an EFI image

The previous patch adds support for rejecting images when the sha384/512
of an x.509 certificate is present in dbx.  Update the sandbox selftests

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2 years agoefi_loader: add sha384/512 on certificate revocation
Ilias Apalodimas [Fri, 6 May 2022 12:36:00 +0000 (15:36 +0300)]
efi_loader: add sha384/512 on certificate revocation

Currently we don't support sha384/512 for the X.509 certificate
in dbx.  Moreover if we come across such a hash we skip the check
and approve the image,  although the image might needs to be rejected.

Rework the code a bit and fix it by adding an array of structs with the
supported GUIDs, len and literal used in the U-Boot crypto APIs instead
of hardcoding the GUID types.

It's worth noting here that efi_hash_regions() can now be reused from
efi_signature_lookup_digest() and add sha348/512 support there as well

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2 years agobootmenu: factor out the user input handling
Masahisa Kojima [Thu, 28 Apr 2022 08:09:45 +0000 (17:09 +0900)]
bootmenu: factor out the user input handling

This commit moves the user input handling from cmd/bootmenu.c
to common/menu.c to reuse it from other modules.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2 years agoefi_loader: Select EVENT as well
Jan Kiszka [Wed, 27 Apr 2022 05:47:15 +0000 (07:47 +0200)]
efi_loader: Select EVENT as well

Fixes

WARNING: unmet direct dependencies detected for EVENT_DYNAMIC
  Depends on [n]: EVENT [=n]
  Selected by [y]:
  - EFI_LOADER [=y] && OF_LIBFDT [=y] && ...

and the succeeding build breakage.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2 years agotools: mkimage: set OPENSSL_API_COMPAT
Heinrich Schuchardt [Fri, 6 May 2022 11:28:52 +0000 (13:28 +0200)]
tools: mkimage: set OPENSSL_API_COMPAT

Building with OpenSSL 3.0 produces warnings like:

../tools/sunxi_toc0.c:846:17: warning: ‘RSA_get0_d’ is deprecated:
Since OpenSSL 3.0 [-Wdeprecated-declarations]
  846 |                 if (root_key && RSA_get0_d(root_key)) {
      |                 ^~

As OpenSSL 3.0 is not available in elder Linux distributions
just silence the warning.

Add missing #include <openssl/bn.h>.

Fixes: e9e87ec47c75 ("tools: mkimage: Add Allwinner TOC0 support")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
2 years agomkimage: Document misc options
Sean Anderson [Fri, 8 Apr 2022 20:08:39 +0000 (16:08 -0400)]
mkimage: Document misc options

Over the years, several options have not made it into the help message.
Document them. Do the same for the man page.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2 years agoMakefile: support CROSS_COMPILE=armv7a-*
Heinrich Schuchardt [Sat, 7 May 2022 20:58:39 +0000 (22:58 +0200)]
Makefile: support CROSS_COMPILE=armv7a-*

Gentoo uses armv7a-hardfloat-linux-gnueabi- as cross compiler prefix.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2 years agoMakefile: Avoid non-portable GNU sed extension
Mark Kettenis [Thu, 5 May 2022 14:42:23 +0000 (16:42 +0200)]
Makefile: Avoid non-portable GNU sed extension

Use [:space:] instead of \s and \S in regular expression that
determines the sandbox target architecture.  Fixes the build
failure on OpenBSD introduced with commit 4e65ca00f3a3
("efi_loader: bootmgr: add booting from removable media").

Fixes: f7691a6d736b ("sandbox: allow cross-compiling sandbox")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2 years agofdt: don't set linux,phandle
John Keeping [Wed, 20 Apr 2022 10:31:11 +0000 (11:31 +0100)]
fdt: don't set linux,phandle

This has been deprecated for over 10 years and everything now uses the
plain "phandle" property in preference.  There's no need to set
linux,phandle when creating phandles for nodes that do not have one.

dtc changed the default to creating just phandle in version 1.4.5
released in September 2017 with the justification that the new style had
already been supported for 7 years by that point (see dtc commit 0016f8c
("dtc: change default phandles to ePAPR style instead of both")).

Signed-off-by: John Keeping <john@metanate.com>
2 years agotest: py: tests: test_gpt.py: add a simple test for the command gpt repair
Philippe Reynes [Fri, 22 Apr 2022 15:46:50 +0000 (17:46 +0200)]
test: py: tests: test_gpt.py: add a simple test for the command gpt repair

Adds a simple test for the command gpt repair.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2 years agocmd: gpt: add subcommand repair
Philippe Reynes [Fri, 22 Apr 2022 15:46:49 +0000 (17:46 +0200)]
cmd: gpt: add subcommand repair

Adds a sub-command repair to the command gpt
that allow to repair a corrupted gpt table. If
the both gpt table (primary and backup) are
valid, then the command does nothing.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>