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3 years agocmd: mtd: expand <name> argument definition in command help
Marek Behún [Wed, 26 May 2021 12:08:26 +0000 (14:08 +0200)]
cmd: mtd: expand <name> argument definition in command help

The <name> argument can now also be MTD's DM device name or OF path.
Mention this is command help.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agomtd: compare also with OF path and device name in get_mtd_device_nm()
Marek Behún [Wed, 26 May 2021 12:08:25 +0000 (14:08 +0200)]
mtd: compare also with OF path and device name in get_mtd_device_nm()

The get_mtd_device_nm() function (code imported from Linux) simply
iterates all registered MTD devices and compares the given name with
all MTDs' names.

With SPI_FLASH_MTD enabled U-Boot registers a SPI-NOR as a MTD device
with name identical to the SPI flash chip name (from SPI ID table). Thus
for a board with multiple same SPI-NORs it registers multiple MTDs, but
all with the same name (such as "s25fl164k"). We do not want to change
this behaviour, since such a change could break existing boot scripts,
which can rely on a hardcoded name.

In order to allow somehow to uniqely select a MTD device, change
get_mtd_device_nm() function as such:
- if first character of name is '/', try interpreting it as OF path
- otherwise compare the name with MTDs name and MTDs device name.

In the following example a board has two "s25fl164k" SPI-NORs. They both
have name "s25fl164k", thus cannot be uniquely selected via this name.
With this change, the user can select the second SPI-NOR either with
"spi-nor@1" or "/soc/spi@10600/spi-nor@1".

Example:
  => mtd list
  List of MTD devices:
  * s25fl164k
    - device: spi-nor@0
    - parent: spi@10600
    - driver: jedec_spi_nor
    - path: /soc/spi@10600/spi-nor@0
    - type: NOR flash
    - block size: 0x1000 bytes
    - min I/O: 0x1 bytes
    - 0x000000000000-0x000000800000 : "s25fl164k"
  * s25fl164k
    - device: spi-nor@1
    - parent: spi@10600
    - driver: jedec_spi_nor
    - path: /soc/spi@10600/spi-nor@1
    - type: NOR flash
    - block size: 0x1000 bytes
    - min I/O: 0x1 bytes
    - 0x000000000000-0x000000800000 : "s25fl164k"

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agocmd: mtd: print device OF path in listing
Marek Behún [Wed, 26 May 2021 12:08:24 +0000 (14:08 +0200)]
cmd: mtd: print device OF path in listing

Print MTD's device OF path in the output of `mtd list` command.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agomtd: probe SPI NOR devices in mtd_probe_devices()
Marek Behún [Wed, 26 May 2021 12:08:23 +0000 (14:08 +0200)]
mtd: probe SPI NOR devices in mtd_probe_devices()

In order for `mtd list` U-Boot command to list SPI NOR devices without
the need to run `sf probe` before, we have to probe SPI NOR devices in
mtd_probe_devices().

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agomtd: remove mtd_probe() function
Marek Behún [Wed, 26 May 2021 12:08:22 +0000 (14:08 +0200)]
mtd: remove mtd_probe() function

The device_probe() function does the same thing as mtd_probe() and
mtd_probe() is only used in mtd_probe_uclass_mtd_devs(), where the
probing can be made simpler by using uclass_foreach_dev_probe macro.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agomtd: spi-nor: fill-in mtd->dev member
Marek Behún [Wed, 26 May 2021 12:08:21 +0000 (14:08 +0200)]
mtd: spi-nor: fill-in mtd->dev member

Fill in mtd->dev member with nor->dev.

This can be used by MTD OF partition parser.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agomtd: spi-nor: allow registering multiple MTDs when DM is enabled
Marek Behún [Wed, 26 May 2021 12:08:20 +0000 (14:08 +0200)]
mtd: spi-nor: allow registering multiple MTDs when DM is enabled

Currently when the SPI_FLASH_MTD config option is enabled, only one SPI
can be registered as MTD at any time - it is the last one probed (since
with old non-DM model only one SPI NOR could be probed at any time).

When DM is enabled, allow for registering multiple SPI NORs as MTDs by
utilizing the nor->mtd structure, which is filled in by spi_nor_scan
anyway, instead of filling a separate struct mtd_info.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agomtd: add support for parsing partitions defined in OF
Marek Behún [Wed, 26 May 2021 12:08:19 +0000 (14:08 +0200)]
mtd: add support for parsing partitions defined in OF

Add support for parsing partitions defined in device-trees via the
`partitions` node with `fixed-partitions` compatible.

The `mtdparts`/`mtdids` mechanism takes precedence. If some partitions
are defined for a MTD device via this mechanism, the code won't register
partitions for that MTD device from OF, even if they are defined.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agodm: core: add ofnode_get_path()
Marek Behún [Wed, 26 May 2021 12:08:18 +0000 (14:08 +0200)]
dm: core: add ofnode_get_path()

Add function for retrieving full node path of a given ofnode.
This uses np->full_name if OF is live, otherwise a call to
fdt_get_path() is made.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agodm: core: add non-translating version of ofnode_get_addr_size_index()
Marek Behún [Wed, 26 May 2021 12:08:17 +0000 (14:08 +0200)]
dm: core: add non-translating version of ofnode_get_addr_size_index()

Add functions ofnode_get_addr_size_index_notrans(), which is a
non-translating version of ofnode_get_addr_size_index().

Some addresses are not meant to be translated, for example those of MTD
fixed-partitions.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spinand: macronix: Add support for serial NAND flash
Jaime Liao [Mon, 7 Jun 2021 08:19:15 +0000 (16:19 +0800)]
mtd: spinand: macronix: Add support for serial NAND flash

Macronix NAND Flash devices are available in different configurations
and densities.

MX"35" means SPI NAND
MX35"UF" , UF meands 1.8V
MX35LF"2G" , 2G means 2Gbits
MX35LF2G"E4" , E4 means internal ECC and Quad I/O(x4)

MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial
NAND flash device with 8-bit on-die ECC
https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/MX35UF4GE4AD,%201.8V,%204Gb,%20v0.00.pdf

MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial
NAND flash device with 8-bit on-die ECC
https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/MX35UF2GE4AC,%201.8V,%202Gb,%20v1.0.pdf

Validated via normal(default) and QUAD mode by read, erase, read back,
on Xilinx Zynq PicoZed FPGA board which included Macronix
SPI Host(drivers/spi/spi-mxic.c).

Signed-off-by: Jaime Liao <jaimeliao@mxic.com.tw>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-ids: Add Macronix MX66UW2G345G
zhengxun [Tue, 23 Mar 2021 13:16:47 +0000 (13:16 +0000)]
mtd: spi-nor-ids: Add Macronix MX66UW2G345G

The MX66UW2G345G is Macronix Flash with SINGLE and OCTAL I/O. Hence,
add SPI_NOR_OCTAL_READ flag for this flash.

Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: change order of id flags]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: zhengxun <zhengxunli.mxic@gmail.com>
3 years agoMerge tag 'u-boot-rockchip-20210618' of https://source.denx.de/u-boot/custodians...
Tom Rini [Sat, 19 Jun 2021 12:20:12 +0000 (08:20 -0400)]
Merge tag 'u-boot-rockchip-20210618' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next

- New SoC platform support: rk3568;
- rockchip pcie Code compile issue fix;
- Board fix for rk3399 Khadas Edge;
- Add Rockchip NFC driver;

3 years agoMerge tag 'u-boot-stm32-20210618' of https://source.denx.de/u-boot/custodians/u-boot...
Tom Rini [Fri, 18 Jun 2021 17:18:29 +0000 (13:18 -0400)]
Merge tag 'u-boot-stm32-20210618' of https://source.denx.de/u-boot/custodians/u-boot-stm into next

 - stm32mp157c-odyssey-som DT fixes
 - stm32_qspi: Fix short data write operation
 - dfu: set max_buf_size to erasesize also for NOR devices
 - Fixes ethernet clock property name for STM32MP1 board
 - STM32CubeProgrammer: various fixes
 - clk: cosmetic update for clk-uclass

3 years agoclk: cosmetic change in uclass
Patrick Delaunay [Tue, 27 Apr 2021 08:57:54 +0000 (10:57 +0200)]
clk: cosmetic change in uclass

Remove the tab in clk_get_bulk to respect the coding rules.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: stm32prog: handle dfu error
Patrick Delaunay [Tue, 18 May 2021 13:12:13 +0000 (15:12 +0200)]
stm32mp: stm32prog: handle dfu error

Handle DFU stack error in STM32CubeProgrammer protocol.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agodfu: add error callback
Patrick Delaunay [Tue, 18 May 2021 13:12:12 +0000 (15:12 +0200)]
dfu: add error callback

Add error callback in dfu stack to manage some board specific
behavior on DFU targets.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: stm32prog: change one message level to debug
Patrick Delaunay [Tue, 18 May 2021 13:12:11 +0000 (15:12 +0200)]
stm32mp: stm32prog: change one message level to debug

Move the message "Invalid or missing layout file."
to debug level as it is a normal behavior and not an error
and add the missing '\n'.

This patch avoids the strange trace :
  Boot over usb0!
  Invalid or missing layout file.DFU alt info setting: done

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: stm32prog: use get_cpu_dev for GetID command
Patrick Delaunay [Tue, 18 May 2021 13:12:10 +0000 (15:12 +0200)]
stm32mp: stm32prog: use get_cpu_dev for GetID command

Use get_cpu_dev() in uart getID command and remove the defines
DEVICE_ID_BYTE1 and 2 defines.

This patch prepare the support for new SOC family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: stm32prog: correctly handle DM_PMIC
Patrick Delaunay [Tue, 18 May 2021 13:12:09 +0000 (15:12 +0200)]
stm32mp: stm32prog: correctly handle DM_PMIC

Correctly handle number of alternate when DM_PMIC is not activated.
This patch remove the last UNKNOWN partition in this case.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
3 years agostm32mp: stm32prog: handle the next phase after USB re-enumeration
Patrick Delaunay [Tue, 18 May 2021 13:12:08 +0000 (15:12 +0200)]
stm32mp: stm32prog: handle the next phase after USB re-enumeration

Handle the second USB enumeration only when the flashlayout is received
and when phase is PHASE_FLASHLAYOUT. This patch removes the call of
stm32prog_next_phase as it is already done in stm32prog_dfu_init().

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: stm32prog: solve compilation with CONFIG_FIT_SIGNATURE
Patrick Delaunay [Tue, 18 May 2021 13:12:07 +0000 (15:12 +0200)]
stm32mp: stm32prog: solve compilation with CONFIG_FIT_SIGNATURE

When CONFIG_FIT_SIGNATURE is activated, CONFIG_LEGACY_IMAGE_FORMAT
is deactivated and the define IMAGE_FORMAT_LEGACY don't exist with
include/image.h:
  #if defined(CONFIG_LEGACY_IMAGE_FORMAT)
  #define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */
  #endif

This patch adds the needed check on compilation flag
CONFIG_LEGACY_IMAGE_FORMAT to avoid the compilation error
for command stm32prog:

cmd_stm32prog.c:81:8: error: ‘IMAGE_FORMAT_LEGACY’ undeclared
(first use in this function); did you mean ‘IMAGE_FORMAT_FIT’?
   81 |    if (IMAGE_FORMAT_LEGACY ==
      |        ^~~~~~~~~~~~~~~~~~~
      |        IMAGE_FORMAT_FIT

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: stm32prog: add support of initrd in flashlayout
Patrick Delaunay [Tue, 18 May 2021 13:12:06 +0000 (15:12 +0200)]
stm32mp: stm32prog: add support of initrd in flashlayout

Add the support in command stm32prog of kernel load and start
with initrd file, identify by the partition Type "Binary" in
the flashlayout.tsv, for example:

- 0x01 fsbl Binary none 0x0 tfa.stm32
- 0x03 fip Binary none 0x0 fip.bin
P 0x10 kernel System ram0 0xC2000000 uImage.bin
P 0x11 dtb FileSystem ram0 0xC4000000 board.dtb
P 0x12 initrd Binary ram0 0xC4400000 <initrd>

The <initrd> file can be a legacy image "uInitrd", generated
with mkimage, or a RAW initrd image "initrd.gz".

After a DFU detach the bootm command with be executed
with the associated address, for example:

$> bootm 0xC2000000 0xC4400000:<size> 0xC4000000

When the "Binary" partition type is absent, the 'bootm'
command starts the kernel without ramdisk, for example:

$> bootm 0xC2000000 - 0xC4000000

With this paths, it is no more mandatory to generate FIT
including the kernel, DT and initrd:

- 0x01 fsbl Binary none 0x0 tfa.stm32
- 0x03 fip Binary none 0x0 fip.bin
P 0x10 fit System ram0 0xC2000000 fit.bin

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: stm32prog: add timeout in stm32prog_serial_get_buffer
Patrick Delaunay [Tue, 18 May 2021 13:12:05 +0000 (15:12 +0200)]
stm32mp: stm32prog: add timeout in stm32prog_serial_get_buffer

Handle timeout in stm32prog_serial_get_buffer to sent NACK
to STM32CubeProgrammer when the buffer is not fully received.

This patch avoids to reach the STM32CubeProgrammer timeout and
the associated unrecoverable error.

  Timeout error occurred while waiting for acknowledgment.

  Error: Write Operation fails at packet number 4165 at address 0x1044FF

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: stm32prog: remove all the header check for UART download
Patrick Delaunay [Tue, 18 May 2021 13:12:04 +0000 (15:12 +0200)]
stm32mp: stm32prog: remove all the header check for UART download

This patch removes the header check for UART download;
the check of checksum is not mandatory with even parity and chuck
checksum for each 256 received bytes and it is only done for
STM32 image (FSBL = TF-A BL2), not for FIT image.

This patch solve issue of duplicated 0x100 byte written with FIP header.

Fixes: 4fb7b3e10891 ("stm32mp: stm32prog: add FIP header support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agoboard: stm32mp1: correct the property name for eth
Patrick Delaunay [Fri, 4 Jun 2021 16:25:55 +0000 (18:25 +0200)]
board: stm32mp1: correct the property name for eth

Use the correct name for STMicroelectronics phys config properties,
replace '_' by '-':
  "st,eth_clk_sel" => "st,eth-clk-sel"
  "st,eth-ref-clk-sel" => st,eth-clk-sel"

These property name are aligned with the upstreamed Linux kernel binding:
 linux/Documentation/devicetree/bindings/net/stm32-dwmac.yaml

See Linux kernel commit "dt-bindings: net: stmmac: add phys config
properties" merged in v5.1-rc1.

This patch allow to reuse the kernel device tree directly in U-Boot.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agodfu: dfu_mtd: set max_buf_size to erasesize also for NOR devices
Patrick Delaunay [Thu, 4 Mar 2021 16:47:56 +0000 (17:47 +0100)]
dfu: dfu_mtd: set max_buf_size to erasesize also for NOR devices

For NOR devices the logical DFU buffer size is the sector_size,
as it is done in dfu_sf.c or in spi/sf_mtd.c
(sf_mtd_info.erasesize = flash->sector_size)

For NAND the DFU size was already limited to erasesize as
has_pages = true.

So the mtd dfu backend can use this erasesize for all the MTD devices,
NOR and NAND with dfu->max_buf_size = mtd->erasesize

This difference was initially copied from MTD command, where
data is fully available in RAM without size limitation.

This patch avoids to have many sector write in dfu_mtd.c at the end
of the DFU transfer and avoids issues with USB timeout or WATCHDOG.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agospi: stm32_qspi: Fix short data write operation
Daniil Stas [Sun, 23 May 2021 22:24:49 +0000 (22:24 +0000)]
spi: stm32_qspi: Fix short data write operation

TCF flag only means that all data was sent to FIFO. To check if the
data was sent out of FIFO we should also wait for the BUSY flag to be
cleared. Otherwise there is a race condition which can lead to
inability to write short (one byte long) data.

Signed-off-by: Daniil Stas <daniil.stas@posteo.net>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agomtd: nand: NFC drivers for RK3308, RK2928 and others
Yifeng Zhao [Mon, 7 Jun 2021 08:40:29 +0000 (16:40 +0800)]
mtd: nand: NFC drivers for RK3308, RK2928 and others

This driver supports Rockchip NFC (NAND Flash Controller) found on
RK3308, RK2928, RKPX30, RV1108 and other SOCs. The driver has been
tested using 8-bit NAND interface on the ARM based RK3308 platform.

Support Rockchip SoCs and NFC versions:
- PX30 and RK3326(NFCv900).
ECC: 16/40/60/70 bits/1KB.
CLOCK: ahb and nfc.
- RK3308 and RV1108(NFCv800).
ECC: 16 bits/1KB.
CLOCK: ahb and nfc.
- RK3036 and RK3128(NFCv622).
ECC: 16/24/40/60 bits/1KB.
CLOCK: ahb and nfc.
- RK3066, RK3188 and RK2928(NFCv600).
ECC: 16/24/40/60 bits/1KB.
CLOCK: ahb.

Supported features:
- Read full page data by DMA.
- Support HW ECC(one step is 1KB).
- Support 2 - 32K page size.
- Support 8 CS(depend on SoCs)

Limitations:
- No support for the ecc step size is 512.
- Untested on some SoCs.
- No support for subpages.
- No support for the builtin randomizer.
- The original bad block mask is not supported. It is recommended to
  use  the BBT(bad block table).

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
3 years agoconfigs: rockchip: rk3399: Khadas Edge add USB OHCI
Artem Lapkin [Mon, 7 Jun 2021 03:45:05 +0000 (11:45 +0800)]
configs: rockchip: rk3399: Khadas Edge add USB OHCI

Problem: USB2.0 port can recognize any USB1.1 devices (like usb keyboard)
Add missed USB OHCI configuration

USB device tree:
  1  Hub (480 Mb/s, 0mA)
     u-boot EHCI Host Controller

  1  Hub (12 Mb/s, 0mA)
  |   U-Boot Root Hub
  |
  +-2  Human Interface (1.5 Mb/s, 100mA)
        Dell KB216 Wired Keyboard

Signed-off-by: Artem Lapkin <art@khadas.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
3 years agoARM64: rockchip: evb_rk3399: add usb ohci definations
Artem Lapkin [Mon, 7 Jun 2021 03:45:04 +0000 (11:45 +0800)]
ARM64: rockchip: evb_rk3399: add usb ohci definations

Problem: USB2.0 port can recognize any USB1.1 devices (like usb keyboard)
Add missed USB OHCI configuration

USB device tree:
  1  Hub (480 Mb/s, 0mA)
     u-boot EHCI Host Controller

  1  Hub (12 Mb/s, 0mA)
  |   U-Boot Root Hub
  |
  +-2  Human Interface (1.5 Mb/s, 100mA)
        Dell KB216 Wired Keyboard

Signed-off-by: Artem Lapkin <art@khadas.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
3 years agopci: pcie_dw_rockchip: Replace msleep occurences by udelay
Anand Moon [Sat, 5 Jun 2021 14:38:43 +0000 (14:38 +0000)]
pci: pcie_dw_rockchip: Replace msleep occurences by udelay

Replace msleep occurences by udelay.

drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit
     declaration of function 'msleep' [-Wimplicit-function-declaration]

Cc: Patrick Wildt <patrick@blueri.se>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
3 years agopci: pcie_dw_rockchip: Drop the unused variable warning
Anand Moon [Sat, 5 Jun 2021 14:38:42 +0000 (14:38 +0000)]
pci: pcie_dw_rockchip: Drop the unused variable warning

Drop the unused variable warning below.

drivers/pci/pcie_dw_rockchip.c:161:6: warning: unused variable
'val' [-Wunused-variable]
  161 |  u32 val;
       |      ^~~
Cc: Patrick Wildt <patrick@blueri.se>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
3 years agopci: pcie_dw_rockchip: Fixed the below compilation error
Anand Moon [Sat, 5 Jun 2021 14:38:41 +0000 (14:38 +0000)]
pci: pcie_dw_rockchip: Fixed the below compilation error

Use the generic error number instead of specific error number.
Changes fix the below error.

drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read':
drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED'
                        undeclared (first use in this function)
   70 |   return PCIBIOS_UNSUPPORTED;
      |          ^~~~~~~~~~~~~~~~~~~
drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_write':
drivers/pci/pcie_dw_rockchip.c:90:10: error: 'PCIBIOS_UNSUPPORTED'
                        undeclared (first use in this function)
   90 |   return PCIBIOS_UNSUPPORTED;
      |          ^~~~~~~~~~~~~~~~~~~

Cc: Patrick Wildt <patrick@blueri.se>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
3 years agoboard: rockchip: Add rk3568 evb support
Joseph Chen [Wed, 2 Jun 2021 08:13:46 +0000 (16:13 +0800)]
board: rockchip: Add rk3568 evb support

Add support for rk3568 evaluation board.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
3 years agorockchip: Add rk3568 architecture core
Joseph Chen [Wed, 2 Jun 2021 07:58:25 +0000 (15:58 +0800)]
rockchip: Add rk3568 architecture core

RK3568 is a high-performance and low power quad-core application
processor designed for personal mobile internet device and AIoT
equipments.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
3 years agorockchip: rk3568: Add sdram driver
Joseph Chen [Wed, 2 Jun 2021 07:58:24 +0000 (15:58 +0800)]
rockchip: rk3568: Add sdram driver

Add the driver for rk3568 u-boot to get sdram capacity.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
3 years agoarm: dts: rockchip: Add dts for rk3568 evb
Joseph Chen [Wed, 2 Jun 2021 07:58:23 +0000 (15:58 +0800)]
arm: dts: rockchip: Add dts for rk3568 evb

Add dts for rk3568 evb, sync from the linux kernel
upstream list [0].

[0] https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
3 years agoarm: dts: Sync rockchip-pinconf.dtsi from kernel
Joseph Chen [Wed, 2 Jun 2021 07:58:22 +0000 (15:58 +0800)]
arm: dts: Sync rockchip-pinconf.dtsi from kernel

Sync from linux kernel:
https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
3 years agork3399_common: setup fdtoverlay_addr_r value
Artem Lapkin [Wed, 26 May 2021 09:34:17 +0000 (17:34 +0800)]
rk3399_common: setup fdtoverlay_addr_r value

fdtoverlay (pxe_utils) require define fdtoverlay_addr_r env variable
for example sunxi-common.h meson64.h already have it.

Signed-off-by: Artem Lapkin <art@khadas.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
3 years agorockchip: rk3568: add clock driver
Elaine Zhang [Wed, 2 Jun 2021 03:39:24 +0000 (11:39 +0800)]
rockchip: rk3568: add clock driver

Add rk3568 clock driver and cru structure definition.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
3 years agorockchip: rk3568: add device tree file
Elaine Zhang [Wed, 26 May 2021 09:01:16 +0000 (17:01 +0800)]
rockchip: rk3568: add device tree file

Add dts binding header for rk3568, files origin from kernel.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
3 years agoarm: dts: stm32mp157c-odyssey-som: enable SDMMC2 in SPL
Grzegorz Szymaszek [Wed, 2 Jun 2021 17:09:18 +0000 (19:09 +0200)]
arm: dts: stm32mp157c-odyssey-som: enable SDMMC2 in SPL

Enable the SDMMC2 device tree node, as well as the pins it uses, in
U-Boot SPL.

Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agoarm: dts: stm32mp157c-odyssey-som: enable the SDMMC2 eMMC HS DDR mode
Grzegorz Szymaszek [Wed, 2 Jun 2021 17:09:13 +0000 (19:09 +0200)]
arm: dts: stm32mp157c-odyssey-som: enable the SDMMC2 eMMC HS DDR mode

Enable the SDMMC2 eMMC high-speed DDR mode as it is done in the
corresponding Linux kernel device tree.

Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agoarm: dts: stm32mp157c-odyssey-som: set the SDMMC2 VQMMC supply
Grzegorz Szymaszek [Wed, 2 Jun 2021 17:09:08 +0000 (19:09 +0200)]
arm: dts: stm32mp157c-odyssey-som: set the SDMMC2 VQMMC supply

Set the SDMMC2 VQMMC supply to vdd (buck3). Note that in the
corresponding Linux kernel device tree, the supply is set to v3v3
(buck4), which is wrong.

Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agoarm: dts: stm32mp157c-odyssey-som: enable all SDMMC2 data lanes
Grzegorz Szymaszek [Wed, 2 Jun 2021 17:09:03 +0000 (19:09 +0200)]
arm: dts: stm32mp157c-odyssey-som: enable all SDMMC2 data lanes

Add the “sdmmc2_d47_pins_d” pins to the SDMMC2 pinctrls. Increase the
bus width from four to eight.

Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agoarm: dts: stm32mp157c-odyssey-som: fix the basic SDMMC2 properties
Grzegorz Szymaszek [Wed, 2 Jun 2021 17:08:23 +0000 (19:08 +0200)]
arm: dts: stm32mp157c-odyssey-som: fix the basic SDMMC2 properties

The SDMMC2 interface hosts an eMMC. Replace the interface properties
that would only apply to SD cards—“broken-cd” and “disable-wp”—with
relevant ones: “non-removable”, “no-sd” and “no-sdio”.

Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agoMerge tag 'u-boot-atmel-2021.10-a' of https://source.denx.de/u-boot/custodians/u...
Tom Rini [Thu, 17 Jun 2021 15:46:44 +0000 (11:46 -0400)]
Merge tag 'u-boot-atmel-2021.10-a' of https://source.denx.de/u-boot/custodians/u-boot-atmel into next

First set of u-boot-atmel features for the 2021.10 cycle:

This feature set converts the boards pm9261 and pm9263 Ethernet support
to DM; enables hash command for all SAM boards; fixes the NAND pmecc
bit-flips correction; adds Falcon boot for sama5d3_xplained board; and
other minor adjustments.

3 years agoMerge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into...
Tom Rini [Thu, 17 Jun 2021 15:46:23 +0000 (11:46 -0400)]
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next

- K210 updates

3 years agotest: Add K210 PLL tests to sandbox defconfigs
Sean Anderson [Fri, 11 Jun 2021 04:16:17 +0000 (00:16 -0400)]
test: Add K210 PLL tests to sandbox defconfigs

This adds the unit test for the K210 PLL to the sandbox defconfigs.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agok210: Don't imply CCF
Sean Anderson [Fri, 11 Jun 2021 04:16:16 +0000 (00:16 -0400)]
k210: Don't imply CCF

Now that the k210 clock driver does not depend on CCF, we should no longer
imply it (and probably should not have in the first place). We can also
reduce the pre-relocation malloc arena back to something sensible.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
3 years agok210: dts: Set PLL1 to the same rate as PLL0
Sean Anderson [Fri, 11 Jun 2021 04:16:15 +0000 (00:16 -0400)]
k210: dts: Set PLL1 to the same rate as PLL0

Linux has had some stability issues when using AISRAM with a different
frequency from SRAM. Mirror their change here now that we relocate into
AISRAM.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
3 years agoclk: k210: Move k210 clock out of its own subdirectory
Sean Anderson [Fri, 11 Jun 2021 04:16:14 +0000 (00:16 -0400)]
clk: k210: Move k210 clock out of its own subdirectory

Now that we have only one clock driver, we don't need to have our own
subdirectory. Move the driver back with the rest of the clock drivers.

The MAINTAINERS for kendryte pinctrl is also fixed since it has always been
wrong.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
3 years agoclk: k210: Remove bypass driver
Sean Anderson [Fri, 11 Jun 2021 04:16:13 +0000 (00:16 -0400)]
clk: k210: Remove bypass driver

This driver no longer serves a purpose now that we have moved away from
CCF. Drop it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
3 years agoclk: k210: Don't set PLL rates if we are already at the correct rate
Sean Anderson [Fri, 11 Jun 2021 04:16:12 +0000 (00:16 -0400)]
clk: k210: Don't set PLL rates if we are already at the correct rate

This speeds up boot by preventing multiple reconfigurations of the PLLs.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
3 years agoclk: k210: Re-add support for setting rate
Sean Anderson [Fri, 11 Jun 2021 04:16:11 +0000 (00:16 -0400)]
clk: k210: Re-add support for setting rate

This adds support for setting clock rates, which was left out of the
initial CCF expunging. There are several tricky bits here, mostly related
to the PLLS:

* The PLL's bypass is broken. If the PLL is reconfigured, any child clocks
  will be stopped.
* PLL0 is the parent of ACLK which is the CPU and SRAM's clock. To prevent
  stopping the CPU while we configure PLL0's rate, ACLK is reparented
  to IN0 while PLL0 is disabled.
* PLL1 is the parent of the AISRAM clock. This clock cannot be reparented,
  so we instead just disallow changing PLL1's rate after relocation (when
  we are using the AISRAM).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
3 years agoclk: k210: Implement soc_clk_dump
Sean Anderson [Fri, 11 Jun 2021 04:16:10 +0000 (00:16 -0400)]
clk: k210: Implement soc_clk_dump

Since we are no longer using CCF we cannot use the default soc_clk_dump.
Instead, implement our own.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
3 years agoclk: k210: Move pll into the rest of the driver
Sean Anderson [Fri, 11 Jun 2021 04:16:09 +0000 (00:16 -0400)]
clk: k210: Move pll into the rest of the driver

Now that there no separate PLL driver, we can no longer make the PLL
functions static. By moving the PLL driver in with the rest of the clock
code, we can make these functions static again. We still keep the pll
header for unit testing, but it is pretty reduced.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
3 years agoclk: k210: Rewrite to remove CCF
Sean Anderson [Fri, 11 Jun 2021 04:16:08 +0000 (00:16 -0400)]
clk: k210: Rewrite to remove CCF

This is effectively a complete rewrite to remove all dependency on CCF.
The code is now smaller, and so is the binary. It also takes up less memory
at runtime (since we don't have to create 40 udevices). In general, I am
much happier with this driver as much of the complexity and late binding
has been removed.

The k210_*_params structs which were previously used to initialize CCF
clocks are now used as the complete configuration. Since we can write our
own division logic, we can now do away with several "half" clocks which
only existed to provide constant factors of two.

The clock IDs have been renumbered to remove unused clocks. This may not be
the last time they are renumbered, since we have diverged with Linux. There
are also still a few clocks left out which may need to be added back in.

In general, I have tried to leave out behavioral changes. However, there is
a small bugfix regarding ACLK. According to the technical reference manual,
its mux comes *after* its divider (which is present only for PLL0). This
would have required yet another intermediate clock to fix with CCF, but
with the new driver it is just 2 lines of code :)

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
3 years agoclk: Allow force setting clock defaults before relocation
Sean Anderson [Fri, 11 Jun 2021 04:16:07 +0000 (00:16 -0400)]
clk: Allow force setting clock defaults before relocation

Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc
state for SPL only") it has been impossible to set clock defaults before
relocation. This is annoying on boards without SPL, since there is no way
to set clock defaults before U-Boot proper. In particular, the aisram rate
must be changed before relocation on the K210, since U-Boot will hang if we
try and change the rate while we are using aisram.

To get around this, extend the stage parameter to allow force setting
defaults, even if they would be otherwise postponed for later. A device
tree property was decided against because of the concerns in the original
commit thread about the overhead of repeatedly parsing the device tree.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoboard: sama5d3_xplained: add Falcon boot support
Michael Opdenacker [Mon, 31 May 2021 21:23:48 +0000 (23:23 +0200)]
board: sama5d3_xplained: add Falcon boot support

This supports Falcon boot support for Microchip SAMA5D3 Xplained,
tested on raw MMC, and on raw NAND.

spl_start_uboot() is has the simplest possible implementation.
It doesn't test the environment because enabling environment support
currently causes the SPL to exceed its maximum size (64 KiB).
It doesn't check the serial for incoming characters either because
this functionality currently doesn't seem to work from the SPL
on this board.

Settings for Falcon boot from at FAT partition are also added to
avoid compile failures when CONFIG_SPL_OS_BOOT is enabled, but this
particular case is currently not functional as adding FAT and
partition support cause the SPL to be too big again.

Signed-off-by: Michael Opdenacker <michael.opdenacker@bootlin.com>
3 years agoconfigs: sam boards: add hash command
Eugen Hristev [Wed, 26 May 2021 13:05:57 +0000 (16:05 +0300)]
configs: sam boards: add hash command

Add hash and hash verify commands. These would be useful for
verifying copied data.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
3 years agoMerge tag 'ti-v2021.10-next-v2' of https://source.denx.de/u-boot/custodians/u-boot...
Tom Rini [Sun, 13 Jun 2021 11:48:22 +0000 (07:48 -0400)]
Merge tag 'ti-v2021.10-next-v2' of https://source.denx.de/u-boot/custodians/u-boot-ti into next

- HSM re-architecture support for all K3 platforms
- AM64 USB support
- Driver model support for Davinci RTC

3 years agodma: ti: k3-udma: Add support for native configuration of chan/flow
Vignesh Raghavendra [Mon, 7 Jun 2021 14:17:53 +0000 (19:47 +0530)]
dma: ti: k3-udma: Add support for native configuration of chan/flow

In absence of Device Manager (DM) services such as at R5 SPL stage,
driver will have to natively setup TCHAN/RCHAN/RFLOW cfg registers.
Add support for the same.

Note that we still need to send chan/flow cfg message to TIFS via TISCI
client driver in order to open up firewalls around chan/flow but setting
up of cfg registers is handled locally.

U-Boot specific code is in a separate file included in main driver so
as to maintain similarity with kernel driver in order to ease porting of
code in future.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-8-vigneshr@ti.com
3 years agosoc: ti: k3-navss-ringacc: Add support for native configuration of rings
Vignesh Raghavendra [Mon, 7 Jun 2021 14:17:52 +0000 (19:47 +0530)]
soc: ti: k3-navss-ringacc: Add support for native configuration of rings

In absence of Device Manager (DM) services such as at R5 SPL stage,
driver will have to natively setup Ring Cfg registers. Add support for
the same.

Note that we still need to send RING_CFG message to TIFS via TISCI
client driver in order to open up firewalls around Rings.

U-Boot specific code is in a separate file included in main driver so
as to maintain similarity with kernel driver in order to ease porting of
code in future.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-7-vigneshr@ti.com
3 years agoARM: dts: k3: Add cfg register space for ringacc and udmap
Vignesh Raghavendra [Mon, 7 Jun 2021 14:17:51 +0000 (19:47 +0530)]
ARM: dts: k3: Add cfg register space for ringacc and udmap

R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING
CFG, TCHAN CFG and RCHAN CFG address ranges.
Note that these registers are present within respective IPs but are
not populated in Linux DT nodes (as they are configured via TISCI APIs)
and hence are added to -u-boot.dtsi for now.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-6-vigneshr@ti.com
3 years agoARM: dts: j72xx-r5-common-proc-board: Add DM firmware node
Vignesh Raghavendra [Mon, 7 Jun 2021 14:17:50 +0000 (19:47 +0530)]
ARM: dts: j72xx-r5-common-proc-board: Add DM firmware node

Add DM firmware node which will provide DM services during R5 SPL stage.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-5-vigneshr@ti.com
3 years agofirmware: ti_sci: Add support for Resoure Management at R5 SPL stage.
Vignesh Raghavendra [Mon, 7 Jun 2021 14:17:49 +0000 (19:47 +0530)]
firmware: ti_sci: Add support for Resoure Management at R5 SPL stage.

On J721e and J7200, MCU R5 core (boot master) itself would run Device
Manager (DM) Firmware and interact with TI Foundational Security (TIFS)
firmware to enable DMA and such other Resource Management (RM) services.
So, during R5 SPL stage there is no such RM service available and ti_sci
driver will have to directly interact with TIFS using DM to DMSC
channels to request RM resources.

Therefore add DT binding and driver for the same. This driver will
handle Resource Management services at R5 SPL stage.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-4-vigneshr@ti.com
3 years agofirmware: ti_sci: Implement GET_RANGE with static data
Vignesh Raghavendra [Mon, 7 Jun 2021 14:17:48 +0000 (19:47 +0530)]
firmware: ti_sci: Implement GET_RANGE with static data

In case of R5 SPL, GET_RANGE API service is not available (as DM
services are not yet up), therefore service such calls locally using
per SoC static data.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-3-vigneshr@ti.com
3 years agomailbox: k3-sec-proxy: Add DM to DMSC communication thread
Vignesh Raghavendra [Mon, 7 Jun 2021 14:17:47 +0000 (19:47 +0530)]
mailbox: k3-sec-proxy: Add DM to DMSC communication thread

R5 SPL would need to talk to DMSC using DM to DMSC sec-proxy threads.
Mark these as valid threads in the driver.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-2-vigneshr@ti.com
3 years agoarm: dts: k3-j72xx: correct MCU timer1 frequency
Tero Kristo [Fri, 11 Jun 2021 08:45:27 +0000 (11:45 +0300)]
arm: dts: k3-j72xx: correct MCU timer1 frequency

MCU timer1 is used as the tick timer for MCU R5 SPL, and the
clock-frequency defined in DT appears to be incorrect at the moment.
Actual clock source for the timer is MCU_SYSCLK0 / 4 which is 250MHz.

Earlier setup of 25MHz went unnoticed, as there was a separate issue
with omap-timer, which caused an error to the clock by a factor of 8
with j7 devices. This problem surfaced once the omap-timer was fixed.

Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoboard: ti: j72xx: README: update build instructions and image formats
Tero Kristo [Fri, 11 Jun 2021 08:45:26 +0000 (11:45 +0300)]
board: ti: j72xx: README: update build instructions and image formats

Update build instructions and image formats based on HSM rearch. A new
DM image is added into the build, which gets executed right after R5
SPL finishes its job.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoconfigs: j7200_evm_r5: Enable raw access power management features
Dave Gerlach [Fri, 11 Jun 2021 08:45:25 +0000 (11:45 +0300)]
configs: j7200_evm_r5: Enable raw access power management features

Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoconfigs: j721e_evm_r5: Enable raw access power management features
Tero Kristo [Fri, 11 Jun 2021 08:45:24 +0000 (11:45 +0300)]
configs: j721e_evm_r5: Enable raw access power management features

Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoarm: mach-k3: j721e_init: Force early probe of clk-k3 driver
Dave Gerlach [Fri, 11 Jun 2021 08:45:23 +0000 (11:45 +0300)]
arm: mach-k3: j721e_init: Force early probe of clk-k3 driver

Force the clk-k3 driver to probe early during R5 SPL boot to ensure the
default system clock configuration is completed. Many other drivers
assume a default state of the clock tree and it is currently possible
for them to probe before clk-k3 depending on the exact system
configuration.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Reported-by: Keerthy <j-keerthy@ti.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoarm: mach-k3: sysfw-loader: pass boardcfg to sciserver
Tero Kristo [Fri, 11 Jun 2021 08:45:22 +0000 (11:45 +0300)]
arm: mach-k3: sysfw-loader: pass boardcfg to sciserver

Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoarm: mach-k3: common: Drop main r5 start
Dave Gerlach [Fri, 11 Jun 2021 08:45:21 +0000 (11:45 +0300)]
arm: mach-k3: common: Drop main r5 start

Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoarm: mach-k3: do board config for PM only if supported
Tero Kristo [Fri, 11 Jun 2021 08:45:20 +0000 (11:45 +0300)]
arm: mach-k3: do board config for PM only if supported

If the raw PM support is built in, we are operating in the split
firmware approach mode where PM support is not available. In this
case, skip the board config for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoarm: mach-k3: add support for detecting firmware images from FIT
Tero Kristo [Fri, 11 Jun 2021 08:45:19 +0000 (11:45 +0300)]
arm: mach-k3: add support for detecting firmware images from FIT

Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoarm: mach-k3: Add platform data for j721e and j7200
Dave Gerlach [Fri, 11 Jun 2021 08:45:18 +0000 (11:45 +0300)]
arm: mach-k3: Add platform data for j721e and j7200

Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agotools: k3_fit_atf: add DM binary to the FIT image
Tero Kristo [Fri, 11 Jun 2021 08:45:17 +0000 (11:45 +0300)]
tools: k3_fit_atf: add DM binary to the FIT image

Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agocmd: ti: pd: Add debug command for K3 power domains
Tero Kristo [Fri, 11 Jun 2021 08:45:16 +0000 (11:45 +0300)]
cmd: ti: pd: Add debug command for K3 power domains

Add support command for debugging K3 power domains. This is useful with
the HSM rearch setup, where power domains are directly controlled by SPL
instead of going through the TI SCI layer. The debugging support is only
available in the u-boot codebase though, so the raw register access
power domain layer must be enabled on u-boot side for this to work. By
default, u-boot side uses the TI SCI layer, and R5 SPL only uses the
direct access methods.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
3 years agopower: domain: Introduce driver for raw TI K3 PDs
Tero Kristo [Fri, 11 Jun 2021 08:45:15 +0000 (11:45 +0300)]
power: domain: Introduce driver for raw TI K3 PDs

Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
3 years agoclk: add support for TI K3 SoC clocks
Tero Kristo [Fri, 11 Jun 2021 08:45:14 +0000 (11:45 +0300)]
clk: add support for TI K3 SoC clocks

Add driver to support TI K3 generation SoC clocks. This driver registers
the clocks provided via platform data, and adds support for controlling
the clocks via DT handles.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoclk: add support for TI K3 SoC PLL
Tero Kristo [Fri, 11 Jun 2021 08:45:13 +0000 (11:45 +0300)]
clk: add support for TI K3 SoC PLL

Add support for TI K3 SoC PLLs. This clock type supports
enabling/disabling/setting and querying the clock rate for the PLL. The
euclidean library routine is used to calculate divider/multiplier rates
for the PLLs.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoclk: fix set_rate to clean up cached rates for the hierarchy
Tero Kristo [Fri, 11 Jun 2021 08:45:12 +0000 (11:45 +0300)]
clk: fix set_rate to clean up cached rates for the hierarchy

Clock rates are cached within the individual clock nodes, and right now
if one changes a clock rate somewhere in the middle of the tree, none
of its child clocks notice the change. To fix this, clear up all the
cached rates for us and our child clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoclk: fix assigned-clocks to pass with deferring provider
Tero Kristo [Fri, 11 Jun 2021 08:45:11 +0000 (11:45 +0300)]
clk: fix assigned-clocks to pass with deferring provider

If a clock provider is not ready for assigning default rates/parents
during its probe, it may return -EPROBE_DEFER directly from xlate.
Handle this special case properly by skipping the entry and adjusting the
return value to pass. The defaults will be handled properly in post probe
phase then.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoclk: sci-clk: fix return value of set_rate
Tero Kristo [Fri, 11 Jun 2021 08:45:10 +0000 (11:45 +0300)]
clk: sci-clk: fix return value of set_rate

Set rate should return the new clock rate on success, and negative error
value on failure. Fix this, as currently set_rate returns 0 on success.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoclk: add support for setting clk rate from cmdline
Tero Kristo [Fri, 11 Jun 2021 08:45:09 +0000 (11:45 +0300)]
clk: add support for setting clk rate from cmdline

Add new clk subcommand "clk setfreq", for setting up a clock rate
directly from u-boot cmdline. This is handy for any debugging purposes
towards clocks.

Acked-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoclk: do not attempt to fetch clock pointer with null device
Tero Kristo [Fri, 11 Jun 2021 08:45:08 +0000 (11:45 +0300)]
clk: do not attempt to fetch clock pointer with null device

Bail out early if device returned for the parent clock is null.
This avoids warning prints like this when doing clk dump:

  dev_get_uclass_priv: null device

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoclk: fix clock tree dump to properly dump out every registered clock
Tero Kristo [Fri, 11 Jun 2021 08:45:07 +0000 (11:45 +0300)]
clk: fix clock tree dump to properly dump out every registered clock

Some clocks are not associated to a DM node, so just parsing the DM is not
enough. This is especially true for root clocks, which typically don't have
any parents. Instead, fetch every registered UCLASS_CLK instance, and dump
these out.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoclk: fixed_rate: add API for directly registering fixed rate clocks
Tero Kristo [Fri, 11 Jun 2021 08:45:06 +0000 (11:45 +0300)]
clk: fixed_rate: add API for directly registering fixed rate clocks

Current driver only supports registering fixed rate clocks from DT. Add
new API which makes it possible to register fixed rate clocks directly
from e.g. platform specific clock drivers.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agocommon: fit: Update board_fit_image_post_process() to pass fit and node_offset
Lokesh Vutla [Fri, 11 Jun 2021 08:45:05 +0000 (11:45 +0300)]
common: fit: Update board_fit_image_post_process() to pass fit and node_offset

board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoremoteproc: k3-r5: remove sysfw PM calls if not supported
Tero Kristo [Fri, 11 Jun 2021 08:45:04 +0000 (11:45 +0300)]
remoteproc: k3-r5: remove sysfw PM calls if not supported

With the sysfw rearch, sysfw PM calls are no longer available from SPL
level. To properly support this, remove the is_on checks and the reset
assertion from the R5 remoteproc driver as these are not supported.
Attempting to access unavailable services will cause the device to hang.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agoarm: mach-k3: introduce new config option for sysfw split
Tero Kristo [Fri, 11 Jun 2021 08:45:03 +0000 (11:45 +0300)]
arm: mach-k3: introduce new config option for sysfw split

On J7 family of SoCs (J721E and J7200), sysfw is being split to be run
under two cores, TIFS portion on DMSC core, and DM firmware under MCU
R5. As MCU R5 is also used to run one phase of the bootloader, we must
prevent access from here towards sysfw services. To support this, add
new config option which can be used to detect presence of RM/PM sysfw
services.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agolib: rational: copy the rational fraction lib routines from Linux
Tero Kristo [Fri, 11 Jun 2021 08:45:02 +0000 (11:45 +0300)]
lib: rational: copy the rational fraction lib routines from Linux

Copy the best rational approximation calculation routines from Linux.
Typical usecase for these routines is to calculate the M/N divider
values for PLLs to reach a specific clock rate.

This is based on linux kernel commit:
"lib/math/rational.c: fix possible incorrect result from rational
fractions helper"
(sha1: 323dd2c3ed0641f49e89b4e420f9eef5d3d5a881)

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
3 years agortc: davinci: fix date loaded on reset
Dario Binacchi [Wed, 2 Jun 2021 20:38:05 +0000 (22:38 +0200)]
rtc: davinci: fix date loaded on reset

On reset, the RTC loads the 2000-01-01 date with a wrong day of the
week (Sunday instead of Saturday).

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210602203805.11494-9-dariobin@libero.it
3 years agortc: davinci: add driver model support
Dario Binacchi [Wed, 2 Jun 2021 20:38:04 +0000 (22:38 +0200)]
rtc: davinci: add driver model support

Update the driver to support the device tree and the driver model.
The read / write helpers in rtc_ops allow access to scratch registers
only. The offset parameter is added to the address of the scratch0
register.

Support for non-DM has been removed as there were no users.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210602203805.11494-8-dariobin@libero.it
3 years agoarm: dts: sync rtc node of am335x boards with Linux 5.9-rc7
Dario Binacchi [Wed, 2 Jun 2021 20:38:03 +0000 (22:38 +0200)]
arm: dts: sync rtc node of am335x boards with Linux 5.9-rc7

There have been some changes to the am335x-<board> DTs related to the
rtc node, so let's re-syncs them with Linux.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210602203805.11494-7-dariobin@libero.it
3 years agortc: davinci: use unlock/lock mechanism
Dario Binacchi [Wed, 2 Jun 2021 20:38:02 +0000 (22:38 +0200)]
rtc: davinci: use unlock/lock mechanism

The RTC module contains a kicker mechanism to prevent any spurious
writes from changing the register values. To set the time, you must
first unlock the TC registers, update them and then lock.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210602203805.11494-6-dariobin@libero.it