Michal Simek [Thu, 1 Feb 2024 12:38:41 +0000 (13:38 +0100)]
arm64: zynqmp: Remove arm,cortex-a53-edac node
There is no dt schema associated with it. Also Linux driver have been
removed in Xilinx Linux tree and never gets to upstream that's why remove
description for it.
Michal Simek [Tue, 30 Jan 2024 14:51:06 +0000 (15:51 +0100)]
arm64: zynqmp: Fix kr260 clock wiring
kr260 revA/revA01 is using discrete oscilator for DP (27MHz) and si5332 for
other clocks but clocks are different compare to kv260 that's why fix it to
aligned with the latest schematics.
On the other handle kr260 revB/revA03 also contains 74.25 MHz discrete
clock chip for SLVC-EC output which is not defined.
Michal Simek [Mon, 29 Jan 2024 07:46:43 +0000 (08:46 +0100)]
arm64: zynqmp: Describe 25MHz fixed clock for PL GEMs
Describe 25Mhz fixed oscilator which is providing clock for PL based
ethernet IPs. Physicially it is one chip but it is described as 2 fixed
clock to be aligned with other SOM versions which were using integrated
clock generators where clocks could be adjusted via i2c (si5332 chips).
Michal Simek [Fri, 26 Jan 2024 07:24:41 +0000 (08:24 +0100)]
arm64: zynqmp: Sync clock labels with kr260 revB
Board description describes the hard part of chip (PS) but programmable
logic (PL) part is not described in this file. But clocks on the board are
not only connected to PS but also wired to PL. And because two revisions
are available where revA is using one si5332 and revB multiple clock chips
using the same clock labels helping with keeping only one device tree
overlay which targets PL. That's why synchronize clock labels and use
labels from revB which are more generic.
Unfortunately if there is driver for si5332 chip split could happen again
but it is still worth to do it now and solve this issue when occurs.
Saeed Nowshadi [Thu, 25 Jan 2024 08:07:58 +0000 (09:07 +0100)]
arm64: zynqmp: Add 'silabs, skip-recall' to all si570 clk nodes
Without 'silabs,skip-recall' property, the driver on System Controller
re-calibrates the output clock frequency at probe() time based on the NVRAM
setting. This re-calibration causes a glitch on the output clock. At
power-on, Versal is also booting and expecting a glitch-free clock for
its correct operation. System Controller should skip the re-calibration
step to prevent any clock instability for Versal.
Michal Simek [Wed, 24 Jan 2024 10:58:40 +0000 (11:58 +0100)]
arm64: xilinx: Enable EFI_HTTP_BOOT by default
Enable EFI_HTTP_BOOT to be able to booting OS via http.
In case of that dhcp server is not providing dns server IP set it up via
setenv dnsip <ip addr>.
configs: versal_net: Enable CONFIG_LTO for mini qspi/ospi
Adding a tiny bit more code for mini u-boot leads to a OCM
image overflow. Fix this by enabling LTO for this board, so that such
changes still can be made to the common U-Boot code.
Enable building mini u-boot image with LTO, which results in about 8KB
reduction in size.
configs: versal: Enable CONFIG_LTO for mini qspi/ospi
Adding a tiny bit more code for mini u-boot leads to a OCM
image overflow. Fix this by enabling LTO for this board, so that such
changes still can be made to the common U-Boot code.
Enable building mini u-boot image with LTO, which results in about 8KB
reduction in size.
Hai Pham [Sun, 28 Jan 2024 15:52:08 +0000 (16:52 +0100)]
ARM: dts: renesas: Add Renesas Gray Hawk boards support
Initial support for the Renesas Gray Hawk CPU and BreakOut boards.
The arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi is extended version of:
https://lore.kernel.org/linux-renesas-soc/b657402113267acd57aece0b4c681b707e704455.1706194617.git.geert+renesas@glider.be/
The version currenty submitted upstream lacks functionality which is
present in this series. Once the upstream support implements that
missing functionality, these DTs will be updated to match.
Hai Pham [Sun, 28 Jan 2024 15:52:06 +0000 (16:52 +0100)]
ARM: dts: renesas: Add Renesas R8A779H0 V4M SoC support
Add initial support for the Renesas R8A779H0 (R-Car V4M) SoC.
The current version is imported and modified from:
https://lore.kernel.org/linux-renesas-soc/4107bc3d7c31932da29e671ddf4b1564ba38a84c.1706194617.git.geert+renesas@glider.be/
The modifications contain nodes from previous version
which are useful in U-Boot and not part of the Linux
kernel DT yet. The following nodes were added:
- pfc
- gpio0..gpio7
- i2c0..i2c3
- avb0..avb2
- mmc0
Hai Pham [Sun, 28 Jan 2024 15:52:05 +0000 (16:52 +0100)]
mtd: spi: renesas: Add R8A779H0 V4M support
Support RPC SPI on R8A779H0 V4M SoC.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Hai Pham [Sun, 28 Jan 2024 15:52:03 +0000 (16:52 +0100)]
pinctrl: renesas: Add R8A779H0 V4M PFC tables
Add pinctrl tables for R8A779H0 V4M SoC.
The current version of these PFC tables is imported and squashed from:
https://lore.kernel.org/linux-renesas-soc/cover.1706264667.git.geert+renesas@glider.be/
Marek Vasut [Sun, 28 Jan 2024 15:52:02 +0000 (16:52 +0100)]
clk: renesas: Implement R8A779H0 V4M PLL7 support
Add PLL7 support to Gen3/Gen4 common clock driver. Add initial PLL7
multiplier and divider values into table in R8A779H0 V4M clock driver.
The PLL7 is new PLL added in R8A779H0 V4M SoC. Only integer multiplication
mode is supported by PLL7. The PLL reference clock are either 16.66 MHz or
20 MHz on R8A779H0 V4M SoC, and the output frequency must be 2000 MHz. The
multiplier values fitting this requirement are calculated to 120 or 100.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Hai Pham [Sun, 28 Jan 2024 15:52:01 +0000 (16:52 +0100)]
clk: renesas: Add R8A779H0 V4M clock tables
Add clock tables for R8A779H0 V4M SoC.
The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be/
The current version still contains PLL7 extras from the
previous version to provide ethernet support in U-Boot.
Sean Anderson [Thu, 1 Feb 2024 18:18:51 +0000 (13:18 -0500)]
lib: sparse: Fix error checking for write_sparse_chunk_raw
The return value of write_sparse_chunk_raw is unsigned, so the existing
check has no effect. Use IS_ERR_VALUE to detect error instead, which is
what write_sparse_chunk_raw does itself.
Igor has not been active for quite some time on lore:
https://lore.kernel.org/all/?q=igor.opaniuk@gmail.com
I'm interested in helping with maintaining the android_avb
command. I'm a long time android/aosp developer and my daily job is
still doing android work.
Add myself as maintainer for Android AVB.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io> Acked-by: Igor Opaniuk <igor.opaniuk@foundries.io> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240112-maintainers-ab-v1-2-f2a538eab18a@baylibre.com Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Igor has not been active for quite some time on lore:
https://lore.kernel.org/all/?q=igor.opaniuk@gmail.com
I'm interested in helping with maintaining the android_ab
command. I'm a long time android/aosp developer and my daily job is
still doing android work.
Tom Rini [Thu, 8 Feb 2024 14:37:16 +0000 (09:37 -0500)]
Merge tag 'u-boot-imx-master-20240208' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Add USB support for phycore-imx8mp
- Fix environment corruption, reset on mx6sabresd
- Print reset cause on imx8
- Extend mkimage to support generating an image for i.MXRT FlexSPI
- Add new apalis and colibri variants
- Add support for phyBOARD-Segin-i.MX93 support
- Fix when FEC is primarily used instead of EQOS on i.MX93.
Primoz Fiser [Tue, 30 Jan 2024 12:43:37 +0000 (13:43 +0100)]
imx9: clock: Fix board_interface_eth_init for FEC
Commit d5eae216d833 ("net: dwc_eth_qos: Add board_interface_eth_init()
for i.MX93") implemented board_interface_eth_init for i.MX9 platforms.
However it only accounted for the EQOS interface while any board using
FEC as primary Ethernet interface was left out as return value -EINVAL
is always returned from the function in such case.
Fix this by returning 0 (success) when FEC interface is primarily used
instead of EQOS interface on i.MX93.
Marek Vasut [Mon, 22 Jan 2024 14:55:48 +0000 (15:55 +0100)]
ARM: imx: Enable kaslrseed command on Data Modul i.MX8M Mini/Plus eDM SBC
Linux 6.6.y with KASLR enabled would print the following message on boot:
"
KASLR disabled due to lack of seed
"
Enable the 'kaslrseed' command so a random number seed can be pulled
from CAAM and inserted into the /chosen node 'kaslr-seed' property of
Linux kernel DT before boot, thus letting KASLR work properly.
Mike Looijmans [Tue, 30 Jan 2024 14:26:56 +0000 (15:26 +0100)]
fsl-layerscape/soc.c: do not destroy bootcmd environment
When an XXX_BOOTCOMMAND isn't defined, the result is that bootcmd is set
to some random memory content. Fix it so that the function does nothing
in that case and leaves the bootcmd environment unmodified.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
Dhruva Gole [Tue, 30 Jan 2024 15:00:00 +0000 (20:30 +0530)]
firmware: ti_sci: Add comment explaining the is_secure code
Add a comment to explain the code under is_secure condition of
ti_sci_do_xfer. This will help avoid confusion amongst people who may in
future touch upon this code.
Dhruva Gole [Tue, 30 Jan 2024 14:59:59 +0000 (20:29 +0530)]
firmware: ti_sci: fix the secure_hdr in do_xfer
The ti_sci driver in U-Boot has support for secure_msg as part of it's
do_xfer function. This let's U-boot send secure messages during boot up.
The protocol to send such secure messages is described as part of the
struct ti_sci_secure_msg_hdr. As part of this, there are 2 fields for
checksum and reserved that occupy the first 4 bytes of any secure
message. This is called as the secure_hdr.
As of now, the secure_hdr needs to be 0 init-ed before sending secure
messages. However the existing code was never putting the zero-inited vars
into the secure_buf, leading to possibility of the first 4 bytes of
secure_buf being possibly garbage.
Fix this by initialising the secure_hdr itself to the secure_buf
location, thus when we make secure_hdr members 0, it automatically ensures
the first 4 bytes of secure_buf are 0.
Fixes: 32cd25128bd849 ("firmware: Add basic support for TI System Control Interface (TI SCI)") Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Dhruva Gole <d-gole@ti.com>
arm: mach-k3: j721s2_init: Support less than max DDR controllers
The number of DDR controllers to be initialised and used should depend
on the device tree with the constraint of the maximum number of
controllers the device supports. Since J721S2 has multiple (2)
controllers, instead of hardcoding the number of probes, move to
depending on the device tree UCLASS_RAM nodes present.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
dma: ti: k3-udma: Use ring_idx to pair k3 nav rings
Use ring_idx to pair rings. ring_idx will be same as tx flow_id for all
non-negative flow_ids. For negative flow_ids, ring_idx will be tchan->id
added with bchan_cnt.
Brandon Maier [Mon, 22 Jan 2024 18:45:50 +0000 (18:45 +0000)]
scripts/gen_compile_commands: update to Linux v6.7
Adds support for assembly files and updates the LINE_PATTERN so it
supports both "cmd" and "savedcmd", which allows reverting the U-Boot
modification in commit 97fbb2eb016b ("scripts/gen_compile_commands.py:
adapt _LINE_PATTERN").
Upstream commits:
- 880946158b011 gen_compile_commands.py: fix path resolve with symlinks in it
- 9e56d3be4bfd2 gen_compile_commands: Sort output compile commands by file name
- 52c15e7e79285 gen_compile_commands: Allow the line prefix to still be cmd_
- 1c67921444bf6 gen_compile_commands: add assembly files to compilation database
Signed-off-by: Brandon Maier <brandon.maier@collins.com> Cc: Joao Marcos Costa <jmcosta944@gmail.com>
Tom Rini [Mon, 5 Feb 2024 18:33:01 +0000 (13:33 -0500)]
Merge patch series "board: siemens: clean up subfolders"
Enrico Leto <enrico.leto@siemens.com> says:
The common folder was initialially created for the common parts of
the products based on draco-am355x board family. We have the
product lines 'pxm2', 'rut' and the base line unfortunately named
'draco'! Adding the new capricorn-imx8 board family, the files
were enhanced without cleanup.
Simplify first EEPROM probe and access that implements both i2c
with & without driver model. Use abstraction functions for this.
Move all am355x specifics to a new file 'board_am335x'.
Enrico Leto [Wed, 24 Jan 2024 14:43:55 +0000 (15:43 +0100)]
siemens: factoryset: use correct config for soc specific implementation
Adding the capricorn board family some parts diverge from draco family.
The switches used were not pertinent and need to be enhanced for each new
board of the capricorn family. Replace them through the SOC name 'AM33XX'
and 'IMX8'.
Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
Enrico Leto [Wed, 24 Jan 2024 14:43:53 +0000 (15:43 +0100)]
siemens: board: clean up products folders vs common
The common folder was initialially created for the common parts of the
products based on draco-am355x board family. These are the product lines
'pxm2', 'rut' and the base line named 'draco'!
Adding the new capricorn-imx8 board family, common was enhanced without
cleanup.
- rename 'common/board.c' to 'common/board_am335x.c'
- add 'common/board_am335x.h' for export to the product lines
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
Jonas Karlman [Wed, 31 Jan 2024 22:07:14 +0000 (22:07 +0000)]
rockchip: rk3568-generic: Enable eMMC HS200 mode
Writing to eMMC using HS200 mode work more reliably then other modes on
RK356x boards.
Add device tree props and enable Kconfig options for eMMC HS200 mode on
the generic RK3566/RK3568 board. Also enable the pinctrl driver in SPL
and add missing rk3568-generic.dtb to Makefile.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 4 Feb 2024 20:53:06 +0000 (20:53 +0000)]
rockchip: rk35xx: Enable eMMC HS200 mode by default
Testing has shown that writing to eMMC using a slower mode then HS200
typically generate an ERROR on first attempt on RK3588.
# Rescan using MMC legacy mode
=> mmc rescan 0
# Write a single block to sector 0x4000 fails with ERROR
=> mmc write 20000000 4000 1
# Write a single block to sector 0x4000 now works
=> mmc write 20000000 4000 1
With the MMC_SPEED_MODE_SET Kconfig option enabled.
Writing to eMMC using HS200 mode work more reliably than slower modes on
RK35xx boards. Enable MMC_HS200_SUPPORT Kconfig option by default to
prefer use of HS200 mode on RK356x and RK3588.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a default u-boot,spl-boot-order prop to rk3588s-u-boot.dtsi and
remove the prop from board u-boot.dtsi files using the default value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 26 Jan 2024 22:14:51 +0000 (22:14 +0000)]
rockchip: rk356x: Move common uart2 props to rk356x-u-boot.dtsi
Move uart2 bootph-pre-ram and clock-frequency props from board to SoC
u-boot.dtsi. Regular board device tree already enables the uart2 node,
so status prop is dropped from u-boot.dtsi file.
Also remove unnecessary stdout-path = &uart2, regular board device tree
already provide a stdout-path = "serial2:" value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Shantur Rathore [Sun, 21 Jan 2024 22:04:47 +0000 (22:04 +0000)]
arch: arm: mach-rockchip: Kconfig: Enable BOOTSTD_FULL for RK3399 and RK3588
Rockchip RK3399 and RK3588 SoCs can support wide range of bootflows.
Without full bootflow commands, it can be difficult to
figure out issues if any, hence enable by default.
Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Shantur Rathore <i@shantur.com>
Tim Lunn [Wed, 24 Jan 2024 03:26:00 +0000 (14:26 +1100)]
board: rockchip: Add Sonoff iHost board
Sonoff iHost is gateway device designed to provide a Smart Home Hub,
it is based on Rockchip RV1126. There is also a version with 2GB RAM
based off the RV1109 dual core SoC however this works with the same
config as the RV1126 for uboot purposes.
Tim Lunn [Wed, 24 Jan 2024 03:25:58 +0000 (14:25 +1100)]
ram: rockchip: Add rv1126 ddr4 support
Add support for ddr4 on rv1126. Timing detection files are imported
from downstream Rockchip BSP u-boot. Allow selecting ddr4 ram with
define CONFIG_RAM_ROCKCHIP_DDR4.
Signed-off-by: Tim Lunn <tim@feathertop.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Thu, 18 Jan 2024 07:19:46 +0000 (07:19 +0000)]
rockchip: rk3328-rock-pi-e: Enable DM_ETH_PHY and PHY_REALTEK
Enable the DM_ETH_PHY and PHY_REALTEK now that the designware ethernet
driver call eth_phy_set_mdio_bus() to assist with resetting the eth PHY
during probe.
Fixes ethernet on the v1.21 hw revision of Radxa ROCK Pi E:
=> mdio list
ethernet@ff540000:
1 - RealTek RTL8211F <--> ethernet@ff540000
=> net list
eth0 : ethernet@ff540000 86:e0:c0:ea:fa:a9 active
eth1 : ethernet@ff550000 86:e0:c0:ea:fa:a8
=> dhcp
Speed: 1000, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
DHCP client bound to address 192.168.1.114 (1004 ms)
Reported-by: Trevor Woerner <twoerner@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Thu, 18 Jan 2024 07:19:45 +0000 (07:19 +0000)]
net: designware: Reset eth phy before phy connect
Some ethernet PHY require being reset before a phy-id can be read back
on the MDIO bus. This can result in the following message being show
on e.g. a Radxa ROCK Pi E v1.21 with a RTL8211F ethernet PHY.
Add support to designware ethernet driver to reset eth phy by calling
the eth phy uclass function eth_phy_set_mdio_bus(). The call use NULL
as bus parameter to not set a shared mdio bus reference that would be
freed when probe fails. Also add a eth_phy_get_addr() call to try and
get the phy addr from DT when DM_MDIO is disabled.
This help fix ethernet on Radxa ROCK Pi E v1.21:
=> mdio list
ethernet@ff540000:
1 - RealTek RTL8211F <--> ethernet@ff540000
Reported-by: Trevor Woerner <twoerner@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Sat, 3 Feb 2024 14:11:25 +0000 (09:11 -0500)]
Merge tag 'smbios-2024-04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request smbios-2024-04-rc2
* In smbios command
- write 'Not Specified' for missing strings
- show correct table size for SMBIOS2.1 entry point
- adjust formatting of handle numbers
- add missing colon after UUID
* In generated SMBIOS table
- avoid introducing 'Unknown' string for missing properties
- provide RISC-V vendor ID in the type 4 structure
- provide the correct chassis handle in structure type 2
* Rename Structure Table Maximum Size field in SMBIOS 3 entry point
smbios: correctly name Structure Table Maximum Size field
In the SMBIOS 3 entry point the Structure Table Maximum Size field was
incorrectly named max_struct_size. A Maximum Structure Size field only
exists in the SMBIOS 2.1 entry point and has a different meaning.
Call the Structure Table Length field table_maximum_size.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Only the SMBIOS 2.1 entry point has a field for the maximum structure size.
As we have switched to an SMBIOS 3 entry point remove the superfluous
calculation.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
projects / u-boot.git / log