Tom Rini [Sun, 5 Jul 2020 22:03:32 +0000 (18:03 -0400)]
Merge branch '2020-07-01-kconfig-etc-updates' into next
- Resync Kconfiglib with the v14.1.0 release.
- Re-sync our <linux/compiler*h> files with v5.7-rc5 from upstream.
- Fully resync checkpatch.pl with v5.7 release.
To safely to all of the above, we have a few bugfixes about functions
that need a 'static inline' but weren't. We also stop setting
CROSS_COMPILE in arch/*/config.mk. Finally, with the above changes
boards can now opt-in to optimizing inlining and we do this for the
socfpga stratix10 platform for space savings.
Tom Rini [Tue, 16 Jun 2020 14:29:46 +0000 (10:29 -0400)]
checkpatch.pl: Fully re-sync with v5.7
While commit 048a648298b1 ("checkpatch.pl: Update to v5.7") largely
re-syncs us with checkpatch.pl from v5.7 there are a number of things
missing still. Re-copy the script and again take care to keep our
allowed debug prints and now localized checks intact.
Fixes: 048a648298b1 ("checkpatch.pl: Update to v5.7") Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:09 +0000 (08:30 -0400)]
socfpga: Enable optimized inlining on stratix10
Enable the new CONFIG_OPTIMIZE_INLINING and CONFIG_SPL_OPTIMIZE_INLINING
options for this platform. With gcc-9.2 from kernel.org this saves us
1784 bytes in U-Boot and 80 bytes in SPL.
Cc: Marek Vasut <marex@denx.de> Cc: Chin-Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinh.nguyen@intel.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Vasut <marex@denx.de>
Tom Rini [Thu, 14 May 2020 12:30:07 +0000 (08:30 -0400)]
compiler_types.h: Re-introduce CONFIG_OPTIMIZE_INLINING for U-Boot
In the Linux kernel, support for forcing inline functions to be made
inline, rather than allowing the compiler to make its own choice has
been removed. With respect to performance, modern GCC (and Clang) do a
good job at deciding when to, or not to, inline code and there are no
run-time requirements in Linux anymore.
There is one downside to this, which is final binary size. On average
in U-Boot removing this support grows SPL by almost 1 kilobyte. But
there are cases where it shrinks the binary by making better inline
choices than we had forced.
Start by re-introducing CONFIG_OPTIMIZE_INLINING as a global which
essentially reverts 889b3c1245de ("compiler: remove CONFIG_OPTIMIZE_INLINING entirely")
from Linux.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:06 +0000 (08:30 -0400)]
compiler*.h: sync include/linux/compiler*.h with Linux 5.7-rc5
Copy these from Linux v5.7-rc5 tag.
This brings in some handy new attributes and is otherwise important to
keep in sync.
We drop the reference to smp_read_barrier_depends() as it is not
relevant on the architectures we support at this time, based on where
it's implemented in Linux today. We drop the call to kasan_check_read()
as that is not relevant to U-Boot as well.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:05 +0000 (08:30 -0400)]
socfpga: Mark socfpga_fpga_add() as static inline in the non-FPGA case
Unless we mark the function as 'static inline' it may end up being
non-inlined by the compiled and result in duplicate functions.
Cc: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Vasut <marex@denx.de>
Tom Rini [Thu, 14 May 2020 12:30:04 +0000 (08:30 -0400)]
x86: Convert from ACCESS_ONCE to READ/WRITE_ONCE
In order to update our <linux/compiler.h> to a newer version that no
longer provides ACCESS_ONCE() but only READ_ONCE()/WRITE_ONCE() we need
to convert arch/x86/include/asm/atomic.h to the other macros.
Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 14 May 2020 12:30:03 +0000 (08:30 -0400)]
tegra: Convert from ACCESS_ONCE to READ/WRITE_ONCE
In order to update our <linux/compiler.h> to a newer version that no
longer provides ACCESS_ONCE() but only READ_ONCE()/WRITE_ONCE() we need
to convert arch/arm/mach-tegra/ivc.c to the other macros.
Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:02 +0000 (08:30 -0400)]
Don't start ad-hoc games with -Wno-maybe-initialized
Borrowing from Linux commit 78a5255ffb6a ("Stop the ad-hoc games with -Wno-maybe-initialized")
move to have maybe-initialized warnings be handled with building with
W=2 instead of playing more guessing games with newer compilers.
Tom Rini [Thu, 14 May 2020 12:30:01 +0000 (08:30 -0400)]
kconfig: Add scripts/Kconfig.include from v4.19
As part of re-syncing our Kconfig logic up to v4.19, we had missed
adding this new file that includes helper macros. To quote the upstream
commit e1cfdc0e72fc ("kconfig: add basic helper macros to scripts/Kconfig.include"):
Kconfig got text processing tools like we see in Make. Add Kconfig
helper macros to scripts/Kconfig.include like we collect Makefile
macros in scripts/Kbuild.include.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 19 May 2020 14:32:33 +0000 (10:32 -0400)]
Remove CROSS_COMPILE default from arch/*/config.mk
In order to support the compiler providing information used within
Kconfig itself we cannot have the compiler be determined by
arch/*/config.mk as we will not be able to evaluate that yet. Given
that most documentation tells people to specify CROSS_COMPILE, remove
these references.
Cc: Huan Wang <alison.wang@nxp.com> Cc: Angelo Dureghello <angelo@sysam.it> Cc: Michal Simek <monstr@monstr.eu> Cc: Rick Chen <rick@andestech.com> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Wolfgang Denk <wd@denx.de> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
riscv: cpu: check and append L1 cache to cpu features
All cpu cores within FU540-C000 having split I/D caches.
Set the L1 cache feature bit using the i-cache-size or d-cache-size
as one of the property from device tree indicating that L1 cache is
present on the cpu core.
riscv: cpu: correctly handle the setting of CPU_FEAT_MMU bit
The conditional check to read "mmu-type" from the device tree
is not rightly handled due to which the cpu feature doesn't include
CPU_FEAT_MMU even if it's corresponding entry is present in the device
tree.
The initialization of cpu features is now taken care in cpu-uclass
driver, so no need to zero out cpu_freq in riscv_cpu driver and can be
removed.
The cmd "cpu detail" fetches uninitialized cpu feature information
and thus displays wrong / inconsitent details as below.
For eg: FU540-C000 doesn't have any microcode, yet the cmd display's it.
=> cpu detail
1: cpu@1 rv64imafdc
ID = 1, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
The L1 cache or MMU entry seen above is also displayed inconsistently.
So initialize cpu information to zero into cpu-uclass itself so that
similar issues can be avoided for other CPU drivers.
We now see correct features as:
=> cpu detail
1: cpu@1 rv64imafdc
ID = 1, freq = 999.100 MHz
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz
Add cpu aliases to U-Boot specific dtsi for hifive-unleashed.
Without aliases we see that the CPU device sequence numbers are set
randomly and the cpu list/detail command will show it as follows:
=> cpu list
1: cpu@1 rv64imafdc
2: cpu@2 rv64imafdc
3: cpu@3 rv64imafdc
0: cpu@4 rv64imafdc
Seems like CPU probing with dm-model also relies on aliases as observed
in case spi. The fu540-c000-u-boot.dtsi has cpu nodes and so adding
corresponding aliases we can ensure that cpu devices are assigned
proper sequence as follows:
=> cpu list
1: cpu@1 rv64imafdc
2: cpu@2 rv64imafdc
3: cpu@3 rv64imafdc
4: cpu@4 rv64imafdc
Sean Anderson [Wed, 24 Jun 2020 10:41:25 +0000 (06:41 -0400)]
riscv: Add Sipeed Maix support
The Sipeed Maix series is a collection of boards built around the RISC-V
Kendryte K210 processor. This processor contains several peripherals to
accelerate neural network processing and other "ai" tasks. This includes a
"KPU" neural network processor, an audio processor supporting beamforming
reception, and a digital video port supporting capture and output at VGA
resolution. Other peripherals include 8M of sram (accessible with and
without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256
accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix
peripherals vary, but include spi flash; on-board usb-serial bridges; ports
for cameras, displays, and sd cards; and ESP32 chips. Currently, only the
Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly
similar.
Documentation for Maix boards is located at
<http://dl.sipeed.com/MAIX/HDK/>. Documentation for the Kendryte K210 is
located at <https://kendryte.com/downloads/>. However, hardware details are
rather lacking, so most technical reference has been taken from the
standalone sdk located at
<https://github.com/kendryte/kendryte-standalone-sdk>.
Sean Anderson [Wed, 24 Jun 2020 10:41:23 +0000 (06:41 -0400)]
riscv: Add device tree for K210 and Sipeed Maix BitM
Where possible, I have tried to find compatible drivers based on the layout
of registers. However, many devices remain untested. All untested devices
have been left disabled, but some tentative properties (such as compatible
strings, and clocks, interrupts, and resets properties) have been added.
Sean Anderson [Wed, 24 Jun 2020 10:41:22 +0000 (06:41 -0400)]
riscv: Enable cpu clock if it is present
The cpu clock is probably already enabled if we are executing code (though
we could be executing from a different core). This patch prevents the cpu
clock or its parents from being disabled.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:21 +0000 (06:41 -0400)]
riscv: Try to get cpu frequency from a "clocks" node if it exists
Instead of always using the "clock-frequency" property to determine cpu
frequency, try using a clock in "clocks" if it exists. This patch also
fixes a bug where there could be spurious higher frequencies if sizeof(u32)
!= sizeof(ulong).
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:20 +0000 (06:41 -0400)]
riscv: Allow use of reset drivers
Currently, one cannot use a reset driver on RISC-V. Follow the MIPS
example, and disable the default reset handler when the sysreset driver is
enabled.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:19 +0000 (06:41 -0400)]
riscv: Add option to support RISC-V privileged spec 1.9
Some older processors (notably the Kendryte K210) use an older version of
the RISC-V privileged specification. The primary changes between the old
and new are in virtual memory, and in the merging of three separate counter
enable CSRs. Using the new CSR on an old processor causes an illegal
instruction exception. This patch adds an option to use the old CSRs
instead of the new one.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:18 +0000 (06:41 -0400)]
riscv: Clean up IPI initialization code
The previous IPI code initialized the device whenever the first call was
made to a riscv_*_ipi function. This made it difficult to determine when
the IPI device was initialized. This patch introduces a new function
riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is
called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions
should be called.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:17 +0000 (06:41 -0400)]
riscv: Clear pending interrupts before enabling IPIs
On some platforms (k210), the previous stage bootloader may have not
cleared pending IPIs before transferring control to U-Boot. This can cause
race conditions, as multiple harts all attempt to initialize the IPI
controller at once. This patch clears IPIs before enabling them, ensuring
that only one hart modifies shared memory at once.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:14 +0000 (06:41 -0400)]
reset: Add generic reset driver
This patch adds a generic reset driver. It is designed to be useful when
one has a register in a regmap which contains bits that reset other
devices. I thought this seemed like a very generic use, so here is a
generic driver. The overall structure has been modeled on the syscon-reboot
driver.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 24 Jun 2020 10:41:13 +0000 (06:41 -0400)]
dm: Fix error handling for dev_read_addr_ptr
dev_read_addr_ptr had different semantics depending on whether OF_LIVE was
enabled. This patch converts both implementations to return NULL on error,
and converts all call sites which check for FDT_ADDR_T_NONE to check for
NULL instead. This patch also removes the call to map_physmem, since we
have dev_remap_addr* for those semantics.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 24 Jun 2020 10:41:12 +0000 (06:41 -0400)]
dm: Add support for simple-pm-bus
This type of bus is used in Linux to designate buses which have power
domains and/or clocks which need to be enabled before their child devices
can be used. Because power domains are automatically enabled before probing
in U-Boot, we just need to enable any clocks present.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 24 Jun 2020 10:41:11 +0000 (06:41 -0400)]
clk: Add K210 clock support
Due to the large number of clocks, I decided to use the CCF. The overall
structure is modeled after the imx code. Clocks parameters are stored in
several arrays, and are then instantiated at run-time. There are some
translation macros (FOOIFY()) which allow for more dense packing.
Signed-off-by: Sean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
Sean Anderson [Wed, 24 Jun 2020 10:41:10 +0000 (06:41 -0400)]
clk: Add a bypass clock for K210
This is a small driver to do a software bypass of a clock if hardware
bypass is not working. I have tried to write this in a generic fashion, so
that it could be potentially broken out of the kendryte code at some future
date. For the K210, it is used to have aclk bypass pll0 and use in0 instead
so that the CPU keeps on working.
Signed-off-by: Sean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
Sean Anderson [Wed, 24 Jun 2020 10:41:09 +0000 (06:41 -0400)]
clk: Add K210 pll support
This pll code is primarily based on the code from the kendryte standalone
sdk in lib/drivers/sysctl.c. k210_pll_calc_config is roughly analogous to
the algorithm used to set the pll frequency, but it has been completely
rewritten to be fixed-point based.
Signed-off-by: Sean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
Sean Anderson [Wed, 24 Jun 2020 10:41:08 +0000 (06:41 -0400)]
clk: Fix clk_get_by_* handling of index
clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean
predicate instead of the index. Other clk_get_by_* functions got the clock
correctly, but passed a predicate instead of the index to clk_get_by_tail.
This could lead to confusing error messages.
Signed-off-by: Sean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
Sean Anderson [Wed, 24 Jun 2020 10:41:07 +0000 (06:41 -0400)]
clk: Check that ops of composite clock components exist before calling
clk_composite_ops was shared between all devices in the composite clock
driver. If one clock had a feature (such as supporting set_parent) which
another clock did not, it could call a null pointer dereference.
This patch does three things
1. It adds null-pointer checks to all composite clock functions.
2. It makes clk_composite_ops const and sets its functions at compile-time.
3. It adds some basic sanity checks to num_parents.
The combined effect of these changes is that any of mux, rate, or gate can
be NULL, and composite clocks will still function normally. Previously, at
least mux had to exist, since clk_composite_get_parent was used to
determine the parent for clk_register.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Lukasz Majewski <lukma@denx.de>
Sean Anderson [Wed, 24 Jun 2020 10:41:06 +0000 (06:41 -0400)]
clk: Always use the supplied struct clk
CCF clocks should always use the struct clock passed to their methods for
extracting the driver-specific clock information struct. Previously, many
functions would use the clk->dev->priv if the device was bound. This could
cause problems with composite clocks. The individual clocks in a composite
clock did not have the ->dev field filled in. This was fine, because the
device-specific clock information would be used. However, since there was
no ->dev, there was no way to get the parent clock. This caused the
recalc_rate method of the CCF divider clock to fail. One option would be to
use the clk->priv field to get the composite clock and from there get the
appropriate parent device. However, this would tie the implementation to
the composite clock. In general, different devices should not rely on the
contents of ->priv from another device.
The simple solution to this problem is to just always use the supplied
struct clock. The composite clock now fills in the ->dev pointer of its
child clocks. This allows child clocks to make calls like clk_get_parent()
without issue.
imx avoided the above problem by using a custom get_rate function with
composite clocks.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Lukasz Majewski <lukma@denx.de>
Tom Rini [Tue, 30 Jun 2020 19:03:25 +0000 (15:03 -0400)]
Merge branch '2020-06-30-minor-TI-board-updates' into next
- Minor updates to some platforms I am the listed maintainer of.
Notably this removes the ti814x_evm which stopped building with the PXA
MMC migration series (oops) but hasn't been functional in some time.
Tom Rini [Mon, 25 May 2020 18:34:06 +0000 (14:34 -0400)]
ti814x: Remove platform
The TI814x (DM814x) platform is rather old and in need of a lot of
migration work. As much of that work is well past the deadline, remove
this platform.
Tom Rini [Mon, 25 May 2020 18:30:36 +0000 (14:30 -0400)]
ti816x_evm: Enable DM_MMC
This platform is already using DM in general and the MMC controller is
the early generation of what is compatible with "ti,omap4-hsmmc" so
enable DM_MMC (which in turn gets BLK enabled).
Tom Rini [Tue, 30 Jun 2020 15:43:18 +0000 (11:43 -0400)]
Merge tag 'mips-pull-2020-06-29' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips into next
- net: pcnet: cleanup and add DM support
- Makefile: add rule to build an endian-swapped U-Boot image
used by MIPS Malta EL variants
- CI: add Qemu tests for MIPS Malta
The Qemu Malta machine expects the firmware in Big-Endian byte order.
Therefore the Little-Endian variants of the Malta board needs to
be byte swapped.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This rule generates an u-boot binary file where the byte endianness
is swapped. This will be used by the MIPS Malta Little-Endian variants
to be able to boot with Qemu. The Qemu Malta Machine expects the
firmware in Big-Endian order.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Marek Vasut [Sun, 17 May 2020 16:24:25 +0000 (18:24 +0200)]
net: pcnet: Add Kconfig entries
Add Kconfig entries for the pcnet driver and convert MIPS malta
to use those.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 17 May 2020 16:24:24 +0000 (18:24 +0200)]
net: pcnet: Add DM support
With all the changes in place, add support for DM into the
pcnet driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 17 May 2020 16:24:23 +0000 (18:24 +0200)]
net: pcnet: Split common and non-DM functions
Pull the common parts of functions out so they can be reused by both
DM and non-DM code paths. The recv() function had to be reworked to
fit into this scheme and this means it now only receives one packet
at a time instead of spinning in an endless loop.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 17 May 2020 16:24:22 +0000 (18:24 +0200)]
net: pcnet: Wrap name and enetaddr into private data
Instead of using the non-DM-only name and enetaddr in struct eth_device,
add pointers into the private data which can either point to that non-DM
name or a DM one later on.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 17 May 2020 16:24:21 +0000 (18:24 +0200)]
net: pcnet: Wrap iobase into private data
Instead of using the non-DM-only iobase in struct eth_device, add
one into the private data to make DM and non-DM operation possible.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 17 May 2020 16:24:20 +0000 (18:24 +0200)]
net: pcnet: Pass private data through dev->priv
Get rid of the global point to private data, and rather pass it
thought dev->priv. Also remove the unnecessary check for lp being
non-NULL, since it is always NULL at this point.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 17 May 2020 16:24:19 +0000 (18:24 +0200)]
net: pcnet: Wrap devbusfn into private data
Instead of using eth_device priv for this PCI devbusfn, free it
so it could be used for driver private data, and wrap devbusfn
into those driver private data.
Note that using the name dev for the variable is a trick left for
later, when DM support is in place, so dm_pci_virt_to_mem() can be
used with minimal ifdeffery.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 17 May 2020 16:24:18 +0000 (18:24 +0200)]
net: pcnet: Drop useless forward declarations
Remove those as they are not needed anymore.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 17 May 2020 16:24:17 +0000 (18:24 +0200)]
net: pcnet: Move initialize function at the end
Move the function at the end of the driver, so we could drop
various forward declarations later. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 17 May 2020 16:24:16 +0000 (18:24 +0200)]
net: pcnet: Move private data allocation to initialize
The private data allocation does not have to be done every time the
NIC is initialized at run time, move the allocation to initialize
function, which means it will be done only once when the driver
starts.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 17 May 2020 16:24:15 +0000 (18:24 +0200)]
net: pcnet: Replace memset+malloc with calloc
This combination of functions can be replaced with calloc(),
make it so.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 17 May 2020 16:24:14 +0000 (18:24 +0200)]
net: pcnet: Simplify private data allocation
The current code is horribly complex. Both the RX and TX buffer
descriptors are 16 bytes in size, the init block is 32 bytes in
size, so simplify the code such that the entire private data of
the driver are allocated cache aligned and the RX and TX buffer
descriptors are part of the private data.
This removes multiple malloc calls and cache flushes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 17 May 2020 16:24:13 +0000 (18:24 +0200)]
net: pcnet: Use PCI_DEVICE() to define PCI device compat list
Use this macro to fully fill the PCI device ID table. This is mandatory
for the DM PCI support, which checks all the fields.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 17 May 2020 16:24:12 +0000 (18:24 +0200)]
net: pcnet: Drop PCNET_HAS_PROM
All of one PCNET users has this option set, make this default
and drop this config option.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 17 May 2020 16:24:11 +0000 (18:24 +0200)]
net: pcnet: Drop typedef struct pcnet_priv_t
Use struct pcnet_priv all over the place instead.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Mon, 29 Jun 2020 19:58:38 +0000 (15:58 -0400)]
Merge branch '2020-06-26-more-Kconfig-migration' into next
- Bring in the first pass at cleaning up config headers that reference
symbols that already have Kconfig symbols.
- In order to do that, bring in the small series that adds
CONFIG_SPL_DM_SPI_FLASH and makes more use of CONFIG_$(SPL_TPL_)DM_SPI
in order to allow for disabling those features in SPL stuff but using
them in full U-Boot
Lukasz Majewski [Thu, 4 Jun 2020 15:11:52 +0000 (23:11 +0800)]
spi: Move DM_SPI_FLASH and SPI_FLASH_DATAFLASH to Kconfig (for ls1021aXXX)
This patch moves the CONFIG_DM_SPI_FLASH and CONFIG_SPI_FLASH_DATAFLASH
to be defined in Kconfig, not in board specific header file
(include/configs/<board>.h).
Before this change the CONFIG_DM_SPI_FLASH was not set in .config (so it
was not possible to use CONFIG_IS_ENABLED(DM_SPI_FLASH) in SPI DM/DTS
converted drivers), but it was set in u-boot.cfg file.
Lukasz Majewski [Thu, 4 Jun 2020 15:11:53 +0000 (23:11 +0800)]
spi: Convert CONFIG_DM_SPI* to CONFIG_$(SPL_TPL_)DM_SPI*
This change allows more fine tuning of driver model based SPI support in
SPL and TPL. It is now possible to explicitly enable/disable the DM_SPI
support in SPL and TPL via Kconfig option.
Before this change it was necessary to use:
/* SPI Flash Configs */
#if defined(CONFIG_SPL_BUILD)
#undef CONFIG_DM_SPI
#undef CONFIG_DM_SPI_FLASH
#undef CONFIG_SPI_FLASH_MTD
#endif
in the ./include/configs/<board>.h, which is error prone and shall be
avoided when we strive to switch to Kconfig.
The goal of this patch:
Provide distinction for DM_SPI support in both U-Boot proper and SPL (TPL).
Valid use case is when U-Boot proper wants to use DM_SPI, but SPL must
still support non DM driver.
Another use case is the conversion of non DM/DTS SPI driver to support
DM/DTS. When such driver needs to work in both SPL and U-Boot proper, the
distinction is needed in Kconfig (also if SPL version of the driver
supports OF_PLATDATA).
In the end of the day one would have to support following use cases (in
single driver file - e.g. mxs_spi.c):
- U-Boot proper driver supporting DT/DTS
- U-Boot proper driver without DT/DTS support (deprecated)
- SPL driver without DT/DTS support
- SPL (and TPL) driver with DT/DTS (when the SoC has enough resources to
run full blown DT/DTS)
- SPL driver with DT/DTS and SPL_OF_PLATDATA (when one have constrained
environment with no fitImage and OF_LIBFDT support).
Some boards do require SPI support (with DM) in SPL (TPL) and some only
have DM_SPI{_FLASH} defined to allow compiling SPL.
This patch converts #ifdef CONFIG_DM_SPI* to #if CONFIG_IS_ENABLED(DM_SPI)
and provides corresponding defines in Kconfig.
Signed-off-by: Lukasz Majewski <lukma@denx.de> Tested-by: Adam Ford <aford173@gmail.com> #da850-evm Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[trini: Fixup a few platforms] Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 26 Jun 2020 21:40:06 +0000 (17:40 -0400)]
x86: Don't build some unused objects in TPL
In the future if we have separate symbols for DM_SPI_FLASH and
SPL_DM_SPI_FLASH we will not always have function declarations available
for some DM calls. This in turn leads to build warnings but not
failures as the code isn't used and is discarded at link time.
Restructure things to not build code we won't use for TPL anyways.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sun, 28 Jun 2020 14:12:25 +0000 (10:12 -0400)]
Merge tag 'fixes-for-v2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-video
- fix logo on mx6ul_14x14_evk with DM_VIDEO enabled
- fix banner string overwriting the logo on small displays
- fix splash warning when building for ARM64
- fix STM32 DSI driver to probe only on supported hardware
- fix memory corruption with DSI panel drivers
Ye Li [Wed, 10 Jun 2020 09:52:22 +0000 (02:52 -0700)]
splash: Fix build warning on 64 bits CPU
Get below warning on ARM64 platform, because the bmp_load_addr
is defined to u32.
common/splash.c: In function ‘splash_video_logo_load’:
common/splash.c:74:9: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
74 | memcpy((void *)bmp_load_addr, bmp_logo_bitmap,
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # bpi-m1+, bpi-m64
Ye Li [Wed, 10 Jun 2020 09:52:21 +0000 (02:52 -0700)]
video: vidconsole: avoid multiple lines overwrite logo
Fix the bug that multiple lines wraps to overwrite logo bmp
display.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # bpi-m1+, bpi-m64
Ye Li [Wed, 10 Jun 2020 09:52:23 +0000 (02:52 -0700)]
video: bmp: support 8bits BMP drawing on 24/32 bpp framebuffer
Update video bmp code so that we can display 8 bits logo on
24 or 32 bpp framebuffer.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # bpi-m1+, bpi-m64
The commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock
driver") changed ARM clock from 600MHz to 1600MHz. It made boot
unstable due to the fact that PMIC at the start generates insufficient
voltage for operation. See also: commit f4f57c58b589 ("rockchip:
rk3188: Setup the armclk in spl").
Fixes commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock
driver").
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Tue, 16 Jun 2020 23:06:29 +0000 (19:06 -0400)]
spi: Enable missing CONFIG_SPL_DM_SPI support
Due to how the Makefile logic is we currently get DM_SPI support in SPL
enabled by having DM_SPI enabled for full U-Boot but not having
CONFIG_SPL_DM_SPI set. Add this missing option to boards that were
inadvertently making use of it.
Cc: Adam Ford <aford173@gmail.com> Cc: Akash Gajjar <akash@openedev.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Andy Yan <andy.yan@rock-chips.com> Cc: Anup Patel <anup.patel@wdc.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Chee Hong Ang <chee.hong.ang@intel.com> Cc: Chin-Liang See <clsee@altera.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Klaus Goger <klaus.goger@theobroma-systems.com> Cc: Levin Du <djw@t-chip.com.cn> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Luca Ceresoli <luca@lucaceresoli.net> Cc: Marek Vasut <marex@denx.de> Cc: Michal Simek <monstr@monstr.eu> Cc: Mike Looijmans <mike.looijmans@topic.nl> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Pavel Machek <pavel@denx.de> Cc: Peter Robinson <pbrobinson@gmail.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Suniel Mahesh <sunil@amarulasolutions.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Wolfgang Grandegger <wg@aries-embedded.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
projects / u-boot.git / log