]> git.dujemihanovic.xyz Git - u-boot.git/log
u-boot.git
4 years agoMerge tag 'u-boot-imx-20200108' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Tom Rini [Wed, 8 Jan 2020 20:24:50 +0000 (15:24 -0500)]
Merge tag 'u-boot-imx-20200108' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

---------------------------------------------------------------------
Add i.MX8MP SoC and EVK board
Update README for i.MX8MN EVK and fix mmc env
Add pca9450 driver
--------------------------------------------------------------------

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/634211885

4 years agoMerge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Wed, 8 Jan 2020 20:23:49 +0000 (15:23 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga

4 years agoMerge tag 'u-boot-amlogic-20200108' of https://gitlab.denx.de/u-boot/custodians/u...
Tom Rini [Wed, 8 Jan 2020 20:23:37 +0000 (15:23 -0500)]
Merge tag 'u-boot-amlogic-20200108' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- Khadas VIM3L based on Amlogic S905D3 support
- Various fixups for amlogic boards
- Unnecessary header includes drop into video/meson

4 years agoMerge branch '2020-01-07-master-imports'
Tom Rini [Wed, 8 Jan 2020 20:08:34 +0000 (15:08 -0500)]
Merge branch '2020-01-07-master-imports'

- DT overlay support in FIT images in SPL
- remoteproc update
- Assorted SATA fixes
- Other assorted fixes

4 years agoata: fsl_sata: Continue probing other sata port when failed current port.
Peng Ma [Wed, 4 Dec 2019 10:36:45 +0000 (10:36 +0000)]
ata: fsl_sata: Continue probing other sata port when failed current port.

In the initialization of sata driver, we want to initialize all port
 probes, Therefore, any detection failure between of them should continue
 initialization by skipping the current port instead of exit.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
4 years agoata: sata_sil: Continue probing other sata port when failed current port.
Peng Ma [Wed, 4 Dec 2019 10:36:42 +0000 (10:36 +0000)]
ata: sata_sil: Continue probing other sata port when failed current port.

In the initialization of sata driver, we want to initialize all port
 probes, Therefore, any detection failure between of them should continue
 initialization by skipping the current port instead of exit.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
4 years agotreewide: Remove CONFIG_SYS_UBOOT_START from configs board files
Patrice Chotard [Fri, 6 Dec 2019 14:01:49 +0000 (15:01 +0100)]
treewide: Remove CONFIG_SYS_UBOOT_START from configs board files

As previous CONFIG_SYS_UBOOT_START is now set by default to
CONFIG_SYS_TEXT_BASE when not defined, CONFIG_SYS_UBOOT_START
can be removed from include/configs board files.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
4 years agoMakefile: Fix CONFIG_SYS_UBOOT_START default value
Patrice Chotard [Fri, 6 Dec 2019 14:01:48 +0000 (15:01 +0100)]
Makefile: Fix CONFIG_SYS_UBOOT_START default value

This patches restores boot on boards which rely on
CONFIG_SYS_UBOOT_START equal to CONFIG_SYS_TEXT_BASE when using SPL

Fixes: d3e97b53c1f2 ("spl: fix entry_point equal to load_addr")
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agocmd/Kconfig: Add more dependencies to OSE bootm support
Tom Rini [Thu, 5 Dec 2019 23:46:11 +0000 (18:46 -0500)]
cmd/Kconfig: Add more dependencies to OSE bootm support

Per Enea OSE documentation, it supports some classes of ARM, PowerPC and
X86.  Limit the option to those platforms.

Signed-off-by: Tom Rini <trini@konsulko.com>
4 years agoimx: imx8mn: enable CONFIG_CMD_ERASEENV
Peng Fan [Mon, 6 Jan 2020 08:19:34 +0000 (16:19 +0800)]
imx: imx8mn: enable CONFIG_CMD_ERASEENV

enable CONFIG_CMD_ERASEENV to make it easy to erase env.
Use savedefconfig to generate new defconfig.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx: imx8mn_evk: add board_mmc_get_env_dev
Peng Fan [Mon, 6 Jan 2020 08:16:32 +0000 (16:16 +0800)]
imx: imx8mn_evk: add board_mmc_get_env_dev

Add board_mmc_get_env_dev, otherwise,
Loading Environment from MMC...
MMC Device 0 not found
*** Warning - No MMC card found, using default environment

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx8mn: evk: add README
Peng Fan [Mon, 6 Jan 2020 07:38:17 +0000 (15:38 +0800)]
imx8mn: evk: add README

Add a README for users to build a workable image.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx: add i.MX8MP EVK board
Peng Fan [Mon, 30 Dec 2019 09:46:21 +0000 (17:46 +0800)]
imx: add i.MX8MP EVK board

Add basic i.MX8MP EVK board support

U-Boot SPL 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800)
power_pca9450b_init
DDRINFO: start DRAM init
DDRINFO:ddrphy calibration done
DDRINFO: ddrmix config done
Normal Boot
Failed to find clock node. Check device tree
WDT:   Not found!
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0

U-Boot 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800)

CPU:   Freescale i.MX8MP rev1.0 at 1000 MHz
Reset cause: POR
Model: NXP i.MX8MPlus EVK board
DRAM:  6 GiB
MMC:   FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Net:   No ethernet found.
Hit any key to stop autoboot:  0
u-boot=> mmc list
FSL_SDHC: 1 (SD)
FSL_SDHC: 2

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx: imx8m: add imximage-8mp-lpddr4.cfg
Peng Fan [Mon, 30 Dec 2019 09:40:38 +0000 (17:40 +0800)]
imx: imx8m: add imximage-8mp-lpddr4.cfg

Add imximage-8mp-lpddr4.cfg for imximage usage, almost same
as i.MX8MN ddr4 cfg, but with different ddr firmware

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoclk: imx: add i.MX8MP clk driver
Peng Fan [Mon, 30 Dec 2019 09:39:18 +0000 (17:39 +0800)]
clk: imx: add i.MX8MP clk driver

Add i.MX8MP clk driver for i.MX8MP CLK driver model usage

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoclk: imx: add imx_clk_mux2_flags
Peng Fan [Mon, 30 Dec 2019 08:56:25 +0000 (16:56 +0800)]
clk: imx: add imx_clk_mux2_flags

Add imx_clk_mux2_flags which will be used by i.MX8MP

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx: imx8m: only support non-dm code in clock_imx8mm.c
Peng Fan [Mon, 30 Dec 2019 08:52:30 +0000 (16:52 +0800)]
imx: imx8m: only support non-dm code in clock_imx8mm.c

The drivers/clk/imx/*.c are used for CLK dm case, the
clock_imx8mm.c is used for non CLK dm case, let's split
it. Sometimes it is hard to enable CLK dm in SPL stage,
considering code size, malloc size requirement, the splittion
will make it easy to use non CLK dm in SPL stage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx: Kconfig: make SPL_IMX_ROMAPI_LOADADDR visible to i.MX8MP
Peng Fan [Mon, 30 Dec 2019 08:44:48 +0000 (16:44 +0800)]
imx: Kconfig: make SPL_IMX_ROMAPI_LOADADDR visible to i.MX8MP

i.MX8MP ROM support ROMAPI as i.MX8MN, so make
SPL_IMX_ROMAPI_LOADADDR visible to i.MX8MP

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx: add i.MX8MP PE property
Peng Fan [Mon, 30 Dec 2019 08:43:48 +0000 (16:43 +0800)]
imx: add i.MX8MP PE property

i.MX8MP does not have LVTTL, it has a PE property

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx: imx8mp: add pin header file
Peng Fan [Mon, 30 Dec 2019 08:40:57 +0000 (16:40 +0800)]
imx: imx8mp: add pin header file

Add pin header file for i.MX8MP

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agopower: Add new PMIC PCA9450 driver
Ye Li [Tue, 15 Oct 2019 09:15:18 +0000 (02:15 -0700)]
power: Add new PMIC PCA9450 driver

PCA9450 PMIC series is used to support iMX8MM (PCA9450A) and
iMX8MN (PCA9450B). Add the PMIC driver for both PCA9450A and PCA9450B.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoarm: dts: freescale: Add i.MX8MP dtsi support
Peng Fan [Mon, 30 Dec 2019 02:03:44 +0000 (10:03 +0800)]
arm: dts: freescale: Add i.MX8MP dtsi support

The i.MX8M Plus Media Applications Processor is part of the growing
mScale family targeting the consumer and industrial market. It brings
an effective Machine Learning and AI accelerator that enables a new
class of applications. It is built in Samsung 14LPP to achieve both
high performance and low power consumption and relies on a powerful
fully coherent core complex based on a quad core ARM Cortex-A53 cluster
and Cortex-M7 low-power coprocessor, audio digital signal processor,
machine learning and graphics accelerators.

Add the basic dtsi support for i.MX8MP.

Patch from Anson Huang for Kernel
https://patchwork.kernel.org/patch/11310915/

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoddr: imx8m: Add DRAM PLL to generate 1000Mhz output
Peng Fan [Mon, 30 Dec 2019 01:58:52 +0000 (09:58 +0800)]
ddr: imx8m: Add DRAM PLL to generate 1000Mhz output

We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agomxc_ocotp: support i.MX8MP
Peng Fan [Tue, 24 Dec 2019 03:26:41 +0000 (11:26 +0800)]
mxc_ocotp: support i.MX8MP

i.MX8MP use similar ocotp as i.MX8MN, but has changed fuse banks
and ctrl register bit definitions, so update to reflect that.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agopinctrl: imx8m: support i.MX8MP
Peng Fan [Mon, 30 Dec 2019 01:52:15 +0000 (09:52 +0800)]
pinctrl: imx8m: support i.MX8MP

Add i.MX8MP compatible to let the pinctrl driver could support
i.MX8MP.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx: imx8m: add 1GHz fracpll entry
Peng Fan [Fri, 27 Dec 2019 03:40:55 +0000 (11:40 +0800)]
imx: imx8m: add 1GHz fracpll entry

4000MTS DDR needs 1GHz fracpll, so add the entry

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx: imx8mp: add basic clock
Peng Fan [Fri, 27 Dec 2019 03:39:15 +0000 (11:39 +0800)]
imx: imx8mp: add basic clock

i.MX8MP has similar architecture as i.MX8MN, but it has different
clk root and index, so add that to make i.MX8MP could use
the non-dm clock driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoarm: dts: add i.MX8MP pinfunc header
Peng Fan [Fri, 27 Dec 2019 02:38:05 +0000 (10:38 +0800)]
arm: dts: add i.MX8MP pinfunc header

Add i.MX8MP pinfunc header for dts usage

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agodt-bindings: clock: add i.MX8MP clock header
Peng Fan [Fri, 27 Dec 2019 02:37:39 +0000 (10:37 +0800)]
dt-bindings: clock: add i.MX8MP clock header

Add i.MX8MP clock header

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx: spl: support i.MX8MP spl_boot_device
Peng Fan [Fri, 27 Dec 2019 02:27:49 +0000 (10:27 +0800)]
imx: spl: support i.MX8MP spl_boot_device

i.MX8MP follows i.MX8MN, so just let it use spl_board_boot_device

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx: imx8m: add Kconfig entry for i.MX8MP
Peng Fan [Fri, 27 Dec 2019 02:24:54 +0000 (10:24 +0800)]
imx: imx8m: add Kconfig entry for i.MX8MP

Add Kconfig entry for i.MX8MP

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx: cpu: enlarge bit mask to 0x1FF for cpu type
Peng Fan [Mon, 30 Dec 2019 09:57:10 +0000 (17:57 +0800)]
imx: cpu: enlarge bit mask to 0x1FF for cpu type

i.MX8MP use 0x182 as dummy id, 0xFF is not able the get the highest
bit, so enlarge bit mask to 0x1FF to make it could detect
cpu type correctly

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx8mp: set BYPASS ID SWAP to avoid AXI bus errors
Peng Fan [Fri, 27 Dec 2019 02:19:42 +0000 (10:19 +0800)]
imx8mp: set BYPASS ID SWAP to avoid AXI bus errors

Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to
generated AXI bus errors with TZC380 enabled.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx: get cpu id/type of i.MX8MP
Peng Fan [Fri, 27 Dec 2019 02:14:02 +0000 (10:14 +0800)]
imx: get cpu id/type of i.MX8MP

Support get i.MX8MP cpu id and cpu type

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoimx: imx8mq: handle ESDHC in mxc_get_clock
Peng Fan [Wed, 11 Dec 2019 06:17:12 +0000 (06:17 +0000)]
imx: imx8mq: handle ESDHC in mxc_get_clock

fsl_esdhc_imx driver will call "mxc_get_clock(MXC_ESDHC_CLK +
dev->seq)", however mxc_get_clock wrongly handle MXC_ESDHC_CLK
as root clk and cause sd card could not be detected in U-Boot proper,
as below:
"Loading Environment from MMC... unable to select a mode"

Handle MXC_ESDHC_CLK in mxc_get_clock to fix the issue.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Tested-by: Fabio Estevam <festevam@gmail.com>
4 years agowandboard: Remove repeated PMIC string
Fabio Estevam [Tue, 10 Dec 2019 09:33:00 +0000 (06:33 -0300)]
wandboard: Remove repeated PMIC string

After the conversion to DM_PMIC the following output is seen:

PMIC:  PMIC:  PFUZE100 ID=0x10

Remove the unnecessary PMIC string from the board file to
avoid the repetead string.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
4 years agowandboard: Fix the DM_PMIC conversion
Fabio Estevam [Tue, 10 Dec 2019 09:32:59 +0000 (06:32 -0300)]
wandboard: Fix the DM_PMIC conversion

Commit ec837c82d709 ("imx6: wandboard: convert to DM_PMIC")
caused the following pmic_get() error:

CPU:   Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: POR
DRAM:  2 GiB
PMIC:  pmic_get() ret -19
...

and since the PMIC presence is used to determine the board D1 revision,
the following error is seen when booting a board rev D1:

WARNING: Could not determine dtb to use

and the kernel does not boot at all.

Fix the regression by passing "pfuze100@8" as the correct parameter
to the pmic_get() function in the DM case.

Fixes: ec837c82d709 ("imx6: wandboard: convert to DM_PMIC")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
4 years agobdinfo: show multi_dtb_fit
Heiko Schocher [Sat, 9 Nov 2019 03:56:10 +0000 (04:56 +0100)]
bdinfo: show multi_dtb_fit

if MULTI_DTB_FIT is enabled it is helpful to display
the value of gd->multi_dtb_fit in bdinfo.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agocmd_ut: add a parameter prefix to the function cmd_ut_category
Philippe Reynes [Tue, 17 Dec 2019 18:07:04 +0000 (19:07 +0100)]
cmd_ut: add a parameter prefix to the function cmd_ut_category

There is black magic in the file conftest.py that list
all the test unit. Then, all those test unit are called
in pytest. This call is done with the end of the name
(for example checksum if the full name is bloblist_test_checksum).

The result is that only test for dm are really executed.
by pytest, all others tests are listed but never executed.

This behaviour happens because the dm test unit only check
the end of the name and others tests checks the full name.

To fix this issue, I've added a prefix to the function
cmd_ut_category, and this prefix is removed when looking
for the unit test.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agopower: regulator: support off-on-delay-us
Peng Fan [Mon, 4 Nov 2019 09:27:23 +0000 (09:27 +0000)]
power: regulator: support off-on-delay-us

off-on-delay-us has been supported by Linux, so let's use it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoremoteproc: stm32: load resource table from firmware
Fabien Dessenne [Wed, 30 Oct 2019 13:38:33 +0000 (14:38 +0100)]
remoteproc: stm32: load resource table from firmware

Load the optional resource table from the firmware, and write its
address in the dedicated backup register.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
4 years agostm32mp1: remove copro_state environment variable
Fabien Dessenne [Wed, 30 Oct 2019 13:38:32 +0000 (14:38 +0100)]
stm32mp1: remove copro_state environment variable

Since the coprocessor state is tracked in a backup register, there is
no more need for tracking it in an environment variable : remove it.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
4 years agoremoteproc: stm32: track the coprocessor state in a backup register
Fabien Dessenne [Wed, 30 Oct 2019 13:38:31 +0000 (14:38 +0100)]
remoteproc: stm32: track the coprocessor state in a backup register

Update the dedicated backup register to track the coprocessor state and
rely on that register to compute the .is_running() value (which expects
a return value of 0 -not 1- if the processor is running).

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
4 years agostm32mp1: reset coprocessor status at cold boot
Fabien Dessenne [Wed, 30 Oct 2019 13:38:30 +0000 (14:38 +0100)]
stm32mp1: reset coprocessor status at cold boot

Reset ResourceTableAddress and CoprocessorState at cold boot, preserve
these values at standby wakeup.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
4 years agostm32mp1: declare backup registers for coprocessor
Fabien Dessenne [Wed, 30 Oct 2019 13:38:29 +0000 (14:38 +0100)]
stm32mp1: declare backup registers for coprocessor

Use the backup register #17 as coprocessor resource table address and
backup register #18 as coprocessor state.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
4 years agoremoteproc: elf_loader: Add elf resource table load support
Fabien Dessenne [Wed, 30 Oct 2019 13:38:28 +0000 (14:38 +0100)]
remoteproc: elf_loader: Add elf resource table load support

Add rproc_elf_load_rsc_table(), which searches for a resource table in
an elf64/elf32 image, and if found, copies it to device memory.
Add also the elf32 and elf64 variants of this API.
Add a test for this.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
4 years agospl: fit: Allow the board to tell if more images must be loaded from FIT
Jean-Jacques Hiblot [Tue, 22 Oct 2019 14:39:22 +0000 (16:39 +0200)]
spl: fit: Allow the board to tell if more images must be loaded from FIT

spl_fit_get_image_name() is used to get the names of the images that the
SPL must load from the FIT. It relies on the content of a property present
in the FIT. The list of images is thus statically defined in the FIT.
With this scheme, it quickly becomes hard to manage combinations of more
than a handful of images.
To address this problem, give the board driver code the opportunity to
add to the list of images. The images from the FIT property are loaded
first, and then the board_get_fit_loadable() is called to get more image
names.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agodts: Add support for adding DT overlays in u-boot.img
Jean-Jacques Hiblot [Tue, 22 Oct 2019 14:39:21 +0000 (16:39 +0200)]
dts: Add support for adding DT overlays in u-boot.img

If u-boot.img is a FIT image, CONFIG_OF_OVERLAY_LIST can be used to add
DT overlays to u-boot.img.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoinclude: board: provide empty stubs when the BOARD option is not selected
Jean-Jacques Hiblot [Tue, 22 Oct 2019 14:39:20 +0000 (16:39 +0200)]
include: board: provide empty stubs when the BOARD option is not selected

Useful to avoid #ifdef throughout the code that uses the board driver API.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agodrivers: board: Add get_fit_loadable()
Jean-Jacques Hiblot [Tue, 22 Oct 2019 14:39:19 +0000 (16:39 +0200)]
drivers: board: Add get_fit_loadable()

This function will be used by the SPL to get the names of images to load
from the FIT. This allows to load different images based on runtime HW
detection.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agodrivers: board: Make the board drivers available in SPL
Jean-Jacques Hiblot [Tue, 22 Oct 2019 14:39:18 +0000 (16:39 +0200)]
drivers: board: Make the board drivers available in SPL

Make the board driver available in the SPL too. The board driver is a way
to provide useful information about the board and that can be useful in
the SPL too.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agospl: fit: constify the output parameter of spl_fit_get_image_name()
Jean-Jacques Hiblot [Tue, 22 Oct 2019 14:39:17 +0000 (16:39 +0200)]
spl: fit: constify the output parameter of spl_fit_get_image_name()

There is no need for it to be non-constant. Making it constant, allows to
return constant string without warning.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoMakefile.lib: include /__symbols__ in dtb if SPL_LOAD_FIT_APPLY_OVERLAY is enabled
Jean-Jacques Hiblot [Tue, 22 Oct 2019 14:39:16 +0000 (16:39 +0200)]
Makefile.lib: include /__symbols__ in dtb if SPL_LOAD_FIT_APPLY_OVERLAY is enabled

In order to apply an overlay to a DTB. The DTB must have been generated
with the option '-@'.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agospl: fit: be more verbose when an error occurs when applying the overlays
Jean-Jacques Hiblot [Tue, 22 Oct 2019 14:39:15 +0000 (16:39 +0200)]
spl: fit: be more verbose when an error occurs when applying the overlays

There are many ways the overlay application can fail.
2 of them are probably the most common:
- the application itself failed. Usually this is comes from an unresolved
  reference
- DTBO not available in FIT (could be because of a typo)

In both case it is good to be more explicit about the error and at least
show which overlay is failing.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agospl: fit: Do not fail immediately if an overlay is not available
Jean-Jacques Hiblot [Tue, 22 Oct 2019 14:39:14 +0000 (16:39 +0200)]
spl: fit: Do not fail immediately if an overlay is not available

If one overlay that must be applied cannot be found in the FIT, the current
implementation stops applying the overlays. Let's make it skip only the
failing overlay instead.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agospl: fit: allocate a temporary buffer to load the overlays
Jean-Jacques Hiblot [Tue, 22 Oct 2019 14:39:13 +0000 (16:39 +0200)]
spl: fit: allocate a temporary buffer to load the overlays

If the node describing an overlay does not specify a load address, it will
be loaded at the address previously used.
Fixing it by allocating a temporary buffer that will be used as a
default load address. By default, the size of the buffer is 64kB which
should be plenty for most use cases.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agospl: fit: Make room in the FDT before applying overlays
Jean-Jacques Hiblot [Tue, 22 Oct 2019 14:39:12 +0000 (16:39 +0200)]
spl: fit: Make room in the FDT before applying overlays

Make room in the FDT before applying the overlay, otherwise it may fail if
the overlay is big. As the exact added size is not known in advance, just
add the size of the overlay.
Move after the end of the application of the overlays, the resize  of the
FDT for the injection of the details on the loadables.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agospl: fit: Add support for applying DT overlay
Michal Simek [Tue, 22 Oct 2019 14:39:11 +0000 (16:39 +0200)]
spl: fit: Add support for applying DT overlay

doc/uImage.FIT/overlay-fdt-boot.txt is describing how to create FIT
image with DT overlays in it.
Add support for this feature to SPL.

Here is the ZynqMP fragment where dtb points to full DT and dtbo is
overlay which should be applied on the top of dtb.
config {
        description = "ATF with full u-boot overlay";
        firmware = "atf";
        loadables = "uboot";
        fdt = "dtb", "dtbo";
};

The whole feature depends on OF_LIBFDT_OVERLAY which is adding +4kB code
and 0 for platforms which are not enabling this feature.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agospl: fit: don't load the firmware twice
Jean-Jacques Hiblot [Tue, 22 Oct 2019 14:39:10 +0000 (16:39 +0200)]
spl: fit: don't load the firmware twice

When u-boot.img is a FIT image generated automatically by mkimage, the
configuration node has the following structure:
conf-1 {
   description = "k3-am654-base-board";
   firmware = "firmware-1";
   loadables = "firmware-1";
   fdt = "fdt-1";
};

The firmware is referenced twice. Once by the 'firmware' property and
once by the 'loadables' property. Currently this result in the firmware
being loaded twice. This is not a big problem but has an impact on the
boot time.
Fixing it by not loading a loadable image if it is also the firmware image.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
4 years agotools: dumpimage: Fall-though to print usage for help command
Andrew F. Davis [Tue, 17 Sep 2019 21:09:35 +0000 (17:09 -0400)]
tools: dumpimage: Fall-though to print usage for help command

This has the same result but some compilers will warn about this
fall-through if there are statements as part of the label block.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
4 years agotools: fit_image: Use fit_image_get_data_and_size for getting offset/size
Andrew F. Davis [Tue, 17 Sep 2019 21:09:34 +0000 (17:09 -0400)]
tools: fit_image: Use fit_image_get_data_and_size for getting offset/size

This is very similar to fit_image_get_data but has the benefit of working
on FIT images with external data unlike fit_image_get_data. This is
useful for extracting sub-images from type of FIT image as this would
previously just silently fail. Add an error message also so if this
still fails it is easier to find out why.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
4 years agotools: dumpimage: Provide more feedback on internal errors
Andrew F. Davis [Tue, 17 Sep 2019 21:09:33 +0000 (17:09 -0400)]
tools: dumpimage: Provide more feedback on internal errors

The dumpimage utility errors out in a number of places without providing
sufficient feedback to allow the user to easily determine what has gone
wrong. Add additional error messages to make the cause of the failure
more obvious.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
4 years agoboard: amlogic: select PWRSEQ for all amlogic platform
Anand Moon [Thu, 26 Dec 2019 11:33:53 +0000 (11:33 +0000)]
board: amlogic: select PWRSEQ for all amlogic platform

commit a10388dc6982 ("mmc: meson-gx: add support for mmc-pwrseq-emmc")
introduce CONFIG_PWRSEQ for power sequence for eMMC module on
amlogic platform, so enable this to all amlogic boards.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agoconfigs: meson64: enable GIC support for G12A/G12B
Anand Moon [Thu, 26 Dec 2019 11:33:52 +0000 (11:33 +0000)]
configs: meson64: enable GIC support for G12A/G12B

Enable GIC support for G12A/G12B platform.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agoboards: amlogic: add Khadas VIM3L support
Christian Hewitt [Wed, 11 Dec 2019 09:20:54 +0000 (13:20 +0400)]
boards: amlogic: add Khadas VIM3L support

Khadas VIM3L uses the same board layout as VIM3, but with an S905D3 chip
instead of A311D. Board config is derived from khadas-vim3_defconfig and
sei610_defconfig. README is based on README.khadas-vim3; the difference
is that VIM3L uses FIP files from the g12a folder in vendor sources not
the g12b folder.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: added vim3l readme into w400 MAINTAINERS]

4 years agoMerge tag 'u-boot-imx-20200107' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Tom Rini [Tue, 7 Jan 2020 13:45:43 +0000 (08:45 -0500)]
Merge tag 'u-boot-imx-20200107' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

New for 2020.04
---------------

- New boards
Embedded Artists COM board
Xea Board
- Switch to DM:
Aristainetos boards
Toradex colibri (DM_ETH)
iCubox
GE bx50v3
mx7dsabre (DM_ETH)
cx9020
- New features:
Bootaux with elf files
Default SYS_THUMB_BUILD for i.MX6/7
- Fixes:
DHCOM i.MX6 PDK
Engicam
i.MX8M tools (imx8m_image)

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664

4 years agoMerge tag 'u-boot-atmel-2020.04-a' of https://gitlab.denx.de/u-boot/custodians/u...
Tom Rini [Tue, 7 Jan 2020 13:44:56 +0000 (08:44 -0500)]
Merge tag 'u-boot-atmel-2020.04-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

First set of u-boot-atmel features for 2020.04 cycle

This feature set is a patch series from Tudor Ambarus which includes
parsing of the spi flash SFDP parser for SST flashes, and using those
tables to retrieve unique saved per device MAC address. This is then
used as base mac address on the SAMA5D2 Wireless SOM EK board.

4 years agoddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access
Thor Thayer [Fri, 6 Dec 2019 19:47:32 +0000 (13:47 -0600)]
ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access

The ECC registers in the SDRAM HMC Adapter should always
be accessible (both when ECC is enabled and disabled).
Currently, the registers are accessible only when ECC is enabled.

The ECC Enabled bit is used to determine the status of
ECC by later OSes so always allow access.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: stratix10: Enable SMMU access
Thor Thayer [Fri, 6 Dec 2019 19:47:31 +0000 (13:47 -0600)]
arm: socfpga: stratix10: Enable SMMU access

Enable TCU access through the Stratix10 CCU so that the
SMMU can access the SDRAM.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoconfigs: socfpga: fix building Stratix10 and Agilex
Simon Goldschmidt [Thu, 12 Dec 2019 11:29:52 +0000 (12:29 +0100)]
configs: socfpga: fix building Stratix10 and Agilex

This fixes a merge error that accidentally left CONFIG_MTD_DEVICE
active by removing it from the config file.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: socfpga: agilex: Enable Agilex SoC build
Ley Foon Tan [Wed, 27 Nov 2019 07:55:32 +0000 (15:55 +0800)]
arm: socfpga: agilex: Enable Agilex SoC build

Add build support for Agilex SoC.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoconfigs: socfpga: Move Stratix10 and Agilex common CONFIGs
Ley Foon Tan [Wed, 27 Nov 2019 07:55:31 +0000 (15:55 +0800)]
configs: socfpga: Move Stratix10 and Agilex common CONFIGs

Move Stratix10 and Agilex common CONFIGs to socfpga_soc64_common.h.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: dts: agilex: Add base dtsi and devkit dts
Ley Foon Tan [Wed, 27 Nov 2019 07:55:30 +0000 (15:55 +0800)]
arm: dts: agilex: Add base dtsi and devkit dts

Add device tree files for Agilex SoC platform.

socfpga_agilex-u-boot.dtsi and socfpga_agilex_socdk-u-boot.dts contains
Uboot specific DT properties.

socfpga_agilex.dtsi and socfpga_agilex_socdk.dts are from Linux
(kernel/git/dinguyen/linux.git, commit 6f0bf971bacacc)

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: socfpga: agilex: Add SPL for Agilex SoC
Ley Foon Tan [Wed, 27 Nov 2019 07:55:29 +0000 (15:55 +0800)]
arm: socfpga: agilex: Add SPL for Agilex SoC

Add SPL support for Agilex SoC.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoboard: intel: agilex: Add socdk board support for Intel Agilex SoC
Ley Foon Tan [Wed, 27 Nov 2019 07:55:28 +0000 (15:55 +0800)]
board: intel: agilex: Add socdk board support for Intel Agilex SoC

Add socdk board support for Intel Agilex SoC

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoddr: altera: agilex: Add SDRAM driver for Agilex
Ley Foon Tan [Wed, 27 Nov 2019 07:55:27 +0000 (15:55 +0800)]
ddr: altera: agilex: Add SDRAM driver for Agilex

Add SDRAM driver for Agilex SoC.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoddr: altera: Restructure Stratix 10 SDRAM driver
Ley Foon Tan [Wed, 27 Nov 2019 07:55:26 +0000 (15:55 +0800)]
ddr: altera: Restructure Stratix 10 SDRAM driver

Restructure Stratix 10 SDRAM driver. Move common code to separate
file, in preparation to support SDRAM driver for Agilex.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: agilex: Add clock handoff offset for Agilex
Ley Foon Tan [Wed, 27 Nov 2019 07:55:25 +0000 (15:55 +0800)]
arm: agilex: Add clock handoff offset for Agilex

Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agocache: Add Arteris Ncore cache coherent unit driver
Ley Foon Tan [Wed, 27 Nov 2019 07:55:24 +0000 (15:55 +0800)]
cache: Add Arteris Ncore cache coherent unit driver

Add Cache Coherency Unit (CCU) driver.
CCU is to ensures consistency of shared data between multi masters
in the system.

Driver initializes CCU's directories and coherency agent
interfaces in CCU IP.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: socfpga: agilex: Add clock wrapper functions
Ley Foon Tan [Wed, 27 Nov 2019 07:55:23 +0000 (15:55 +0800)]
arm: socfpga: agilex: Add clock wrapper functions

Add clock wrapper functions call to clock DM functions to get clock
frequency and used in cm_print_clock_quick_summary().

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoclk: agilex: Add clock driver for Agilex
Ley Foon Tan [Wed, 27 Nov 2019 07:55:22 +0000 (15:55 +0800)]
clk: agilex: Add clock driver for Agilex

Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz
Ley Foon Tan [Wed, 27 Nov 2019 07:55:21 +0000 (15:55 +0800)]
arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz

CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz.
Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: socfpga: Move Stratix10 and Agilex clock manager common code
Ley Foon Tan [Wed, 27 Nov 2019 07:55:20 +0000 (15:55 +0800)]
arm: socfpga: Move Stratix10 and Agilex clock manager common code

Move Stratix10 and Agilex clock manager common code to new header file.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: socfpga: agilex: Add system manager support
Ley Foon Tan [Wed, 27 Nov 2019 07:55:19 +0000 (15:55 +0800)]
arm: socfpga: agilex: Add system manager support

Add system manager support for Agilex.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: socfpga: Move Stratix10 and Agilex system manager common code
Ley Foon Tan [Wed, 27 Nov 2019 07:55:18 +0000 (15:55 +0800)]
arm: socfpga: Move Stratix10 and Agilex system manager common code

Move Stratix10 and Agilex system manager common code to
system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: socfpga: agilex: Add reset manager support
Ley Foon Tan [Wed, 27 Nov 2019 07:55:17 +0000 (15:55 +0800)]
arm: socfpga: agilex: Add reset manager support

Add reset manager support for Agilex.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: socfpga: Move Stratix10 and Agilex reset manager common code
Ley Foon Tan [Wed, 27 Nov 2019 07:55:16 +0000 (15:55 +0800)]
arm: socfpga: Move Stratix10 and Agilex reset manager common code

Move Stratix10 and Agilex reset manager common code to
reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*.

Remove unused RSTMGR_XXX defines.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: socfpga: Move firewall code to firewall file
Ley Foon Tan [Wed, 27 Nov 2019 07:55:15 +0000 (15:55 +0800)]
arm: socfpga: Move firewall code to firewall file

Move firewall related code to new firewall.c, to share
code in Stratix 10 and Agilex.

SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC
to allow DMA transfer to OCRAM.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: socfpga: agilex: Add base address for Intel Agilex SoC
Ley Foon Tan [Wed, 27 Nov 2019 07:55:14 +0000 (15:55 +0800)]
arm: socfpga: agilex: Add base address for Intel Agilex SoC

Add base address for Intel Agilex SoC.

Reuse base_addr_s10.h for Agilex, only one base address is
different from S10.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: socfpga: Convert clock manager from struct to defines
Ley Foon Tan [Fri, 8 Nov 2019 02:38:21 +0000 (10:38 +0800)]
arm: socfpga: Convert clock manager from struct to defines

Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get clock manager base address from DT node instead of using
#define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: socfpga: Convert system manager from struct to defines
Ley Foon Tan [Fri, 8 Nov 2019 02:38:20 +0000 (10:38 +0800)]
arm: socfpga: Convert system manager from struct to defines

Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get system manager base address from DT node instead of
using #define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: socfpga: Convert reset manager from struct to defines
Ley Foon Tan [Fri, 8 Nov 2019 02:38:19 +0000 (10:38 +0800)]
arm: socfpga: Convert reset manager from struct to defines

Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get reset manager base address from DT node instead of using
#define.

spl_early_init() initializes the DT setup. So, move spl_early_init() to
beginning of function and before get base address from DT.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoarm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes
Ley Foon Tan [Fri, 8 Nov 2019 02:38:18 +0000 (10:38 +0800)]
arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes

Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL.
In preparation to get base address from DT.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agospl: Allow cache drivers to be used in SPL
Ley Foon Tan [Fri, 11 Oct 2019 05:48:33 +0000 (13:48 +0800)]
spl: Allow cache drivers to be used in SPL

Add an option for building cache drivers in SPL.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoARM: dts: Import Khadas VIM3L DT from Linux 5.5-rc1
Christian Hewitt [Wed, 11 Dec 2019 09:20:53 +0000 (13:20 +0400)]
ARM: dts: Import Khadas VIM3L DT from Linux 5.5-rc1

Import the Khadas VIM3L device-tree from [1]

[1] e42617b825f8 ("Linux 5.5-rc1")

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agovideo: meson: Drop unnecessary header includes
Simon Glass [Sun, 27 Oct 2019 15:54:03 +0000 (09:54 -0600)]
video: meson: Drop unnecessary header includes

These files should not be included in meson header files. Drop them and
tidy up the affected C files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agoARM: mxs: spl_boot.c: make early_delay more robust
Rasmus Villemoes [Tue, 10 Sep 2019 08:32:01 +0000 (08:32 +0000)]
ARM: mxs: spl_boot.c: make early_delay more robust

It's true that booting normally doesn't take long enough for the
register to roll (which actually happens in a little over an hour, not
just a few seconds). However, the counter starts at power-on, and if
the board is held in reset to be booted over USB, one actually risks
hitting wrap-around during boot, which can both result in too short
delays (if the "st += delay" calculation makes st small) and
theoretically also unbound delays (if st ends up being UINT_MAX and
one just misses sampling digctl_microseconds at that point).

It doesn't take more code to DTRT, and once bitten, twice shy.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
4 years agoARM: dts: imx6qdl-icore-1.5: Remove duplicate phy reset methods
Michael Trimarchi [Mon, 30 Dec 2019 12:04:08 +0000 (17:34 +0530)]
ARM: dts: imx6qdl-icore-1.5: Remove duplicate phy reset methods

Engicam i.CoreM6 1.5 Quad/Dual MIPI dtsi is reusing fec node
from Engicam i.CoreM6 dtsi but have sampe copy of phy-reset-gpio
and phy-mode properties.

So, drop this phy reset methods from imx6qdl-icore-1.5 dsti file.

Cc: Jacopo Mondi <jacopo@jmondi.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agoARM: dts: imx6q-icore-mipi: Use 1.5 version of i.Core MX6DL
Jagan Teki [Mon, 30 Dec 2019 12:04:07 +0000 (17:34 +0530)]
ARM: dts: imx6q-icore-mipi: Use 1.5 version of i.Core MX6DL

The EDIMM STARTER KIT i.Core 1.5 MIPI Evaluation is based on
the 1.5 version of the i.Core MX6 cpu module. The 1.5 version
differs from the original one for a few details, including the
ethernet PHY interface clock provider.

With this commit, the ethernet interface works properly:
SMSC LAN8710/LAN8720 2188000.ethernet-1:00: attached PHY driver

While before using the 1.5 version, ethernet failed to startup
do to un-clocked PHY interface:
fec 2188000.ethernet eth0: could not attach to PHY

Similar fix has merged for i.Core MX6Q but missed to update for DL.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agoARM: dts: icorem6: Sync engicam device trees from v5.4
Jagan Teki [Mon, 30 Dec 2019 12:04:06 +0000 (17:34 +0530)]
ARM: dts: icorem6: Sync engicam device trees from v5.4

Sync Engicam device tree file from v5.4 linux-next.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>