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3 years agomips: octeon: Add cvmx-sata-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:49 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-sata-defs.h header file

Import cvmx-sata-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-rst-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:48 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-rst-defs.h header file

Import cvmx-rst-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-pow-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:47 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-pow-defs.h header file

Import cvmx-pow-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-pko-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:46 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-pko-defs.h header file

Import cvmx-pko-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-pki-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:45 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-pki-defs.h header file

Import cvmx-pki-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-pip-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:44 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-pip-defs.h header file

Import cvmx-pip-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-pepx-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:43 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-pepx-defs.h header file

Import cvmx-pepx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-pemx-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:42 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-pemx-defs.h header file

Import cvmx-pemx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-pcsx-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:41 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-pcsx-defs.h header file

Import cvmx-pcsx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-pciercx-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:40 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-pciercx-defs.h header file

Import cvmx-pciercx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-pcieepx-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:39 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-pcieepx-defs.h header file

Import cvmx-pcieepx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-npi-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:38 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-npi-defs.h header file

Import cvmx-npi-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-mio-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:37 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-mio-defs.h header file

Import cvmx-mio-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-l2c-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:36 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-l2c-defs.h header file

Import cvmx-l2c-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-ipd-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:35 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-ipd-defs.h header file

Import cvmx-ipd-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-gserx-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:34 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-gserx-defs.h header file

Import cvmx-gserx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-gmxx-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:33 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-gmxx-defs.h header file

Import cvmx-gmxx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-fpa-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:32 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-fpa-defs.h header file

Import cvmx-fpa-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-dtx-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:31 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-dtx-defs.h header file

Import cvmx-dtx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-dpi-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:30 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-dpi-defs.h header file

Import cvmx-dpi-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-dbg-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:29 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-dbg-defs.h header file

Import cvmx-dbg-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-ciu-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:28 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-ciu-defs.h header file

Import cvmx-ciu-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-bgxx-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:27 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-bgxx-defs.h header file

Import cvmx-bgxx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-asxx-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:26 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-asxx-defs.h header file

Import cvmx-asxx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add cvmx-agl-defs.h header file
Aaron Williams [Fri, 11 Dec 2020 16:05:25 +0000 (17:05 +0100)]
mips: octeon: Add cvmx-agl-defs.h header file

Import cvmx-agl-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: Add misc cvmx-helper header files
Aaron Williams [Fri, 11 Dec 2020 16:05:24 +0000 (17:05 +0100)]
mips: octeon: Add misc cvmx-helper header files

Import misc cvmx-helper header files from 2013 U-Boot. They will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: global_data.h: Add Octeon specific data to arch_global_data struct
Stefan Roese [Fri, 11 Dec 2020 16:05:23 +0000 (17:05 +0100)]
mips: global_data.h: Add Octeon specific data to arch_global_data struct

This will be used by the upcoming Serdes and driver code ported from
the original 2013 U-Boot code to mainline.

Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomips: octeon: octeon_ebb7304_defconfig: Enable USB storage support
Stefan Roese [Fri, 19 Feb 2021 13:02:17 +0000 (14:02 +0100)]
mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support

This patch enables USB storage support with the necessary partition
support on the MIPS Octeon EBB7304.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
3 years agomips: octeon: octeon_ebb7304_defconfig: Enable MMC support
Stefan Roese [Fri, 12 Mar 2021 08:48:28 +0000 (09:48 +0100)]
mips: octeon: octeon_ebb7304_defconfig: Enable MMC support

Enable MMC support including the regulator support on Octeon EBB7304.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 years agomips: octeon: mrvl,octeon_ebb7304.dts: Add MMC DT node
Stefan Roese [Fri, 12 Mar 2021 08:48:27 +0000 (09:48 +0100)]
mips: octeon: mrvl,octeon_ebb7304.dts: Add MMC DT node

Add the MMC DT node to the Octeon EBB7304 DT file including the
regulator node for the MMC power supply.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 years agomips: octeon: mrvl,cn73xx.dtsi: Add MMC DT node
Stefan Roese [Fri, 12 Mar 2021 08:48:26 +0000 (09:48 +0100)]
mips: octeon: mrvl,cn73xx.dtsi: Add MMC DT node

Add the MMC DT node to the Octeon CN73xx dtsi file.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 years agommc: octeontx_hsmmc: Add support for MIPS Octeon
Stefan Roese [Fri, 12 Mar 2021 08:48:25 +0000 (09:48 +0100)]
mmc: octeontx_hsmmc: Add support for MIPS Octeon

Until now, the Octeontx MMC driver did only support the ARM Octeon
TX/Tx2 platforms. This patch adds support for the MIPS Octeon platform
to this driver. Here a short summary of the changes:

- Enable driver compilation for MIPS Octeon, including the MMC related
  header file
- Reorder header inclusion
- Switch to using the clk framework to get the input clock
- Remove some functions for MIPS Octeon, as some registers don't
  exist here

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 years agomips: mt7628: fix the displayed DDR type of mt7628
Weijie Gao [Fri, 5 Mar 2021 03:13:27 +0000 (11:13 +0800)]
mips: mt7628: fix the displayed DDR type of mt7628

The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type
from bootstrap register must be ignored, and always be assumed as DDR1.

This patch fixes the displayed DDR type of mt7628.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agomips: mt7628: fix ddr_type for MT7688KN
Weijie Gao [Tue, 23 Feb 2021 07:12:44 +0000 (15:12 +0800)]
mips: mt7628: fix ddr_type for MT7688KN

The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type
from bootstrap register must be ignored, and always be assumed as DDR1.

This patch fixes an issue that mt7628_ddr_pad_ldo_config() may be passed
with a wrong ddr_type in MT7688KN.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agonet: jr2: Fix Serdes6G configuration
Horatiu Vultur [Wed, 10 Mar 2021 08:31:39 +0000 (09:31 +0100)]
net: jr2: Fix Serdes6G configuration

Sometimes no traffic was getting out on the ports, the root cause was
a wrong configuration of the Serdes6G, which is used on jr2 pcb111.
This patch fixes this issue by applying the correct configuration.

Fixes: 5e1d417bec92ac ("net: Add MSCC Jaguar2 network driver.")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
3 years agonet: jr2: Reset switch
Horatiu Vultur [Wed, 10 Mar 2021 08:31:38 +0000 (09:31 +0100)]
net: jr2: Reset switch

Make sure to reset the switch core at probe time.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
3 years agoMerge branch '2021-04-20-assorted-improvements'
Tom Rini [Tue, 20 Apr 2021 11:32:04 +0000 (07:32 -0400)]
Merge branch '2021-04-20-assorted-improvements'

- ARM64 GIC fix, CONFIG_IRQ now moved to Kconfig
- IDE, lz4 fixes
- octeontx cleanups / enhancements
- highbank DM migration
- psci updates
- Enable use of -fstack-protector

3 years agoAdd support for stack-protector
Joel Peshkin [Sun, 11 Apr 2021 09:21:58 +0000 (11:21 +0200)]
Add support for stack-protector

Add support for stack protector for UBOOT, SPL, and TPL
as well as new pytest for stackprotector

Signed-off-by: Joel Peshkin <joel.peshkin@broadcom.com>
Adjust UEFI build flags.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agox86: correct usage of CFLAGS_NON_EFI
Heinrich Schuchardt [Sun, 11 Apr 2021 09:21:57 +0000 (11:21 +0200)]
x86: correct usage of CFLAGS_NON_EFI

The current usage of the variable CFLAGS_NON_EFI on the x86 architecture
deviates from other architectures.

Variable CFLAGS_NON_EFI is the list of compiler flags to be removed when
building UEFI applications. It is not a list of flags to be added anywhere.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agotest: fix test/dm/regmap.c
Heinrich Schuchardt [Sun, 11 Apr 2021 09:21:56 +0000 (11:21 +0200)]
test: fix test/dm/regmap.c

regmap_read() only fills the first two bytes of val. The last two bytes are
random data from the stack. This means the test will fail randomly.

For low endian systems we could simply initialize val to 0 and get correct
results. But tests should not depend on endianness. So let's use a pointer
conversion instead.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agotoradex: configblock: fix module revision in config block
Denys Drozdov [Wed, 7 Apr 2021 12:28:24 +0000 (15:28 +0300)]
toradex: configblock: fix module revision in config block

U-boot might display wrong module revision information
for modules with an assembly version 'K'. "cfgblock create"
does not takes into account all revision digits from PID8.

This fix takes into account all digits of PID8
to store module revision.

Signed-off-by: Denys Drozdov <denys.drozdov@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
3 years agodoc: usage: add usage details for reset cmd
Igor Opaniuk [Wed, 31 Mar 2021 23:01:56 +0000 (02:01 +0300)]
doc: usage: add usage details for reset cmd

Add usage details for reset command.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
3 years agosysreset: provide type of reset in do_reset cmd
Igor Opaniuk [Wed, 31 Mar 2021 23:01:55 +0000 (02:01 +0300)]
sysreset: provide type of reset in do_reset cmd

Add additional param for reset cmd, which provides type of reset.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
3 years agosysreset: psci: use psci driver exported functions
Igor Opaniuk [Wed, 31 Mar 2021 23:01:54 +0000 (02:01 +0300)]
sysreset: psci: use psci driver exported functions

Use psci driver exported functions for reset/poweroff, instead of
invoking directly invoke_psci_fn.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
3 years agopsci: add features/reset2 support
Igor Opaniuk [Wed, 31 Mar 2021 23:01:53 +0000 (02:01 +0300)]
psci: add features/reset2 support

Adds support for:
* PSCI_FEATURES, which was introduced in PSCI 1.0. This provides API
that allows discovering whether a specific PSCI function is implemented
and its features.
* SYSTEM_RESET2, which was introduced in PSCI 1.1, which extends existing
SYSTEM_RESET. It provides support for vendor-specific resets, providing
reset_type as an additional param.

For additional details visit [1].

Implementations of some functions were borrowed from Linux PSCI driver
code [2].

[1] https://developer.arm.com/documentation/den0022/latest/
[2] drivers/firmware/psci/psci.c

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
3 years agopsci: add v1.0/v1.1 definitions from Linux
Igor Opaniuk [Wed, 31 Mar 2021 23:01:52 +0000 (02:01 +0300)]
psci: add v1.0/v1.1 definitions from Linux

Sync and add PSCI API versions 1.0/1.1 definitions from Linux.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
3 years agosysinfo.h: Add re-inclusion guard
Tom Rini [Mon, 19 Apr 2021 20:18:49 +0000 (16:18 -0400)]
sysinfo.h: Add re-inclusion guard

Add #ifndef __SYSINFO_H__ ... #endif to prevent re-inclusion of this
file.

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoarm: highbank: Update maintainership
Andre Przywara [Mon, 12 Apr 2021 00:04:55 +0000 (01:04 +0100)]
arm: highbank: Update maintainership

Rob does not have access to any Calxeda systems anymore, also has
expressed a lack of interest in those systems in the past.

I have multiple working Midway nodes under my desk in the office, so
am happy to take over maintainership.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
3 years agoarm: highbank: Do DRAM init from DT
Andre Przywara [Mon, 12 Apr 2021 00:04:54 +0000 (01:04 +0100)]
arm: highbank: Do DRAM init from DT

So far U-Boot was hard coding a (surely sufficient) memory size of 512
MB, even though all machines out there have at least 4GB of DRAM.
Since U-Boot uses its memory knowledge to populate the EFI memory map,
we are missing out here, at best losing everything beyond 4GB on Midway
boxes (which typically come with 8GB of DRAM).

Since the management processor populated the DT memory node already with
the detected DRAM size and configuration, we use that to populate
U-Boot's memory bank information, which is the base for the UEFI memory
map.
This finally allows us to get rid of the NR_DRAM_BANKS=0 hack, that we
had in place to avoid U-Boot messing up the DT memory node before
loading the kernel.

Also, to cover the whole of memory, we need to enable PHYS_64BIT.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
3 years agoarm: highbank: Remove artificial SDRAM size
Andre Przywara [Mon, 12 Apr 2021 00:04:53 +0000 (01:04 +0100)]
arm: highbank: Remove artificial SDRAM size

So far we were defining a somewhat confusing PHYS_SDRAM_1_SIZE variable,
which originally was only used for setting the memtest boundaries. This
definition in highbank.h has been removed about a year ago (moved to
Kconfig), so we also don't need the hard-coded size definition any longer.

Get rid of the misleading memory size definition, which was actually wrong
anyway (it's 4088 MB for those machines with just 4GB of DRAM).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
3 years agonet: calxedagmac: Convert to DM_ETH
Andre Przywara [Mon, 12 Apr 2021 00:04:52 +0000 (01:04 +0100)]
net: calxedagmac: Convert to DM_ETH

To squash that nasty warning message and make better use of the newly
gained OF_CONTROL feature, let's convert the calxedagmac driver to the
"new" driver model.
The conversion is pretty straight forward, mostly just adjusting the
use of the involved data structures.
The only actual change is the required split of the receive routine into
a receive and free_pkt part.
Also this allows us to get rid of the hardcoded platform information and
explicit init calls.

This also uses the opportunity to wrap the code decoding the MMIO
register base address, to make it safe for using PHYS_64BIT later.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
3 years agoarm: highbank: Enable OF_CONTROL
Andre Przywara [Mon, 12 Apr 2021 00:04:51 +0000 (01:04 +0100)]
arm: highbank: Enable OF_CONTROL

All Calxeda machines are actually a poster book example of device tree
usage: the DT is loaded from flash by the management processor into
DRAM, the memory node is populated with the detected DRAM size and this
DT is then handed over to the kernel.
So it's a shame that U-Boot didn't participate in this chain, but
fortunately this is easy to fix:

Define CONFIG_OF_CONTROL and CONFIG_OF_BOARD, and provide a trivial
function to tell U-Boot about the (fixed) location of the DTB in DRAM.
Then enable DM_SERIAL, to let the PL011 driver pick up the UART platform
data from the DT. Also define AHCI, to bring this driver into the driver
model world as well.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
3 years agoarm: highbank: Limit FDT and initrd load addresses
Andre Przywara [Mon, 12 Apr 2021 00:04:50 +0000 (01:04 +0100)]
arm: highbank: Limit FDT and initrd load addresses

So far on Highbank/Midway machines U-Boot only ever uses 512MB of DRAM,
even though the machines have typically 4GB and 8GB, respectively.
That means that so far we didn't need an extra limit for placing the DTB
and initrd, as the 512MB are lower than the kernel's limit ("lowmem",
typically 768MB).

With U-Boot now needing to learn about the actual memory size (to
correctly populate the EFI memory map), it might relocate fdt and initrd
to the end of DRAM, which is out of reach of the kernel.

So add limiting values to the fdt_high and initrd_high environment
variables, to prevent U-Boot from using too high addresses.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
3 years agodoc: device-tree-bindings: regulator: anatop regulator
Ying-Chun Liu (PaulLiu) [Sat, 27 Mar 2021 13:46:52 +0000 (21:46 +0800)]
doc: device-tree-bindings: regulator: anatop regulator

Document the bindings for fsl,anatop-regulator

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
3 years agopower: regulator: add driver for ANATOP regulator
Ying-Chun Liu (PaulLiu) [Sat, 27 Mar 2021 13:46:51 +0000 (21:46 +0800)]
power: regulator: add driver for ANATOP regulator

Anatop is an integrated regulator inside i.MX6 SoC.
There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
This patch adds the Anatop regulator driver.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
3 years agocmd: CONFIG_CMD_MMC depends on CONFIG_MMC
Heinrich Schuchardt [Sat, 27 Mar 2021 10:43:54 +0000 (11:43 +0100)]
cmd: CONFIG_CMD_MMC depends on CONFIG_MMC

Trying to compile with CONFIG_CMD_MMC=y and CONFIG_MMC=n leads to errors:

riscv64-linux-gnu-ld.bfd: cmd/built-in.o: in function `do_mmcops':
cmd/mmc.c:984: undefined reference to `get_mmc_num'
riscv64-linux-gnu-ld.bfd: cmd/built-in.o: in function `do_mmc_setdsr':
cmd/mmc.c:873: undefined reference to `find_mmc_device'

Add missing dependency.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
3 years agonet: octeontx: smi: fix mii probe
Tim Harvey [Fri, 26 Mar 2021 00:07:37 +0000 (17:07 -0700)]
net: octeontx: smi: fix mii probe

The fdt node offset is apparently not set properly when probed
causing no MDIO busses to be found. Fix this by obtaining the
offset.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agodrivers: ata: ahci: update max id if it is more than available ports
Suneel Garapati [Fri, 26 Mar 2021 00:07:36 +0000 (17:07 -0700)]
drivers: ata: ahci: update max id if it is more than available ports

After check for maximum between max id and available ports, also check
if available port count is less than max id and update.

In the case of the CN8030 OcteonTX SoC max_id needs to be reduced to
the number of ports found otherwise the following occurs on a scan:

GW6404-B> scsi scan
scanning bus for devices...
Target spinup took 0 ms.
AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
flags: 64bit ncq ilck stag pm led clo only pmp fbss pio slum part ccc
apst
  Device 0: (0:0) Vendor: ATA Prod.: SanDisk SD8SFAT0 Rev: Z233
            Type: Hard Disk
            Capacity: 61057.3 MB = 59.6 GB (125045424 x 512)
"Synchronous Abort" handler, esr 0x96000006
elr: 000000000052f824 lr : 000000000052fa10 (reloc)
elr: 000000007fee9824 lr : 000000007fee9a10
x0 : 0000000000000001 x1 : 0000000000000001
x2 : 000000007bea3528 x3 : 000000007bea3580
x4 : 0000000000000200 x5 : 0000000000000000
x6 : 0000000000000002 x7 : 000000007bea3540
x8 : 00000000fffffff8 x9 : 0000000000000008
x10: 00000000000186a0 x11: 000000000000000d
x12: 0000000000000006 x13: 000000000001869f
x14: 0000000000000007 x15: 00000000ffffffff
x16: 000000007ff439a5 x17: 000000007ff5730c
x18: 000000007bea9de0 x19: 000000007ff7a580
x20: 000000007bec79f8 x21: 0000000000000000
x22: 000000007bea3580 x23: 0000000000000000
x24: 0000000000000000 x25: 000000007bec7a00
x26: 00000000ffffffc0 x27: 000000007bec79d0
x28: 000000007beb51c0 x29: 000000007bea3480

Code: 91246800 940130c2 12800000 1400004f (b9402ae0)
Resetting CPU ...

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agodrivers: net: octeontx: fix QSGMII
Tim Harvey [Fri, 26 Mar 2021 00:07:35 +0000 (17:07 -0700)]
drivers: net: octeontx: fix QSGMII

Revert a change that occured between the Marvell SDK-10.1.1.0
and SDK-10.3.1.1 which broke QSMII phy support.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3 years agoarm: octeontx: enable WDT_SBSA
Tim Harvey [Fri, 26 Mar 2021 00:07:34 +0000 (17:07 -0700)]
arm: octeontx: enable WDT_SBSA

The OcteonTX uses ARM's SBSA Watchdog device

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: octeontx: support generic distro config
Tim Harvey [Fri, 26 Mar 2021 00:07:33 +0000 (17:07 -0700)]
arm: octeontx: support generic distro config

Support Generic Distro Default config

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: octeontx: move CONFIG_SUPPORT_RAW_INITRD to configs
Tim Harvey [Fri, 26 Mar 2021 00:07:32 +0000 (17:07 -0700)]
arm: octeontx: move CONFIG_SUPPORT_RAW_INITRD to configs

Move CONFIG_SUPPORT_RAW_INITRD out of the octeontx_common header
and into the defconfig files.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agolz4: Fix unaligned accesses
Karl Beldan [Wed, 17 Mar 2021 22:31:58 +0000 (22:31 +0000)]
lz4: Fix unaligned accesses

Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com>
3 years agoFix IDE commands issued, fix endian issues, fix non MMIO
Reinoud Zandijk [Wed, 24 Feb 2021 16:44:42 +0000 (17:44 +0100)]
Fix IDE commands issued, fix endian issues, fix non MMIO

Fixes IDE issues found on the Malta board under Qemu:

1) DMA implied commands were sent to the controller in stead of the PIO
variants. The rest of the code is DMA free and written for PIO operation.

2) direct pointer access was used to read and write the registers instead
of the inb/inw/outb/outw functions/macros. Registers don't have to be
memory mapped and ATA_CURR_BASE() does not have to return an offset from
address zero.

3) Endian isues in ide_ident() and reading/writing data in general. Names
were corrupted and sizes misreported.

Tested malta_defconfig and maltael_defconfig to work again in Qemu.

Signed-off-by: Reinoud Zandijk <reinoud@NetBSD.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agosandbox: enable IRQ using select for sandbox architecture
Wasim Khan [Mon, 8 Mar 2021 15:48:16 +0000 (16:48 +0100)]
sandbox: enable IRQ using select for sandbox architecture

Enable IRQ using select for sandbox architecture.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoarch: Kconfig: enable IRQ using select for x86 architecture
Wasim Khan [Mon, 8 Mar 2021 15:48:15 +0000 (16:48 +0100)]
arch: Kconfig: enable IRQ using select for x86 architecture

use 'select' to enable IRQ as it does not have architecture
specific dependency.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoarch: arm: update Kconfig to select IRQ when GIC_V3_ITS is enabled
Wasim Khan [Mon, 8 Mar 2021 15:48:14 +0000 (16:48 +0100)]
arch: arm: update Kconfig to select IRQ when GIC_V3_ITS is enabled

GIC_V3_ITS uses UCLASS_IRQ driver. Update Kconfig to select
IRQ when GIC_V3_ITS is enabled.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
3 years agomisc: make CONFIG_IRQ selectable for all platforms
Wasim Khan [Mon, 8 Mar 2021 15:48:13 +0000 (16:48 +0100)]
misc: make CONFIG_IRQ selectable for all platforms

UCLASS_IRQ driver is not Intel specific. Make CONFIG_IRQ
selectable for all platforms.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoarm64: gic-v3-its: Clear the Pending table before enabling LPIs
Hou Zhiqiang [Fri, 5 Mar 2021 07:02:35 +0000 (15:02 +0800)]
arm64: gic-v3-its: Clear the Pending table before enabling LPIs

The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables
must contain only zeros on initial allocation, and this must be visible
to the Redistributors, or else the effect is UNPREDICTABLE".

And as the following statement, we here clear the whole Pending tables
instead of the first 1KB.
"An LPI Pending table that contains only zeros, including in the first 1KB,
indicates that there are no pending LPIs.
The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However,
if the first 1KB of the LPI Pending table and the rest of the table contain
only zeros, this must indicate that there are no pending LPIs."

And there isn't any pending LPI under U-Boot, so it's unnecessary to
load the contents of the Pending table during the enablement, then set
the GICR_PENDBASER.PTZ flag.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> # NXP LS1028A
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboards: amlogic: update documentation for PCIe support
Neil Armstrong [Fri, 16 Apr 2021 12:22:31 +0000 (14:22 +0200)]
boards: amlogic: update documentation for PCIe support

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoconfigs: meson64: add NVME boot target
Neil Armstrong [Fri, 26 Feb 2021 14:17:36 +0000 (15:17 +0100)]
configs: meson64: add NVME boot target

Let's add a boot target for NVMe so we can do a full boot over NVMe.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoconfigs: khadas-vim3: enable PCIe and NVMe
Neil Armstrong [Fri, 26 Feb 2021 13:47:06 +0000 (14:47 +0100)]
configs: khadas-vim3: enable PCIe and NVMe

Now we have PCIe, let's also enable NVMe to access an eventual NVMe SSDs
connected on the M.2 slot.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoarm: dts: meson-khadas-vim3: enable PCIe in U-boot
Neil Armstrong [Thu, 25 Feb 2021 17:47:05 +0000 (18:47 +0100)]
arm: dts: meson-khadas-vim3: enable PCIe in U-boot

Enable PCIe by default in u-boot, this should eventually be made dynamic
in the runtime board config depending on the MCU configuration.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agophy: meson-g12a-usb3-pcie: add support for PCIe ops
Neil Armstrong [Thu, 25 Feb 2021 16:53:23 +0000 (17:53 +0100)]
phy: meson-g12a-usb3-pcie: add support for PCIe ops

Add the PCIe part of the G12A USB3 PCIe Combo PHY driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoclk: meson-g12a: add PCIe gates
Neil Armstrong [Thu, 25 Feb 2021 17:46:12 +0000 (18:46 +0100)]
clk: meson-g12a: add PCIe gates

Add missing gates used for PCIe.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoarm64: dts: meson: odroidc2: readd PHY reset properties
Stefan Agner [Thu, 8 Apr 2021 08:25:28 +0000 (10:25 +0200)]
arm64: dts: meson: odroidc2: readd PHY reset properties

The sync of the device tree and dt-bindings from Linux v5.6-rc2
11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
ODROID-C2. The PHY seems to need proper reset timing to be functional
in U-Boot and Linux afterwards. Readd the old PHY reset bindings for
dwmac until we support the new bindings in the PHY node.

Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoMerge tag 'u-boot-amlogic-20210419' of https://source.denx.de/u-boot/custodians/u...
Tom Rini [Mon, 19 Apr 2021 17:35:23 +0000 (13:35 -0400)]
Merge tag 'u-boot-amlogic-20210419' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- fix Ethernet on Odroid-C2 by re-adding old bindings style PHY reset
- add G12A PCIe clock gates
- add G12A PCIe PHY OPs
- enable PCIe for Khadas VIM3/VIM3L boards DT
- enable PCIe and NVME for Khadas VIM3/VIM3L boards config
- update Amlogic board documentation for PCIe support

3 years agoMerge tag 'u-boot-atmel-2021.07-b' of https://source.denx.de/u-boot/custodians/u...
Tom Rini [Mon, 19 Apr 2021 15:34:17 +0000 (11:34 -0400)]
Merge tag 'u-boot-atmel-2021.07-b' of https://source.denx.de/u-boot/custodians/u-boot-atmel

Second set of u-boot-atmel features for 2021.07 cycle:

This small feature set include support for 5th PIO bank on pio4 pinctrl
driver and a fix for the SPL on sama5d3.

3 years agoRevert "spl: Drop bd_info in the data section"
Alexandru Gagniuc [Thu, 8 Apr 2021 16:56:11 +0000 (11:56 -0500)]
Revert "spl: Drop bd_info in the data section"

This reverts commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75.

struct global_data contains a pointer to the bd_info structure. This
pointer was populated spl_set_bd() to a pre-allocated bd_info in the
".data" section. The referenced commit replaced this mechanism to one
that uses malloc(). That new mechanism is only used if SPL_ALLOC_BD=y.
which very few boards do.

The result is that (struct global_data)->bd is NULL in SPL on most
platforms. This breaks falcon mode, since arch_fixup_fdt() tries to
access (struct global_data)->bd and set the "/memory" node in the
devicetree. The result is that the "/memory" node contains garbage
values, causing linux to panic() as it sets up the page table.

Instead of trying to fix the mess, potentially causing other issues,
revert to the code that worked, while this change is reworked.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agoboards: amlogic: update documentation for PCIe support
Neil Armstrong [Fri, 16 Apr 2021 12:22:31 +0000 (14:22 +0200)]
boards: amlogic: update documentation for PCIe support

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoconfigs: meson64: add NVME boot target
Neil Armstrong [Fri, 26 Feb 2021 14:17:36 +0000 (15:17 +0100)]
configs: meson64: add NVME boot target

Let's add a boot target for NVMe so we can do a full boot over NVMe.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoconfigs: khadas-vim3: enable PCIe and NVMe
Neil Armstrong [Fri, 26 Feb 2021 13:47:06 +0000 (14:47 +0100)]
configs: khadas-vim3: enable PCIe and NVMe

Now we have PCIe, let's also enable NVMe to access an eventual NVMe SSDs
connected on the M.2 slot.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoarm: dts: meson-khadas-vim3: enable PCIe in U-boot
Neil Armstrong [Thu, 25 Feb 2021 17:47:05 +0000 (18:47 +0100)]
arm: dts: meson-khadas-vim3: enable PCIe in U-boot

Enable PCIe by default in u-boot, this should eventually be made dynamic
in the runtime board config depending on the MCU configuration.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agophy: meson-g12a-usb3-pcie: add support for PCIe ops
Neil Armstrong [Thu, 25 Feb 2021 16:53:23 +0000 (17:53 +0100)]
phy: meson-g12a-usb3-pcie: add support for PCIe ops

Add the PCIe part of the G12A USB3 PCIe Combo PHY driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoclk: meson-g12a: add PCIe gates
Neil Armstrong [Thu, 25 Feb 2021 17:46:12 +0000 (18:46 +0100)]
clk: meson-g12a: add PCIe gates

Add missing gates used for PCIe.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoarm64: dts: meson: odroidc2: readd PHY reset properties
Stefan Agner [Thu, 8 Apr 2021 08:25:28 +0000 (10:25 +0200)]
arm64: dts: meson: odroidc2: readd PHY reset properties

The sync of the device tree and dt-bindings from Linux v5.6-rc2
11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
ODROID-C2. The PHY seems to need proper reset timing to be functional
in U-Boot and Linux afterwards. Readd the old PHY reset bindings for
dwmac until we support the new bindings in the PHY node.

Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoARM: dts: at91: sama5d3: add u-boot properties to sama5d3 pit timer
Manuel Reis [Tue, 6 Apr 2021 09:39:53 +0000 (10:39 +0100)]
ARM: dts: at91: sama5d3: add u-boot properties to sama5d3 pit timer

in the early SPL boot stage whenever there is a call to udelay,
dm_timer_init fails to find the pit timer whenever it traverses
the device tree, if this property is not present

Signed-off-by: Manuel Reis <mluis.reis@gmail.com>
CC: Eugen Hristev <eugen.hristev@microchip.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
3 years agoARM: dts: at91: sama7g5: change pinctrl compatible to sama7g5
Eugen Hristev [Wed, 7 Apr 2021 08:39:29 +0000 (11:39 +0300)]
ARM: dts: at91: sama7g5: change pinctrl compatible to sama7g5

Change the pinctrl compatible to sama7g5, the right one for this product.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
3 years agogpio: atmel_pio4: add support for sama7g5 pio4 version with 5 banks
Eugen Hristev [Wed, 7 Apr 2021 08:39:28 +0000 (11:39 +0300)]
gpio: atmel_pio4: add support for sama7g5 pio4 version with 5 banks

Add support for sama7g5 pinctrl variant, with 5 banks with a degraded
8 line only 5th bank.
Based on Linux Kernel implementation.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
3 years agoMerge tag 'efi-2021-07-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Tom Rini [Sun, 18 Apr 2021 12:47:27 +0000 (08:47 -0400)]
Merge tag 'efi-2021-07-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2021-07-rc1-2

Documentation:
man-page for fatinfo

Bug fixes:
memory leak in efi_capsule_scan_dir()
incorrect invocations of EFI_CALL macro creating ESRT table
buffer overflow in tcg2_create_digest()

3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-usb
Tom Rini [Sun, 18 Apr 2021 12:46:58 +0000 (08:46 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-usb

This is a patchset which makes away with the .bind() controller indexing
workaround which was broken since before v2021.04, and then adds PHY
support and MX8M support on top of that. Better add it into the release
early to get as much testing as possible done, because this really does
a lot of changes to the ehci-mx6 driver.

3 years agoMerge tag 'ti-v2021.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-ti
Tom Rini [Sun, 18 Apr 2021 12:46:39 +0000 (08:46 -0400)]
Merge tag 'ti-v2021.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-ti

- Support for pinmux status command on beaglebone
- Updates for MMC speed modes for J721e-evm
- Fix MMC booting on omap35_logic_somlv board

3 years agoMerge branch '2021-04-16-env-updates'
Tom Rini [Sun, 18 Apr 2021 12:44:25 +0000 (08:44 -0400)]
Merge branch '2021-04-16-env-updates'

- SPI Flash ENV improvements / cleanups
- Redundant support for FAT
- Assorted bugfixes

3 years agoARM: imx8m: verdin-imx8mm: Enable USB Host support
Marek Vasut [Wed, 31 Mar 2021 21:46:35 +0000 (23:46 +0200)]
ARM: imx8m: verdin-imx8mm: Enable USB Host support

Enable USB host support on MX8MM Verdin.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Max Krummenacher <max.krummenacher@toradex.com>
Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
3 years agousb: ehci-mx6: Add iMX8M support
Marek Vasut [Fri, 2 Apr 2021 12:07:22 +0000 (14:07 +0200)]
usb: ehci-mx6: Add iMX8M support

The iMX8M uses nop PHY, select PHY and NOP_PHY automatically.
Otherwise, the DM capable driver is now perfectly compatible.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
3 years agousb: ehci-mx6: Fix aarch64 build warnings
Marek Vasut [Tue, 6 Apr 2021 18:37:16 +0000 (20:37 +0200)]
usb: ehci-mx6: Fix aarch64 build warnings

Fix cast from pointer to integer of different size by casting the
pointer to uintptr_t instead of uint32_t, the former has correct
size on both 32bit and 64bit architectures.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
3 years agousb: ehci-mx6: Add fsl,imx7d-usb compatible string
Marek Vasut [Fri, 2 Apr 2021 11:07:59 +0000 (13:07 +0200)]
usb: ehci-mx6: Add fsl,imx7d-usb compatible string

Add new compatible string, used by some more up-to-date DTs.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
3 years agousb: ehci-mx6: Set default CONFIG_MXC_USB_PORTSC if not defined
Marek Vasut [Sat, 10 Apr 2021 14:03:04 +0000 (16:03 +0200)]
usb: ehci-mx6: Set default CONFIG_MXC_USB_PORTSC if not defined

There is now multiple copies of CONFIG_MXC_USB_PORTSC in configs set to
PORT_PTS_UTMI | PORT_PTS_PTW, which is in fact the default register value
for MX6, MX7 and MX7ULP. Define the default value of CONFIG_MXC_USB_PORTSC
in the driver and use it in case CONFIG_MXC_USB_PORTSC is not defined in
config, to reduce the duplication.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
3 years agousb: ehci-mx6: Add generic EHCI PHY support
Marek Vasut [Fri, 2 Apr 2021 11:07:49 +0000 (13:07 +0200)]
usb: ehci-mx6: Add generic EHCI PHY support

In case PHY support is enabled, use the generic EHCI PHY support
to start and stop the PHY.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
3 years agousb: ehci-mx6: Use portnr from DT in DM case
Marek Vasut [Fri, 2 Apr 2021 11:56:28 +0000 (13:56 +0200)]
usb: ehci-mx6: Use portnr from DT in DM case

In case the platform uses DM, determine port number, which is
used as offset in USBMISC registers, from PHY node DT aliases,
just like Linux does.

Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>