]> git.dujemihanovic.xyz Git - u-boot.git/log
u-boot.git
2 years agoarm: samsung: Remove dead LCD code
Tom Rini [Sat, 11 Jun 2022 02:59:31 +0000 (22:59 -0400)]
arm: samsung: Remove dead LCD code

Since bb5930d5c97f ("exynos: video: Convert several boards to driver
model for video") there have been no callers of any of the exynos_lcd_*
family of functions.  Remove these from the boards, and then remove
unused logo and related code as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2 years agoblock: ide: Remove ide_preinit function
Tom Rini [Sat, 11 Jun 2022 02:59:30 +0000 (22:59 -0400)]
block: ide: Remove ide_preinit function

The only platform currently that defines an ide_preinit function has an
empty one that immediately returns.  Remove this hook.

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoata: sata_sil: Remove useless BLK guard in sata_sil.h
Tom Rini [Sat, 11 Jun 2022 02:59:29 +0000 (22:59 -0400)]
ata: sata_sil: Remove useless BLK guard in sata_sil.h

Now that the driver only supports CONFIG_BLK, remove the useless guard
in sata_sil.h.

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoConvert CONFIG_LBA48 et al to Kconfig
Tom Rini [Sat, 11 Jun 2022 02:59:28 +0000 (22:59 -0400)]
Convert CONFIG_LBA48 et al to Kconfig

This converts the following to Kconfig:
   CONFIG_LBA48
   CONFIG_SYS_64BIT_LBA

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoConvert CONFIG_FSL_SATA_V2 to Kconfig
Tom Rini [Sat, 11 Jun 2022 02:59:27 +0000 (22:59 -0400)]
Convert CONFIG_FSL_SATA_V2 to Kconfig

This converts the following to Kconfig:
   CONFIG_FSL_SATA_V2

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoata: fsl_sata: Remove legacy non-BLK code
Tom Rini [Sat, 11 Jun 2022 02:59:26 +0000 (22:59 -0400)]
ata: fsl_sata: Remove legacy non-BLK code

The migration deadline for this has passed and all boards have been
updated, remove this legacy code and references for it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoata: dwc_ahsata: Remove legacy non-CONFIG_AHCI code
Tom Rini [Sat, 11 Jun 2022 02:59:25 +0000 (22:59 -0400)]
ata: dwc_ahsata: Remove legacy non-CONFIG_AHCI code

The migration deadline for this has passed and all boards have been
updated, remove this legacy code and references for it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoxtensa: Switch to using CONFIG_XTENSA for building device trees
Tom Rini [Sat, 11 Jun 2022 02:59:24 +0000 (22:59 -0400)]
xtensa: Switch to using CONFIG_XTENSA for building device trees

The only use of CONFIG_XTFPGA was to build all of the in-tree device
trees.  Switch to using CONFIG_XTENSA instead of a non-Kconfig symbol.

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agovpl: Ensure all VPL symbols in Kconfig have some VPL dependency
Tom Rini [Wed, 8 Jun 2022 12:24:40 +0000 (08:24 -0400)]
vpl: Ensure all VPL symbols in Kconfig have some VPL dependency

Tighten up symbol dependencies in a number of places.  Ensure that a VPL
specific option has at least a direct dependency on VPL.  In places
where it's clear that we depend on something more specific, use that
dependency instead.

Reported-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agotpl: Ensure all TPL symbols in Kconfig have some TPL dependency
Tom Rini [Wed, 8 Jun 2022 12:24:39 +0000 (08:24 -0400)]
tpl: Ensure all TPL symbols in Kconfig have some TPL dependency

Tighten up symbol dependencies in a number of places.  Ensure that a TPL
specific option has at least a direct dependency on TPL.  In places
where it's clear that we depend on something more specific, use that
dependency instead.

Reported-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agospl: Move SPL_LDSCRIPT defaults to one place
Tom Rini [Wed, 8 Jun 2022 12:24:37 +0000 (08:24 -0400)]
spl: Move SPL_LDSCRIPT defaults to one place

We want to keep all of the default values for SPL_LDSCRIPT in the same
place both for overall clarity as well as not polluting unrelated config
files.

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agousb: ehci-mx5: Remove non-DM code
Tom Rini [Wed, 8 Jun 2022 12:24:36 +0000 (08:24 -0400)]
usb: ehci-mx5: Remove non-DM code

The deadline for DM_USB migration has passed and all users have been
migrated.  Remove now unused code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agousb: ehci-mxc: Remove
Tom Rini [Wed, 8 Jun 2022 12:24:35 +0000 (08:24 -0400)]
usb: ehci-mxc: Remove

There are no platforms enabling this driver, remove.

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoPowerPC: Remove some unused USB code
Tom Rini [Wed, 8 Jun 2022 12:24:34 +0000 (08:24 -0400)]
PowerPC: Remove some unused USB code

These particular code paths aren't used anymore, remove.

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoConvert CONFIG_TEGRA_GPU to Kconfig
Tom Rini [Wed, 8 Jun 2022 12:24:33 +0000 (08:24 -0400)]
Convert CONFIG_TEGRA_GPU to Kconfig

This converts the following to Kconfig:
   CONFIG_TEGRA_GPU

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agousb: xhci-fsl: Remove non-DM code
Tom Rini [Wed, 8 Jun 2022 12:24:32 +0000 (08:24 -0400)]
usb: xhci-fsl: Remove non-DM code

The deadline for DM_USB migration has passed and all users have been
migrated.  Remove now unused code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoConvert CONFIG_USB_EHCI_TXFIFO_THRESH to Kconfig
Tom Rini [Wed, 8 Jun 2022 12:24:31 +0000 (08:24 -0400)]
Convert CONFIG_USB_EHCI_TXFIFO_THRESH to Kconfig

This converts the following to Kconfig:
   CONFIG_USB_EHCI_TXFIFO_THRESH

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agousb: ehci-fsl: Remove non-DM code
Tom Rini [Wed, 8 Jun 2022 12:24:30 +0000 (08:24 -0400)]
usb: ehci-fsl: Remove non-DM code

The deadline for DM_USB migration has passed and all users have been
migrated.  Remove now unused code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoConvert CONFIG_HAS_FSL_DR_USB to Kconfig
Tom Rini [Wed, 8 Jun 2022 12:24:28 +0000 (08:24 -0400)]
Convert CONFIG_HAS_FSL_DR_USB to Kconfig

This converts the following to Kconfig:
   CONFIG_HAS_FSL_DR_USB

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoConvert CONFIG_EHCI_HCD_INIT_AFTER_RESET to Kconfig
Tom Rini [Wed, 8 Jun 2022 12:24:27 +0000 (08:24 -0400)]
Convert CONFIG_EHCI_HCD_INIT_AFTER_RESET to Kconfig

This converts the following to Kconfig:
   CONFIG_EHCI_HCD_INIT_AFTER_RESET

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoConvert CONFIG_EHCI_DESC_BIG_ENDIAN et al to Kconfig
Tom Rini [Wed, 8 Jun 2022 12:24:26 +0000 (08:24 -0400)]
Convert CONFIG_EHCI_DESC_BIG_ENDIAN et al to Kconfig

This converts the following to Kconfig:
   CONFIG_EHCI_DESC_BIG_ENDIAN
   CONFIG_EHCI_MMIO_BIG_ENDIAN

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoehci-mxs: Remove non-DM code
Tom Rini [Wed, 8 Jun 2022 12:24:25 +0000 (08:24 -0400)]
ehci-mxs: Remove non-DM code

This code is not enabled anywhere, drop it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoConvert CONFIG_EFLASH_PROTSECTORS to Kconfig
Tom Rini [Wed, 8 Jun 2022 12:24:24 +0000 (08:24 -0400)]
Convert CONFIG_EFLASH_PROTSECTORS to Kconfig

This converts the following to Kconfig:
   CONFIG_EFLASH_PROTSECTORS

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoConvert CONFIG_E1000_NO_NVM to Kconfig
Tom Rini [Wed, 8 Jun 2022 12:24:23 +0000 (08:24 -0400)]
Convert CONFIG_E1000_NO_NVM to Kconfig

This converts the following to Kconfig:
   CONFIG_E1000_NO_NVM

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoMerge branch '2022-06-28-mpc85xx-and-aspeed-fixes' into next
Tom Rini [Tue, 28 Jun 2022 14:52:00 +0000 (10:52 -0400)]
Merge branch '2022-06-28-mpc85xx-and-aspeed-fixes' into next

- Merge a PowerPC MPC85xx cleanup / fix, and aspeed linker fix

2 years agoaspeed/ast2600: Fix SPL linker script
Joel Stanley [Tue, 28 Jun 2022 04:27:25 +0000 (13:57 +0930)]
aspeed/ast2600: Fix SPL linker script

The commit 99e2fbcb69f0 ("linker_lists: Rename sections to remove .
prefix") changed the name of the linker list sections. As the Aspeed SPL
linker wasn't in the tree yet, it missed the change.

This updates the SPL linker to match arch/arm/cpu/u-boot-spl.lds which
Aspeed was copied from.

Fixes: 442a69c14375 ("configs: ast2600: Move SPL bss section to DRAM space")
Signed-off-by: Joel Stanley <joel@jms.id.au>
2 years agopowerpc: mpc85xx: Set TEXT_BASE addresses to real base values
Pali Rohár [Thu, 16 Jun 2022 12:19:44 +0000 (14:19 +0200)]
powerpc: mpc85xx: Set TEXT_BASE addresses to real base values

Currently CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE addresses are
manually increased by 0x1000 due to .bootpg section. This section has size
of 0x1000 bytes and is manually put by linker script before .text section
(and therefore before base address) when CONFIG_SYS_MPC85XX_NO_RESETVEC is
set. Due to this fact lot of other config options are manually increased by
0x1000 value to make correct layout. Note that entry point is not on
CONFIG_SPL_TEXT_BASE (image+0x1000) but it is really on address
CONFIG_SPL_TEXT_BASE-0x1000 (means at the start of the image).

Cleanup handling of .bootpg section when CONFIG_SYS_MPC85XX_NO_RESETVEC is
set. Put .bootpg code directly into .text section and move text base
address to the start of .bootpg code. And finally remove +0x1000 value from
lot of config options. With this removal custom PHDRS is not used anymore,
so remove it too.

After this change entry point would be at CONFIG_SPL_TEXT_BASE and not at
address -0x1000 anymore.

Tested on P2020 board with SPL and proper U-Boot.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agoMerge branch '2022-06-27-add-armv8-sha1-sha256-support' into next
Tom Rini [Mon, 27 Jun 2022 17:39:19 +0000 (13:39 -0400)]
Merge branch '2022-06-27-add-armv8-sha1-sha256-support' into next

To quote the author:

This series adds support for the SHA-1 and SHA-256 Secure Hash Algorithm
for CPUs that have support of the ARM v8 Crypto Extensions. It Improves
speed of integrity & signature checking procedures.

2 years agoqemu_arm64: Enable CONFIG_ARMV8_CRYPTO support
Tom Rini [Thu, 23 Jun 2022 19:44:47 +0000 (15:44 -0400)]
qemu_arm64: Enable CONFIG_ARMV8_CRYPTO support

Now that we can make use of CPU features for sha1/sha256, enable in QEMU
so that we get some test coverage.

Cc: Loic Poulain <loic.poulain@linaro.org>
Cc: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoarmv8 SHA-256 using ARMv8 Crypto Extensions
Loic Poulain [Wed, 1 Jun 2022 18:26:31 +0000 (20:26 +0200)]
armv8 SHA-256 using ARMv8 Crypto Extensions

This patch adds support for the SHA-256 Secure Hash Algorithm for CPUs
that have support for the SHA-256 part of the ARM v8 Crypto Extensions.

It greatly improves sha-256 based operations, about 17x faster on iMX8M
evk board. ~12ms vs ~208ms for a 20MiB kernel sha-256 verification.

asm implementation is a simplified version of the Linux version (from
Ard Biesheuvel).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2 years agolib: sha256: Add support for hardware specific sha256_process
Loic Poulain [Wed, 1 Jun 2022 18:26:30 +0000 (20:26 +0200)]
lib: sha256: Add support for hardware specific sha256_process

Mark sha256_process as weak to allow hardware specific implementation.
Add parameter for supporting multiple blocks processing.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2 years agoarmv8 SHA-1 using ARMv8 Crypto Extensions:
Loic Poulain [Wed, 1 Jun 2022 18:26:29 +0000 (20:26 +0200)]
armv8 SHA-1 using ARMv8 Crypto Extensions:

This patch adds support for the SHA-1 Secure Hash Algorithm for CPUs
that have support for the SHA-1 part of the ARM v8 Crypto Extensions.

It greatly improves sha-1 based operations, about 10x faster on iMX8M
evk board. ~12ms vs ~165ms for a 20MiB kernel sha-1 verification.

asm implementation is a simplified version of the Linux version (from
Ard Biesheuvel).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2 years agosha1: Fix digest state size/type
Loic Poulain [Wed, 1 Jun 2022 18:26:28 +0000 (20:26 +0200)]
sha1: Fix digest state size/type

sha1 digest size is 5*32-bit => 160-bit. Using 64-bit unsigned long
does not cause issue with the current sha1 implementation, but could
be problematic for vectorized access.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2 years agolib: sha1: Add support for hardware specific sha1_process
Loic Poulain [Wed, 1 Jun 2022 18:26:27 +0000 (20:26 +0200)]
lib: sha1: Add support for hardware specific sha1_process

Mark sha1_process as weak to allow hardware specific implementation.
Add parameter to support for multiple blocks processing.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2 years agoMerge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot...
Tom Rini [Mon, 27 Jun 2022 14:15:50 +0000 (10:15 -0400)]
Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.10

cpu:
- Add driver for microblaze cpu

net:
- Add support for DM_ETH_PHY to AXI emac and emaclite

xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS

zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize

versal:
- Enable loading app at EL1

serial:
- Setup default address and clock rates for DEBUG uarts

pinctrl:
- Add support for tri state and output enable properties

relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze

microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support

timer:
- Extract axi timer driver from Microblaze to generic location

2 years agotimer: Add SPL_REGMAP dependency for Xilinx timer
Michal Simek [Thu, 23 Jun 2022 11:08:30 +0000 (13:08 +0200)]
timer: Add SPL_REGMAP dependency for Xilinx timer

Add SPL_REGMAP dependency when SPL is enabled. This can avoid compilation
issues if timer is selected but SPL_REGMAP not.

Reported-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8f6c187e04cb3127bf5148ae2dbbdf55b25ea544.1655982509.git.michal.simek@amd.com
2 years agoxilinx: Enable support for SquashFS
Michal Simek [Thu, 23 Jun 2022 11:04:21 +0000 (13:04 +0200)]
xilinx: Enable support for SquashFS

Enable SquashFS for all xilinx platforms.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/dbe85afda8cd90ebfc537979d382808ff9bec160.1655982259.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Move helper functions below header includes
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:50 +0000 (18:36 +0200)]
arm64: zynqmp: Move helper functions below header includes

Move helper functions in psu_init files below header includes to avoid
forward declarations.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-15-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agotools: zynqmp_psu_init_minimize: Move helper functions below header includes
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:49 +0000 (18:36 +0200)]
tools: zynqmp_psu_init_minimize: Move helper functions below header includes

Move helper functions below header includes to avoid forward
declarations.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-14-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agotools: zynqmp_psu_init_minimize: Use CR instead of LF
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:48 +0000 (18:36 +0200)]
tools: zynqmp_psu_init_minimize: Use CR instead of LF

Use carriage return instead of line feed to support mangling across
lines.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-13-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agotools: zynqmp_psu_init_minimize: Remove low level uart settings
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:47 +0000 (18:36 +0200)]
tools: zynqmp_psu_init_minimize: Remove low level uart settings

There is no reason to do serial initialization. Uart driver does it
already based on DT. Good effect is that it is clear which interface is
console.
The resulting change was done in past by commit 84d2bbf082fa ("arm64:
zynqmp: Remove low level UART setting").

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-12-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoxilinx: zynqmp: make spi flash support optional
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:46 +0000 (18:36 +0200)]
xilinx: zynqmp: make spi flash support optional

The set_dfu_alt_info function use the CONFIG_SYS_SPI_U_BOOT_OFFS define
to set the dfu_alt_info environment variable for qspi boot mode. Guard
the usage of CONFIG_SYS_SPI_U_BOOT_OFFS to make spi flash support
optional.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-11-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoxilinx: common: Separate display cpu info function
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:45 +0000 (18:36 +0200)]
xilinx: common: Separate display cpu info function

Move the print_cpuinfo function of CONFIG_DISPLAY_CPUINFO into its own
source file to support reuse by other board vendors.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-10-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoxilinx: cpuinfo: Print soc machine
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:44 +0000 (18:36 +0200)]
xilinx: cpuinfo: Print soc machine

Print the soc machine in the print_cpuinfo function.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-9-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agosoc: xilinx: zynqmp: Add machine identification support
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:43 +0000 (18:36 +0200)]
soc: xilinx: zynqmp: Add machine identification support

Add machine identification support based on the
zynqmp_get_silicon_idcode_name function and use the soc_get_machine
function of the soc uclass to get silicon idcode name for the fpga init.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-8-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agosoc: xilinx: zynqmp: Remove redundant checks for zynqmp_mmio_read
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:42 +0000 (18:36 +0200)]
soc: xilinx: zynqmp: Remove redundant checks for zynqmp_mmio_read

Remove the redundant SPL and CurrentEL checks for the zynqmp_mmio_read
function call because the function itself runs the same checks.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-7-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoxilinx: zynqmp: Merge device lists
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:41 +0000 (18:36 +0200)]
xilinx: zynqmp: Merge device lists

Merge the svd / xck devices into to the common zynqmp device list.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-6-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoxilinx: zynqmp: Reuse shift macros to define masks
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:40 +0000 (18:36 +0200)]
xilinx: zynqmp: Reuse shift macros to define masks

Reuse the shift macros to define the masks.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-5-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoxilinx: zynqmp: Add macro for device type mask
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:39 +0000 (18:36 +0200)]
xilinx: zynqmp: Add macro for device type mask

Add a macro for the device type mask of the id code.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-4-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoxilinx: zynqmp: Replace strncat with strlcat
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:38 +0000 (18:36 +0200)]
xilinx: zynqmp: Replace strncat with strlcat

Replace strncat with strlcat to always produce a valid null-terminated
string.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-3-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agofirmware: zynqmp: Probe driver before use
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:37 +0000 (18:36 +0200)]
firmware: zynqmp: Probe driver before use

Probe the driver before use to ensure that the driver is always
available and the global data are valid. Initialize the global data
with zero and probe the driver if the global data are still zero. This
allows a usage of the firmware functions from other drivers with
arbitrary order between the drivers.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-2-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agofirmware: zynqmp: Check if rx channel dev pointer is valid
Stefan Herbrechtsmeier [Mon, 20 Jun 2022 16:36:36 +0000 (18:36 +0200)]
firmware: zynqmp: Check if rx channel dev pointer is valid

Check if rx channel dev pointer is valid and not if the address of the
pointer is valid.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoARM: zynq: Fix size-cells for pl353 driver
Amit Kumar Mahapatra [Wed, 15 Jun 2022 10:22:41 +0000 (12:22 +0200)]
ARM: zynq: Fix size-cells for pl353 driver

"size-cells" of the nand controller node should be 0 as the "reg"
property of the nand device node contains the chip select number and not
address information.
The patch fixes the below compilation warning
arch/arm/dts/zynq-zc770-xm011.dtb: Warning (reg_format):
/axi/memory-controller@e000e000/nand-controller@0,0/nand@0:reg: property
has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1)

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6e90665a2dad7fe8ade10b8f57101f8144963791.1655288559.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Fix usb node drive strength and slew rate
Ashok Reddy Soma [Wed, 15 Jun 2022 10:16:13 +0000 (12:16 +0200)]
arm64: zynqmp: Fix usb node drive strength and slew rate

As per design, all input/rx pins should have fast slew rate and 12mA
drive strength. Rest all pins should be slow slew rate and 4mA drive
strength. Fix usb nodes as per this and remove setting of slow slew rate
for all the usb gorup pins.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b245c165f05845c1f3ab41a92c82b7ec1538cee4.1655288171.git.michal.simek@amd.com
2 years agomicroblaze: Remove interrupt handler
Michal Simek [Fri, 24 Jun 2022 12:16:32 +0000 (14:16 +0200)]
microblaze: Remove interrupt handler

The primary purpose for this code was timer. By converting it to
CONFIG_TIMER there is no code which uses this implementation that's why
remove it. If there is a need to handle interrupts this patch can be
reverted in future.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5f2decc5a30a5678490ebde26d8c6f5a5f873cda.1654684731.git.michal.simek@amd.com
2 years agomicroblaze: Convert axi timer to DM driver
Michal Simek [Fri, 24 Jun 2022 12:16:32 +0000 (14:16 +0200)]
microblaze: Convert axi timer to DM driver

Move axi timer driver from Microblaze to generic location.
Origin implementation was irq based with counting down timer.

CONFIG_TIMER drivers are designed differently that timer is free running up
timer with automatic reload without any interrupt.
Information about clock rates are find out in timer_pre_probe() that's why
there is no need to get any additional information from DT in the driver
itself (only register offset).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
2 years agocpu: add CPU driver for microblaze
Ovidiu Panait [Tue, 31 May 2022 18:14:35 +0000 (21:14 +0300)]
cpu: add CPU driver for microblaze

Add a basic CPU driver that retrieves information about the microblaze CPU
core. cpu_ops handlers are implemented so that the "cpu" command can work
properly:

U-Boot-mONStR> cpu list
  0: cpu@0      MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
U-Boot-mONStR> cpu detail
  0: cpu@0      MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
        ID = 0, freq = 50 MHz: L1 cache, MMU

Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from
linux.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-14-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agomicroblaze: add support for handling PVR data
Ovidiu Panait [Tue, 31 May 2022 18:14:34 +0000 (21:14 +0300)]
microblaze: add support for handling PVR data

Add helper code for PVR (Processor Version Register) data handling. It
will be used by the UCLASS_CPU driver to populate cpuinfo fields at
runtime.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-13-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agomicroblaze: Kconfig: introduce XILINX_MICROBLAZE0_FPGA_FAMILY option
Ovidiu Panait [Tue, 31 May 2022 18:14:33 +0000 (21:14 +0300)]
microblaze: Kconfig: introduce XILINX_MICROBLAZE0_FPGA_FAMILY option

Provide a static Kconfig value for the target FPGA archtitecture, as it is
done in Linux. The cpu-uclass driver will cross-check it with the value
read from PVR10 register.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-12-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agomicroblaze: cache: introduce flush_dcache_range()
Ovidiu Panait [Tue, 31 May 2022 18:14:32 +0000 (21:14 +0300)]
microblaze: cache: introduce flush_dcache_range()

Align microblaze with the other architectures and provide an
implementation for flush_dcache_range(). Also, remove the microblaze
exception in drivers/core/device.c.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-11-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agomicroblaze: cache: introduce cpuinfo structure
Ovidiu Panait [Tue, 31 May 2022 18:14:31 +0000 (21:14 +0300)]
microblaze: cache: introduce cpuinfo structure

Introduce a minimal cpuinfo structure to hold cache related info. The
instruction/data cache size and cache line size are initialized early in
the boot to default Kconfig values. They will be overwritten with data
from PVR/dtb if the microblaze UCLASS_CPU driver is enabled.

The cpuinfo struct was placed in global_data to allow the microblaze
UCLASS_CPU driver to also run before relocation (initialized global data
should be read-only before relocation).

gd_cpuinfo() helper macro was added to avoid volatile
"-Wdiscarded-qualifiers" warnings when using the pointer directly.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-10-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/)
2 years agomicroblaze: cache: introduce flush_cache_all()
Ovidiu Panait [Tue, 31 May 2022 18:14:30 +0000 (21:14 +0300)]
microblaze: cache: introduce flush_cache_all()

All flush_cache() calls in microblaze code are supposed to flush the
entire instruction and data caches, so introduce flush_cache_all()
helper to handle this.

Also, provide implementations for flush_dcache_all() and
invalidate_icache_all() so that icache and dcache u-boot commands can
work.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-9-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agomicroblaze: cache: introduce Kconfig options for icache/dcache sizes
Ovidiu Panait [Tue, 31 May 2022 18:14:29 +0000 (21:14 +0300)]
microblaze: cache: introduce Kconfig options for icache/dcache sizes

Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for
instruction and data caches sizes, respectively:
CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE
CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE

Also, get rid of the hardcoded value in icache_disable().

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/g)
2 years agomicroblaze: cache: split flush_cache() function
Ovidiu Panait [Tue, 31 May 2022 18:14:28 +0000 (21:14 +0300)]
microblaze: cache: split flush_cache() function

Factor out icache/dcache components from flush_cache() function. Call the
newly added __flush_icache()/__flush_dcache() functions inside
icache_disable() and dcache_disable(), respectively. There is no need to
flush both caches when disabling a particular cache type.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-7-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agomicroblaze: cache: improve icache Kconfig options
Ovidiu Panait [Tue, 31 May 2022 18:14:27 +0000 (21:14 +0300)]
microblaze: cache: improve icache Kconfig options

Replace CONFIG_ICACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WIC. It should be enabled if the processor supports
the "wic" (Write to Instruction Cache) instruction. It will be used to
guard "wic" invocations in microblaze cache code.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-6-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agomicroblaze: cache: improve dcache Kconfig options
Ovidiu Panait [Tue, 31 May 2022 18:14:26 +0000 (21:14 +0300)]
microblaze: cache: improve dcache Kconfig options

Replace CONFIG_DCACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports
the "wdc" (Write to Data Cache) instruction. It will be used to guard
"wdc" invocations in microblaze cache code.

Also, drop all ifdefs around flush_cache() calls and only keep one
CONFIG_IS_ENABLED() guard within flush_cache() itself.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-5-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agomicroblaze: cache: replace XILINX_USE_DCACHE -> CONFIG_DCACHE
Ovidiu Panait [Tue, 31 May 2022 18:14:25 +0000 (21:14 +0300)]
microblaze: cache: replace XILINX_USE_DCACHE -> CONFIG_DCACHE

XILINX_USE_DCACHE macro was removed in 7556fa09e0e ("microblaze: Simplify
cache handling"), but it was still used in a couple of places.

Replace those occurences with CONFIG_DCACHE.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-4-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agomicroblaze: start.S: remove unused code
Ovidiu Panait [Tue, 31 May 2022 18:14:24 +0000 (21:14 +0300)]
microblaze: start.S: remove unused code

in16/out16 routines seem to not be used anywhere in microblaze code, so
remove them.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-3-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agocpu-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOC
Ovidiu Panait [Tue, 31 May 2022 18:14:23 +0000 (21:14 +0300)]
cpu-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOC

Relocate cpu_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled.

The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done
logic works for drivers that use DM_FLAG_PRE_RELOC.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-2-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agocmd: cpu: migrate cpu command to U_BOOT_CMD_WITH_SUBCMDS()
Ovidiu Panait [Tue, 31 May 2022 18:14:22 +0000 (21:14 +0300)]
cmd: cpu: migrate cpu command to U_BOOT_CMD_WITH_SUBCMDS()

Migrate cpu command to use U_BOOT_CMD_WITH_SUBCMDS() helper macro, to
reduce duplicated code. This also fixes the cpu command on boards that
enable CONFIG_NEEDS_MANUAL_RELOC.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-1-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agomicroblaze: Add support for run time relocation
Michal Simek [Fri, 24 Jun 2022 12:15:01 +0000 (14:15 +0200)]
microblaze: Add support for run time relocation

Microblaze is using NEEDS_MANUAL_RELOC from the beginnging. This is causing
issues with function pointer arrays which need to be updated manually after
relocation. Building code with -fPIC and linking with -pic will remove this
limitation and there is no longer need to run manual update.

By default still old option is enabled but by disabling NEEDS_MANUAL_RELOC
code will be compiled for full relocation.

The patch does couple of things which are connected to each other.
- Define STATIC_RELA dependency to call relocate-rela to fill sections.
- REMAKE_ELF was already enabled but u-boot file can't be used because
  sections are empty. relocate-rela will fill them and output file is
  u-boot.elf which should be used.
- Add support for full relocation (u-boot.elf)
- Add support for early relocation when u-boot.bin is loaded to different
  address then CONFIG_SYS_TEXT_BASE
- Add rela.dyn and dynsym sections

Disabling NEEDS_MANUAL_RELOC U-Boot size increased by 10% of it's original
size (550kB to 608kB).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a845670b34925859b2e321875f7588a29f6655f9.1655299267.git.michal.simek@amd.com
2 years agotools: relocate-rela: Add support for 32bit Microblaze relocation
Michal Simek [Fri, 24 Jun 2022 12:15:00 +0000 (14:15 +0200)]
tools: relocate-rela: Add support for 32bit Microblaze relocation

Microblaze is 32bit that's why it is using elf32 format. Relocation code
requires to get information about rela and dynsym senctions and also text
base which was used for compilation.
Code build with -fPIC and linked with -pic generates 4 relocation types.
R_MICROBLAZE_NONE is the easiest one which doesn't require any action.
R_MICROBLAZE_REL only requires write addend to r_offset address.
R_MICROBLAZE_32/R_MICROBLAZE_GLOB_DAT are the most complicated. There is a
need to find out symbol value with adding symbol value and write it to
address pointed by r_offset. Calculation with addend is also added but
only 0 addend values are generated now.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9912c3d76933bdf75e1ebb6aab43726cd32cafb5.1655299267.git.michal.simek@amd.com
2 years agotools: relocate-rela: Add support for elf32 decoding
Michal Simek [Fri, 24 Jun 2022 12:15:00 +0000 (14:15 +0200)]
tools: relocate-rela: Add support for elf32 decoding

Add support for 32bit ELF format which is used by Microblaze. Also check
that code runs only for Microblaze.

Function finds information about rela.dyn and dynsym which will be used
later for relocation.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7491cc72fe04cbd48db014f1492ce463e91dfb42.1655299267.git.michal.simek@amd.com
2 years agotools: relocate-rela: Check that relocation works only for EM_AARCH64
Michal Simek [Fri, 24 Jun 2022 12:15:00 +0000 (14:15 +0200)]
tools: relocate-rela: Check that relocation works only for EM_AARCH64

Relocation support is only for EM_AARCH64 that's why check machine type to
make sure that the code will never run on any unsupported one.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/36f26c8752335239344b265e5ddedad10e9cac8b.1655299267.git.michal.simek@amd.com
2 years agotools: relocate-rela: Extract elf64 reloc to special function
Michal Simek [Fri, 24 Jun 2022 12:15:00 +0000 (14:15 +0200)]
tools: relocate-rela: Extract elf64 reloc to special function

Adding support for new type requires to change code layout that's why move
elf64 code to own function for easier maintenance.

It also solves the problem with not calling fclose in case of error.
Return value from rela_elf64 is saved to variable that's why fclose() is
called all the time.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/21763b80527521c85ca7d4ac64ad6ff4885409c8.1655299267.git.michal.simek@amd.com
2 years agomicroblaze: Create SYM_ADDR macro to deal with symbols
Michal Simek [Fri, 24 Jun 2022 12:15:00 +0000 (14:15 +0200)]
microblaze: Create SYM_ADDR macro to deal with symbols

Symbol handling depends on compilation flags. Right now manual relocation
is used that's why symbols can be referenced just by name and there is no
need to find them out. But when position independent code (PIC) is used
symbols need to be described differently. That's why having one macro
change is easier than changing the whole code.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d704e9a267c8b536452fb999111dbfbc9d652be5.1655299267.git.michal.simek@amd.com
2 years agomicroblaze: Add comment about reset location
Michal Simek [Fri, 24 Jun 2022 12:15:00 +0000 (14:15 +0200)]
microblaze: Add comment about reset location

Better to add comment to explain why reset vector points all the time to
origin U-Boot location.
If reset happens U-Boot should start from it's origin location.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5ca6341b7487708247fe2948d7e496ea6f7c2e02.1655299267.git.michal.simek@amd.com
2 years agomicroblaze: Remove _start symbol handling at U-Boot start
Michal Simek [Fri, 24 Jun 2022 12:15:00 +0000 (14:15 +0200)]
microblaze: Remove _start symbol handling at U-Boot start

Right now U-Boot runs all the time from the same address where it is loaded
but going to full relocation code starting address doesn't need to be fixed
and can be simply discovered from reading PC register. That's why use r20
to get PC address and subtract offset from the beginning to get starting
address.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/044b727c33dfbe662f68512d0da0775a4805f360.1655299267.git.michal.simek@amd.com
2 years agomicroblaze: Remove code around r20 in relocate_code()
Michal Simek [Fri, 24 Jun 2022 12:15:00 +0000 (14:15 +0200)]
microblaze: Remove code around r20 in relocate_code()

r20 is not used that's why remove logic around it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1b32bab5c050d099b2f6d49bc4896322ed03d788.1655299267.git.michal.simek@amd.com
2 years agomicroblaze: Optimize register usage in relocate_code
Michal Simek [Fri, 24 Jun 2022 12:15:00 +0000 (14:15 +0200)]
microblaze: Optimize register usage in relocate_code

There are additional operations which can be done simpler that's why
improve logic around relocation address r7 handling and _start symbol.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8b60f72f1605c2ba6b4b7be1893d7e6ec3d8597.1655299267.git.michal.simek@amd.com
2 years agomicroblaze: Change stack protection address to new stack address
Michal Simek [Fri, 24 Jun 2022 12:15:00 +0000 (14:15 +0200)]
microblaze: Change stack protection address to new stack address

SLR low address is still setup to 0 that's why only high limit should be
updated. STACK_SIZE macro is present and could be possible used for
low address alignment but it is not done by this patch.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c00cb843df848703b760a65934ed3ce31fafcf19.1655299267.git.michal.simek@amd.com
2 years agomicroblaze: Separate code end substraction
Michal Simek [Fri, 24 Jun 2022 12:15:00 +0000 (14:15 +0200)]
microblaze: Separate code end substraction

Follow up patch will convert symbol handling that's why it is necessary to
separate logic around symbols to special instruction. It adds 4B for new
instruction but it is worth to do it to have code ready for for full
relocation.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/030863fa9a9c1ca0a9b082fe498522da09189fbc.1655299267.git.michal.simek@amd.com
2 years agomicroblaze: Enable REMAKE_ELF
Michal Simek [Fri, 24 Jun 2022 12:14:59 +0000 (14:14 +0200)]
microblaze: Enable REMAKE_ELF

Enable u-boot.elf recreation from u-boot.bin to prepare for removing manul
relocation. Enable option for big endian configuration but it is not used
too much that's why it is completely untested.
By supporting this system there is a need to define LITTLE/BIG endian
Kconfig options to pass -EL/-EB flags.

Full command line for u-boot.elf recreation looks like this:
microblazeel-xilinx-linux-gnu-objcopy -I binary -B microblaze \
 -O elf32-microblazeel u-boot.bin u-boot-elf.o

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7e242a519fcd1c693b9103c5599b515af555ca43.1655299267.git.michal.simek@amd.com
2 years agomips: Move endianness selection to arch/Kconfig
Michal Simek [Fri, 24 Jun 2022 12:14:59 +0000 (14:14 +0200)]
mips: Move endianness selection to arch/Kconfig

This option will be used by Microblaze that's why move it to generic
location to be able to use it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ceb39fa615cb5657b66a7b77bab99e86ca7a3346.1655299267.git.michal.simek@amd.com
2 years agomicroblaze: Fix typo in exception.c
Michal Simek [Fri, 24 Jun 2022 12:14:59 +0000 (14:14 +0200)]
microblaze: Fix typo in exception.c

Trivial fix.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c4ede6dc738c5bd7c518f3bb2c9410b15c102e20.1655299267.git.michal.simek@amd.com
2 years agomicroblaze: Remove CONFIG_TEXT_BASE from code
Michal Simek [Fri, 24 Jun 2022 12:14:59 +0000 (14:14 +0200)]
microblaze: Remove CONFIG_TEXT_BASE from code

Use symbol instead macro to find where U-Boot starts.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d5d4c201bee6171e85b47783d916387d84db0456.1655299267.git.michal.simek@amd.com
2 years agomicroblaze: Fix early stack allocation
Michal Simek [Fri, 24 Jun 2022 12:14:59 +0000 (14:14 +0200)]
microblaze: Fix early stack allocation

CONFIG_SYS_INIT_SP_OFFSET macro place stack to TEXT_BASE - SYS_MALLOC_F_LEN
but there is no reason to do it now because board_init_f_alloc_reserve()
returns exact location where stack should be. That's why stack location is
calculated at run time and there is no need to hardcode it via macro. This
change will help with placing U-Boot to any address.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e9aee69646e022fd8a96cbee2d2a07ab81fb6e05.1655299267.git.michal.simek@amd.com
2 years agomicroblaze: Fix stack protection behavior
Michal Simek [Fri, 24 Jun 2022 12:14:59 +0000 (14:14 +0200)]
microblaze: Fix stack protection behavior

When U-Boot starts stack protection can be already enabled that's why setup
the lowest possible SLR value which is address 0. And the highest possible
stack in front of U-Boot. That's why you should never load U-Boot to the
beginning of DDR. There must be some space reserved. Code is using this
location for early malloc space, early global data and stack.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/86b9748bad12142659804d6381bc6bbf20be44f1.1655299267.git.michal.simek@amd.com
2 years agomicroblaze: Switch absolute branches to relative
Michal Simek [Fri, 24 Jun 2022 12:14:59 +0000 (14:14 +0200)]
microblaze: Switch absolute branches to relative

There is no reason to use absolute branches and use just relative. This
change helps with moving binary to different location and start it from
there.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/83a5103b85c1c2220cd3ab4d5365169c6660e40a.1655299267.git.michal.simek@amd.com
2 years agotools: relocate-rela: Read rela start/end directly from ELF
Michal Simek [Fri, 24 Jun 2022 12:14:59 +0000 (14:14 +0200)]
tools: relocate-rela: Read rela start/end directly from ELF

There is no need to pass section information via parameters.
Let's read text base and rela start/end directly from elf.
It will help with reading other information from ELF for others
architecture. Input to relocate-rela is u-boot binary and u-boot ELF.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ab7ae14a6e058722e8c608089729e98edf20a08d.1655299267.git.michal.simek@amd.com
2 years agotools: relocate-rela: Use global variables
Michal Simek [Fri, 24 Jun 2022 12:14:59 +0000 (14:14 +0200)]
tools: relocate-rela: Use global variables

Declare rela_start/end and text_base as global variables. It will help with
using these variables for ELF decoding.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7485b163e92f8f3f754c35f7c88c3314f2212efd.1655299267.git.michal.simek@amd.com
2 years agoMakefile: Fix description for relocate-rela parameters
Michal Simek [Fri, 24 Jun 2022 12:14:59 +0000 (14:14 +0200)]
Makefile: Fix description for relocate-rela parameters

Numbers in comment are shifter which is visible from command which calls
them. Also relocate-rela usage is describing them.
"Usage: %s <bin file> <text base> <rela start> <rela end>"

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bb0287b9071eb33eea0cf914a7128c2603684377.1655299267.git.michal.simek@amd.com
2 years agotools: relocate-rela: Open binary u-boot file later
Michal Simek [Fri, 24 Jun 2022 12:14:59 +0000 (14:14 +0200)]
tools: relocate-rela: Open binary u-boot file later

There is no value to open u-boot binary file so early. Better to check all
values first and then open binary file.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9c2b4ebadbe83497db28af02f6af2623793ffdb6.1655299267.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Fix tps544/u3007 node description
Michal Simek [Wed, 15 Jun 2022 09:56:56 +0000 (11:56 +0200)]
arm64: zynqmp: Fix tps544/u3007 node description

u3007 is removed in zynqmp-m-a2197-02-revA board and on
zynqmp-m-a2197-03-revA it was renamed to v3022 at address 0x18.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f477796bcca6fce09168699a0498d792f4a54acf.1655287013.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Update tps53681 i2c address
Michal Simek [Wed, 15 Jun 2022 09:56:55 +0000 (11:56 +0200)]
arm64: zynqmp: Update tps53681 i2c address

TI manual (https://www.ti.com/lit/gpn/TPS53681) is saying that i2c address
is 7bit where c0h is 1100000 which is 0x60.

This will fix issues reported by make dtbs that 0xc0 is above 7bit regular
i2c address range.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2f50c1cd258f6b05deb2a6a9af7fa92952f3f8cb.1655287013.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Fix i2c addresses for vck190 SC
Michal Simek [Wed, 15 Jun 2022 09:56:54 +0000 (11:56 +0200)]
arm64: zynqmp: Fix i2c addresses for vck190 SC

si570 is normally at 0x5d address and address is not aligned with address
in node.
8T49N240 can't be at 0xd8 that's why it is shifter by one bit.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4fa86fffa9cb8abe633fbc5a9c55bea249b5edfb.1655287013.git.michal.simek@amd.com
2 years agopinctrl: zynqmp: Add support for output-enable and bias-high-impedance
Ashok Reddy Soma [Wed, 15 Jun 2022 09:52:28 +0000 (11:52 +0200)]
pinctrl: zynqmp: Add support for output-enable and bias-high-impedance

Add support to handle 'output-enable' and 'bias-high-impedance'
configurations. DT property output-enable brings out the pins from
tri-state, whereas bias-high-impedance changes the pins state to
tri-state.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1a02cd41d183d397ebce23c497178281c7286692.1655286745.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Enable DP for kv260-revA board
Michal Simek [Fri, 24 Jun 2022 12:14:25 +0000 (14:14 +0200)]
arm64: zynqmp: Enable DP for kv260-revA board

DP is enabled for revB and should be enabled for kv260-revA too. Changes in
other boards were done by commit 8b82a3a7feb0 ("arm64: zynqmp: Enable DP
driver for SOMs").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4e273bce3a8acf4495b67b702b1704acec8d9ccb.1654779436.git.michal.simek@amd.com
2 years agoxilinx: zynqmp: Do not use 0 as spl bss start address
Stefan Herbrechtsmeier [Tue, 7 Jun 2022 07:43:14 +0000 (09:43 +0200)]
xilinx: zynqmp: Do not use 0 as spl bss start address

Do not use 0 as address for memory because of the special meaning for
pointers (null pointer). Change the spl bss start address to the second
page.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220607074314.27125-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoarm64: zynqmp: Add support for kr260 revA/B boards
Michal Simek [Wed, 18 May 2022 10:49:26 +0000 (12:49 +0200)]
arm64: zynqmp: Add support for kr260 revA/B boards

Board is using kv260 design for couple of parts defined by spec like i2c
eeproms, ina260, uart, etc.

Board has 4 gems. One gem connected via PS SGMII(GT), another PS RGMII(MIO)
and 2 via EMIO. First two shares the same MIO lines for PHYs. PL based one
have separate EMIO lines via PL.

Also two USB 3.0 with usb hubs are present. USB phys and USB hubs should
have separate reset line. The first usb0 hub also has USB-SD controller
(usb2244) connected to port 0.

To test compatibility with k26 you can run:
fdtoverlay -o /tmp/output.dtb -i arch/arm/dts/zynqmp-sm-k26-revA.dtb \
arch/arm/dts/zynqmp-sck-kr-g-revA.dtbo

Also add support for kr260-revB board. Based on FRU it is revision B
but schematics can be label as revA03.
Changes in revB are:
- SFP light
- GEM2/3 TX_CLK fixes
- PMOD/RPI connector fixes
- Replace si5332 with oscilators

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/dac2ee1826e73b89c8cc1e430354eb43d291f675.1652870941.git.michal.simek@amd.com