The proper CPU ID for those Exynos variants is 0x5422,
but before the 0x5800 was set. This commit fix this back.
Changes:
- set cpu id to 0x5422 instead of 0x5800
- remove macro proid_is_exynos5800()
- add macro proid_is_exynos5422()
- change the calls to proid_is_exynos5800() with new macro
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This platform is based on Exynos5800 but the cpu id is 0x5422.
This doesn't fit the common Exynos SoC name convention, so now,
the CPU name is defined by device tree string, to be printed
properly.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The CPU name for Exynos was concatenated with cpu id,
but for new Exynos platforms, like Chromebook Peach Pi
based on Exynos5800, the name of SoC variant does not
include the real SoC cpu id (0x5422).
For such case, the CPU name should be defined in device tree.
This commit introduces new device-tree property for Exynos:
- "cpu-model" - with cpu name string
If defined, then the cpu id is not printed.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Alison Wang [Fri, 30 Oct 2015 14:45:38 +0000 (22:45 +0800)]
ls102xa: Adjust some macros for SD boot on LS1021A QDS board
As more features are added for SD boot on LS1021A QDS board,
the size of U-Boot is larger. CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS
needs to be adjusted to a suitable value.
Starting address of the malloc pool used in SPL needs to be
adjusted too, or it will occupy the address u-boot loads.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
It will take more than 1s when wake up from deep sleep. Most of the
time is spent on outputing information. This patch reduced the deep
sleep latency by:
1. avoid outputing system informaton
2. remove flush cache after DDR restore
3. skip reloading second stage uboot binary when SD boot
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Bin Meng [Thu, 8 Oct 2015 04:45:44 +0000 (21:45 -0700)]
net: eth: Check return value in various places
eth_get_dev() can return NULL which means device_probe() fails for
that ethernet device. Add return value check in various places or
U-Boot will crash due to NULL pointer access.
With this commit, 'dm_test_eth_act' test case passes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Bin Meng [Thu, 8 Oct 2015 04:45:42 +0000 (21:45 -0700)]
net: eth: Clear MAC address in eth_pre_remove()
platdata->enetaddr was assigned to a value in dev_probe() last time.
If we don't clear it, for dev_probe() at the second time, dm eth
will end up treating it as a MAC address from ROM no matter where it
came from originally (maybe env, ROM, or even random). Fix this by
clearing platdata->enetaddr when removing an Ethernet device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Bin Meng [Thu, 8 Oct 2015 04:32:39 +0000 (21:32 -0700)]
net: pch_gbe: Add driver remove support
In pch_gbe_probe(), some additional resources are allocated
(eg: mdio, phy). We should free these in the driver remove phase.
Add pch_gbe_remove() to clean it up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Bin Meng [Thu, 8 Oct 2015 04:32:38 +0000 (21:32 -0700)]
net: designware: Add driver remove support
In designware_eth_probe(), some additional resources are allocated
(eg: mdio, phy). We should free these in the driver remove phase.
Add designware_eth_remove() to clean it up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 8 Oct 2015 04:19:31 +0000 (21:19 -0700)]
net: phy: Test previous phydev->dev against new mac dev
In phy_connect_dev(), if the phy device has an accociated mac device
before, a warning message will be printed. But we should test the
old device against the new one, if they are actually the same one,
don't print the warning message.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Bin Meng [Thu, 8 Oct 2015 04:19:30 +0000 (21:19 -0700)]
net: phy: Change to print all phys that are not found
In get_phy_device_by_mask(), when no phy is found, currently we only
print a message to show the first phy address that is not found. But
this is not always the case as multiple phys can be specified by
phy_mask. Change to print all phys that are not found, and to reduce
the console boot log, change to use 'debug' instead of 'printf'.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Sylvain Rochet [Wed, 7 Oct 2015 20:54:22 +0000 (22:54 +0200)]
net: phy: micrel: disable NAND-tree for KSZ8051
NAND-tree is used to check wiring between MAC and PHY using NAND gates
on the PHY side, hence the name.
NAND-tree initial status is latched at reset by probing the IRQ pin.
However some devices are sharing the PHY IRQ pin with other peripherals
such as Atmel SAMA5D[34]x-EK boards when using the optional TM7000
display module, therefore they are switching the PHY in NAND-tree test
mode depending on the current IRQ line status at reset.
This patch ensure PHY is not in NAND-tree test mode only for the Micrel
KSZ8051 PHY used by Atmel. There are other Micrel PHY affected but I
doubt they are used on such weird hardware design.
Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stephen Warren [Fri, 2 Oct 2015 23:44:34 +0000 (17:44 -0600)]
net: rtl8169: Build warning fixes for 64-bit
Casting from dev->priv to pci_dev_t changes the value's size on a 64-bit
system. This causes the compiler to complain about casting a pointer to an
integer of a different (smaller) size. To avoid this, cast to an integer
of matching size first, then perform an int->int cast to perform the size
change. This signals explicitly that we do want to change the size, and
avoids the compiler warning. This is legitimate since we know the pointer
actually stores a small integer, not a pointer value.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stefan Brüns [Tue, 8 Sep 2015 03:12:00 +0000 (05:12 +0200)]
smsc95xx: Use zero length packets when RX fifo is empty
Using NAKs on empty RX fifo for bulk in transfers is the right choice
for a interrupt driven model, but U-Boot uses polling and expects an
immediate answer if there is no incoming packet. Using ZLP Bulk In Response
(BIR) mode avoids unexpected timeouts in the host controller driver.
As ZLP mode is reset default, there is no need to set it.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stefan Brüns [Thu, 3 Sep 2015 22:31:49 +0000 (00:31 +0200)]
net: parse DHCP options from overloaded file/sname fields
If Option 52 in the vendor option field signals overloading
of the file and/or sname fields, these field may contain
additional options. Formatting of file/sname contained options
is the same as in the vendor options field, but without the
leading magic.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
tang yuantian [Fri, 16 Oct 2015 08:06:05 +0000 (16:06 +0800)]
arm: ls1021a: Add sata support on qds and twr board
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Mon, 26 Oct 2015 06:08:28 +0000 (14:08 +0800)]
arm: ls102xa: Set fdt_high and initrd_high to the value of 0xffffffff
As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel
fails to access the device tree blob on boot. The reason is that u-boot
relocates the device tree blob into high memory when booting the kernel
and the kernel is unable to access the blob.
To avoid this issue, fdt_high is set to the value of 0xffffffff. The
device tree blob will not get relocated and is still in low memory to
make it accessible to the kernel.
For the same reason, initrd_high is set to the value of 0xffffffff too.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Hou Zhiqiang [Mon, 26 Oct 2015 11:47:57 +0000 (19:47 +0800)]
armv8/ls1043a: Enable secondary cores
After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to
make secondary cores excute in spin loop.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Yangbo Lu [Mon, 26 Oct 2015 11:47:55 +0000 (19:47 +0800)]
armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb
This patch adds esdhc support for ls1043ardb.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Mon, 26 Oct 2015 11:47:54 +0000 (19:47 +0800)]
armv8/ls1043a: Add Fman support
Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Gong Qianyu [Mon, 26 Oct 2015 11:47:53 +0000 (19:47 +0800)]
armv8/ls1043ardb: Add nand boot support
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Mingkai Hu [Mon, 26 Oct 2015 11:47:52 +0000 (19:47 +0800)]
armv8/ls1043ardb: Add LS1043ARDB board support
LS1043ARDB Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 SDRAM (32bit bus)
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* XFI 10G port
* QSGMII with 4x 1G ports
* Two RGMII ports
PCIe:
* PCIe2 (Lanes C) to mini-PCIe slot
* PCIe3 (Lanes D) to PCIe slot
USB 3.0: two super speed USB 3.0 type A ports
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Mingkai Hu [Mon, 26 Oct 2015 11:47:51 +0000 (19:47 +0800)]
armv8/fsl_lsch2: Add fsl_lsch2 SoC
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Mingkai Hu [Mon, 26 Oct 2015 11:47:50 +0000 (19:47 +0800)]
armv8/fsl_lsch3: Change arch to fsl-layerscape
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Mon, 26 Oct 2015 11:47:49 +0000 (19:47 +0800)]
net/fm: fix MDIO controller base on FMAN2
MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are two
FMANs, so we should only define MDIO controller base on FMAN2 when there
is FMAN2.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Mon, 26 Oct 2015 11:47:48 +0000 (19:47 +0800)]
net/fm: Add QSGMII PCS init
QSGMII PCS needed to be programmed same as SGMII PCS, and there are
four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared
port 0's MDIO controller, so when programming port 0, we continue to
program other three ports.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Mon, 26 Oct 2015 11:47:47 +0000 (19:47 +0800)]
net: Move some header files to include/
The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Mon, 26 Oct 2015 11:47:46 +0000 (19:47 +0800)]
net: fm: bug fix when CONFIG_PHYLIB not defined
codes related to phylib operations should be wrapped by CONFIG_PHYLIB.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Hou Zhiqiang [Mon, 26 Oct 2015 11:47:45 +0000 (19:47 +0800)]
net/fm: Make the return value logic consistent with convention
In convention, the '0' is a normal return value indicating there isn't
an error. While some functions of FMan IM driver treat '0' as an error
return value.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Hou Zhiqiang [Mon, 26 Oct 2015 11:47:44 +0000 (19:47 +0800)]
net/fm: Add support for 64-bit platforms
The FMan IM driver is developed for 32-bit platfroms and isn't
friendly to 64-bit platforms, so do the minimal refactor:
1. Refine the MURAM management and access.
2. Correct the initialization and operations for QDs and BDs.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Hou Zhiqiang [Mon, 26 Oct 2015 11:47:43 +0000 (19:47 +0800)]
net/fm: Fix the endian issue to support both endianness platforms
The Frame Manager(FMan) is a big-endian peripheral, so the
registers, internal MURAM and BDs, which are allocated in main
memory and used to communication between core and FMan, should
be accessed in big-endian. The big-endian platforms can access
them directly as the code implemented so far, while for the
little-endian platforms it need to swap the byte-order.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Mingkai Hu [Mon, 26 Oct 2015 11:47:41 +0000 (19:47 +0800)]
armv7/ls1021a: move ns_access to common file
Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Gong Qianyu [Mon, 26 Oct 2015 11:47:42 +0000 (19:47 +0800)]
common/board_f.c: change the macro name and remove it for PPC platforms
For most PPC platforms, they will call the first get_clocks() in
init_sequence_f[] as they define CONFIG_PPC. CONFIG_SYS_FSL_CLK is
then defined to call the second get_clocks(), which should be
redundant for PPC.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
arm: ls102xa: enable snooping for CAAM transactions
Enable snooping for CAAM read & write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[SECWRSNP]
Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Aneesh Bansal [Thu, 29 Oct 2015 17:28:03 +0000 (22:58 +0530)]
crypto/fsl: SEC driver cleanup for 64 bit and endianness
The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings will
be depend on endianness of SEC block as 32 bit low and
high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Stefan Brüns [Sun, 30 Aug 2015 15:59:45 +0000 (17:59 +0200)]
smsc95xx: Fetch whole burst with 1 URB, avoid framing errors
smsc95xx_recv() does not reassemble bursts spread over multiple URBs.
If there is a lot of broadcast traffic, the fifo will fill up to the
burst cap limit. Lowering the burst cap to the URB size ensures no packet
spans multiple urbs.
Caveat, lower limit for working burst cap is 5/33 HS/FS packets.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stefan Brüns [Sun, 30 Aug 2015 15:47:17 +0000 (17:47 +0200)]
net: cancel timeout handler after DHCPACK
Timeout handler should be stopped after reception of DHCPACK. If "autoload"
is not set, the handler is immediately replaced by the TFTP handler,
otherwise it may trigger before the next boot stage begins.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stefan Brüns [Sun, 30 Aug 2015 15:46:54 +0000 (17:46 +0200)]
net/arp: account for ARP delay, avoid duplicate packets on timeout
eth_rx() in the main reception loop may trigger sending a packet which
is already timed out (or will immediately) upon reception of an ARP reply.
As long as the ARP reply is pending, the timeout handler of a packet
should be postponed.
Happens on TFTP with bad network (e.g. WLAN).
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stefan Brüns [Thu, 27 Aug 2015 21:57:18 +0000 (23:57 +0200)]
net: send RFC1542 compliant value for bootp requests
RFC1542, 3.2:
"The 'secs' field of a BOOTREQUEST message SHOULD represent the
elapsed time, in seconds, since the client sent its first BOOTREQUEST
message. Note that this implies that the 'secs' field of the first
BOOTREQUEST message SHOULD be set to zero."
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stefan Brüns [Thu, 27 Aug 2015 21:53:26 +0000 (23:53 +0200)]
net: reject Bootp/DHCP packets with bad OP value
Rename check_packet to check_reply_packet to make its function more
obvious.
The check for DHCP_* values is completely off, as it should
compare against DHCP option 53 (Message Type). Only valid value for
any Bootp/DHCP reply is BOOTREPLY.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
TFTP source and destination port variable names are
'tftpsrcp' and 'tftpdstp' in the code, but 'tftpsrcport'
and 'tftpdstport' in the README file. Fix the README.
Add environment variable 'tftptimeoutcountmax'. As per the
comments about the global variable tftp_timeout_count_max,
make sure tftptimeoutcountmax is nonnegative.
Introduce configuration option CONFIG_NET_TFTP_VARS,
which controls whether environment variables tftpblocksize,
tftptimeout, and tftptimoueoutcountmax are read by the TFTP
client code. CONFIG_NET_TFTP_VARS defaults to y but can be
set to n by targets with to tight size contraints.
Make bf527-ezkit set CONFIG_NET_TFTP_VARS to n to keep the
target size below limit.
Jagan Teki [Tue, 27 Oct 2015 17:39:56 +0000 (23:09 +0530)]
spi: altera_spi: Use BIT macro
Replace numerical bit shift with BIT macro
in altera_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Marek Vasut <marex@denx.de> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Tom Rini [Tue, 27 Oct 2015 23:04:40 +0000 (19:04 -0400)]
image.c: Fix non-Android booting with ramdisk and/or device tree
In 1fec3c5 I added a check that if we had an Android image we default to
trying the kernel address for a ramdisk. However when we don't have an
Android image buf is NULL and we oops here. Ensure that we have 'buf'
to check first.
Reported-by: elipe Balbi <balbi@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Jagan Teki [Thu, 22 Oct 2015 19:31:36 +0000 (01:01 +0530)]
spi: designware_spi: Use GENMASK
Replace numeric mask hexcodes with GENMASK macro
in designware_spi
Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Thu, 22 Oct 2015 20:09:06 +0000 (01:39 +0530)]
spi: tegra: Use BIT macro
Replace numerical bit shift with BIT macro
in tegra*.c
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Warren <twarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Thu, 22 Oct 2015 20:07:18 +0000 (01:37 +0530)]
spi: fsl: Use BIT macro
Replace numerical bit shift with BIT macro
in fsl_*spi.c
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: York Sun <yorksun@freescale.com> Cc: Haikun Wang <Haikun.Wang@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Thu, 22 Oct 2015 20:06:23 +0000 (01:36 +0530)]
spi: designware_spi: Use BIT macro
Replace numerical bit shift with BIT macro
in designware_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Thu, 22 Oct 2015 20:06:06 +0000 (01:36 +0530)]
spi: cadence_qspi_apb: Use BIT macro
Replace numerical bit shift with BIT macro
in cadence_qspi_apb
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Tom Rini [Sat, 24 Oct 2015 21:24:07 +0000 (17:24 -0400)]
ocotea: Drop
This board has not compiled for me for quite some time due to size
constraints, remove.
Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
projects / u-boot.git / log