]> git.dujemihanovic.xyz Git - u-boot.git/log
u-boot.git
3 years agoriscv: ae350: Switch to use binman to generate u-boot.itb
Bin Meng [Mon, 10 May 2021 12:23:40 +0000 (20:23 +0800)]
riscv: ae350: Switch to use binman to generate u-boot.itb

Use the new BINMAN_STANDALONE_FDT option for AE350 based SPL defconfigs,
so that binman is now used to generate u-boot.itb.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
3 years agoriscv: qemu: Switch to use binman to generate u-boot.itb
Bin Meng [Mon, 10 May 2021 12:23:39 +0000 (20:23 +0800)]
riscv: qemu: Switch to use binman to generate u-boot.itb

By utilizing the newly introduced BINMAN_STANDALONE_FDT option, along
with a new dedicated device tree source file for the QEMU virt target
used for binman only, we can now use binman to generate u-boot.itb.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoriscv: dts: Sort build targets in alphabetical order
Bin Meng [Mon, 10 May 2021 12:23:38 +0000 (20:23 +0800)]
riscv: dts: Sort build targets in alphabetical order

Sort the RISC-V DTS build targets by their Kconfig target names in
alphabetical order.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agobinman: Support packaging U-Boot for scenarios like OF_BOARD or OF_PRIOR_STAGE
Bin Meng [Mon, 10 May 2021 12:23:37 +0000 (20:23 +0800)]
binman: Support packaging U-Boot for scenarios like OF_BOARD or OF_PRIOR_STAGE

For scenarios like OF_BOARD or OF_PRIOR_STAGE, no device tree blob is
provided in the U-Boot build phase hence the binman node information
is not available. In order to support such use case, a new Kconfig
option BINMAN_STANDALONE_FDT is introduced, to tell the build system
that a device tree blob containing binman node is explicitly required
when using binman to package U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agolib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED
Bin Meng [Mon, 10 May 2021 12:23:36 +0000 (20:23 +0800)]
lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED

Generally speaking BINMAN_FDT makes sense for OF_SEPARATE or OF_EMBED.
For the other OF_CONTROL methods, it's quite possible binman node is
not available as binman is invoked during the build phase instead of
runtime. Let's only turn it on for OF_SEPARATE or OF_EMBED by default.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoriscv: sifive: unleashed: Switch to use binman to generate u-boot.itb
Bin Meng [Mon, 10 May 2021 12:23:35 +0000 (20:23 +0800)]
riscv: sifive: unleashed: Switch to use binman to generate u-boot.itb

At present SiFive Unleashed board uses the Makefile to create the FIT,
using USE_SPL_FIT_GENERATOR, which is deprecated as per the Makefile
warning. Update to use binman instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agomakefile: Pass OpenSBI blob to binman make rules
Bin Meng [Mon, 10 May 2021 12:23:34 +0000 (20:23 +0800)]
makefile: Pass OpenSBI blob to binman make rules

This updates the make rules to pass OpenSBI blob to binman.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agobinman: Add support for RISC-V OpenSBI fw_dynamic blob
Bin Meng [Mon, 10 May 2021 12:23:33 +0000 (20:23 +0800)]
binman: Add support for RISC-V OpenSBI fw_dynamic blob

Add an entry for RISC-V OpenSBI's 'fw_dynamic' firmware payload.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
3 years agobinman: test: Rename 172_fit_fdt.dts to 170_fit_fdt.dts
Bin Meng [Mon, 10 May 2021 12:23:32 +0000 (20:23 +0800)]
binman: test: Rename 172_fit_fdt.dts to 170_fit_fdt.dts

Currently there are 2 binman test cases using the same 172 number.
It seems that 172_fit_fdt.dts was originally named as 170_, but
commit c0f1ebe9c1b9 ("binman: Allow selecting default FIT configuration")
changed its name to 172_ for no reason. Let's change it back.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agobinman: Correct the comment for ATF entry type
Bin Meng [Mon, 10 May 2021 12:23:31 +0000 (20:23 +0800)]
binman: Correct the comment for ATF entry type

This is wrongly referring to Intel ME, which should be ATF.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agobinman: Correct '-a' description in the doc
Bin Meng [Mon, 10 May 2021 12:23:30 +0000 (20:23 +0800)]
binman: Correct '-a' description in the doc

It needs a space around '-a'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
3 years agocommon: kconfig: Correct a typo in SPL_LOAD_FIT
Bin Meng [Mon, 10 May 2021 12:23:29 +0000 (20:23 +0800)]
common: kconfig: Correct a typo in SPL_LOAD_FIT

It should be FDT, not FTD.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
3 years agoMerge branch '2021-05-17-assorted-fixes'
Tom Rini [Tue, 18 May 2021 18:17:54 +0000 (14:17 -0400)]
Merge branch '2021-05-17-assorted-fixes'

3 years agoMerge tag 'efi-2021-07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Tom Rini [Tue, 18 May 2021 15:10:00 +0000 (11:10 -0400)]
Merge tag 'efi-2021-07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2021-07-rc3

Documentation:

* add a man-page for the size command
* add man-page for extension command to index

Bug fixes:

* avoid build failure due to missing SHA512 hardware acceleration
* correct error handling in TCG2 protocol
* don't let user disable capsule authentication
* correct reading directories via UEFI API

3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-riscv
Tom Rini [Tue, 18 May 2021 15:09:41 +0000 (11:09 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

3 years agolib: introduce HASH_CALCULATE option
Masahisa Kojima [Thu, 13 May 2021 14:48:08 +0000 (23:48 +0900)]
lib: introduce HASH_CALCULATE option

Build error occurs when CONFIG_EFI_SECURE_BOOT or
CONFIG_EFI_CAPSULE_AUTHENTICATE is enabled,
because hash-checksum.c is not compiled.

Since hash_calculate() implemented in hash-checksum.c can be
commonly used aside from FIT image signature verification,
this commit itroduces HASH_CALCULATE option to decide
if hash-checksum.c shall be compiled.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: Fix Kconfig for EFI_TCG2 protocol
Ilias Apalodimas [Tue, 11 May 2021 11:40:58 +0000 (14:40 +0300)]
efi_loader: Fix Kconfig for EFI_TCG2 protocol

EFI_TCG2 depends not only on TPMv2 but also on the underlying algorithms.
So select the missing SHA1, SHA256, SHA384 and SHA512 we currently support

Reported-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Add 'default y'.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: Don't stop EFI subsystem init if installing TCG2 fails
Ilias Apalodimas [Tue, 11 May 2021 21:03:41 +0000 (00:03 +0300)]
efi_loader: Don't stop EFI subsystem init if installing TCG2 fails

Up to now we are stopping the EFI subsystem if a TPMv2 exists but the
protocol fails to install.  Now that we've switched the config to 'default
y' the sandbox TPM fails, since it doesn't support all the required
capabilities of the protocol.

Not installing the protocol is not catastrophic.  If the protocol fails
to install the PCRs will never be extended to the expected values, so
some other entity later in the boot flow will eventually figure it out
and take the necessary actions.

While at it fix a corner case were the user can see an invalid error
message when the protocol failed to install.  We do have a tcg2_uninit()
which we call when the protocol installation fails.  There are cases though
that this might be called before the configuration table is installed (e.g
probing the TPM for capabilities failed).  In that case the user will see
"Failed to delete final events config table".  So stop printing it since it's
not an actual failure , simply because the config table was never installed
in the first place.

In order to stop printing it make efi_init_event_log() and create_final_event()
cleanup themselves and only call tcg2_uninit() when the protocol installation
fails.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: Uninstall the TCG2 protocol if logging s-crtm fails
Ilias Apalodimas [Mon, 10 May 2021 18:19:14 +0000 (21:19 +0300)]
efi_loader: Uninstall the TCG2 protocol if logging s-crtm fails

Instead of just failing, clean up the installed config table and
EventLog memory if logging an s-crtm event fails during the protocol
installation

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Eliminate label 'out:' by using return.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: Clean up tcg2 once in case of failure
Ilias Apalodimas [Mon, 10 May 2021 18:15:08 +0000 (21:15 +0300)]
efi_loader: Clean up tcg2 once in case of failure

efi_init_event_log() calls tcg2_uninit() in case of failure.
We can skip that since the function is called on efi_tcg2_register()
which also cleans up if an error occurs

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: loosen buffer parameter check in efi_file_read_int
Peng Fan [Wed, 28 Apr 2021 13:54:01 +0000 (21:54 +0800)]
efi_loader: loosen buffer parameter check in efi_file_read_int

This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
but that fix was wrongly partial reverted.

When reading a directory, EFI_BUFFER_TOO_SMALL should be returned when
the supplied buffer is too small, so a use-case is to call
EFI_FILE_PROTOCOL.Read() with *buffer_size=0 and buffer=NULL to
obtain the needed size before doing the actual read.

So remove the check only for directory reading, file reading already
do the check by itself.

Fixes: db12f518edb0("efi_loader: implement non-blocking file services")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefan Sørensen <stefan.sorensen@spectralink.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: capsule: Remove the check for capsule_authentication_enabled environment...
Sughosh Ganu [Mon, 12 Apr 2021 15:05:23 +0000 (20:35 +0530)]
efi_loader: capsule: Remove the check for capsule_authentication_enabled environment variable

The current capsule authentication code checks if the environment
variable capsule_authentication_enabled is set, for authenticating the
capsule. This is in addition to the check for the config symbol
CONFIG_EFI_CAPSULE_AUTHENTICATE. Remove the check for the environment
variable. The capsule will now be authenticated if the config symbol
is set.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviwed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agohash: Kconfig option for SHA512 hardware acceleration
Heinrich Schuchardt [Fri, 14 May 2021 05:08:27 +0000 (07:08 +0200)]
hash: Kconfig option for SHA512 hardware acceleration

Commit a479f103dc1c ("hash: Allow for SHA512 hardware implementations")
defined function definitions for hardware accelerated SHA384 and SHA512.
If CONFIG_SHA_HW_ACCEL=y, these functions are used.

We already have boards using CONFIG_SHA_HW_ACCEL=y but none implements the
new functions hw_sha384() and hw_sha512().

For implementing the EFI TCG2 protocol we need SHA384 and SHA512. The
missing hardware acceleration functions lead to build errors on boards like
peach-pi_defconfig.

Introduce a new Kconfig symbol CONFIG_SHA512_HW_ACCEL to control if the
functions hw_sha384() and hw_sha512() shall be used to implement the SHA384
and SHA512 algorithms.

Fixes: a479f103dc1c ("hash: Allow for SHA512 hardware implementations")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoefi_loader: build warning in efi_tcg2_hash_log_extend_event
Heinrich Schuchardt [Wed, 12 May 2021 15:37:20 +0000 (17:37 +0200)]
efi_loader: build warning in efi_tcg2_hash_log_extend_event

Building 32bit boards with the TCG2 protocol enabled leads to a build
warning due to a missing conversion.

    lib/efi_loader/efi_tcg2.c:774:27:
    error: cast to pointer from integer of different size
    [-Werror=int-to-pointer-cast]
    774 |  ret = tcg2_create_digest((u8 *)data_to_hash, data_to_hash_len,
        |                           ^

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
3 years agodoc: extension.rst missing in doc/usage/index.rst
Heinrich Schuchardt [Sat, 15 May 2021 22:34:28 +0000 (00:34 +0200)]
doc: extension.rst missing in doc/usage/index.rst

'make htmldocs' results in a build warning

    checking consistency... doc/usage/extension.rst:
    WARNING: document isn't included in any toctree

Add the document to the index.

Fixes: 2f84e9cf06d3 ("cmd: add support for a new "extension" command")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agodoc: man-page for size command
Heinrich Schuchardt [Sat, 15 May 2021 11:08:57 +0000 (13:08 +0200)]
doc: man-page for size command

Provide a man-page for the size command.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoMAINTAINERS, git-mailrc: socfpga: Update email address for Ley Foon
Ley Foon Tan [Wed, 12 May 2021 10:31:57 +0000 (18:31 +0800)]
MAINTAINERS, git-mailrc: socfpga: Update email address for Ley Foon

My mail address doesn't work any longer, change to gmail.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
3 years agoMakefile: Handle building in a very old build directory
Simon Glass [Fri, 7 May 2021 01:32:23 +0000 (19:32 -0600)]
Makefile: Handle building in a very old build directory

Versions of U-Boot before 2014.01 created a symlink from include/asm to
the architecture-specific header directory.

If an ARM board is build with that old version, then sandbox is built on
a more recent version (both with in-tree builds), the include/asm symlink
confuses the build system. It picks up the ARM headers when it should be
using the sandbox ones.

Since 2014 U-Boot has only created a symlink inside the include/asm/
directory and only for out-of-tree builds. So for in-tree builds it does
not expect to see an include/asm symlink. It is not removed by
'make mrproper'. It does show up with 'git status' but is easy enough to
miss.

Add include/asm to the files to remove with 'make mkproper'. For recent
U-Boot builds this has no effect, since include/asm is a directory, not a
file. If the include/asm symlink is there, it will be removed.

Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agopsci: rename psci_features function
Igor Opaniuk [Thu, 6 May 2021 14:34:27 +0000 (17:34 +0300)]
psci: rename psci_features function

s/psci_features/request_psci_features/g for the case when both
ARCH_SUPPORT_PSCI=y and ARM_PSCI_FW=y, that leads to these
compilation issues:

drivers/firmware/psci.c:69:12: error: conflicting types for 'psci_features'
   69 | static int psci_features(u32 psci_func_id)
      |            ^~~~~~~~~~~~~
In file included from drivers/firmware/psci.c:23:
./arch/arm/include/asm/system.h:548:5: note: previous declaration of 'psci_features' was here
  548 | s32 psci_features(u32 function_id, u32 psci_fid);
      |     ^~~~~~~~~~~~~

Tested-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Fixes: b7135b034f ("psci: add features/reset2 support")
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
3 years agocli: slighly more clear error messages
peng.wang@smartm.com [Tue, 4 May 2021 08:45:59 +0000 (01:45 -0700)]
cli: slighly more clear error messages

This patch tries to distinguish two error messages.

Signed-off-by: peng.wang@smartm.com <peng.wang@smartm.com>
3 years agoMakefile: allow to override python3
Andrey Zhizhikin [Sat, 1 May 2021 20:12:21 +0000 (22:12 +0200)]
Makefile: allow to override python3

Python3 taken from the PATH causes build issues when pylibfdt bindings are
generated with Yocto SDK.

Python3 provided as a part of SDK is not compatible with host Python3,
therefore binding build breaks with following errors:

scripts/dtc/pylibfdt/libfdt_wrap.c:154:11: fatal error: Python.h: No such file or directory
  154 | # include <Python.h>
      |           ^~~~~~~~~~

Do not enforce the python3 from the PATH and make it conditionally-assigned
so it can be overridden from outside of build system. Keep the default
assignment to point to version that is taken from the PATH.

Similar fix has been introduced in b48bfc74ee ("tools: allow to override
python"), where conditional assignment is used for python executable to
address similar build errors.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Simon Glass <sjg@chromium.org>
Fixes: e91610da7c ("kconfig: re-sync with Linux 4.17-rc4")
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-marvell
Tom Rini [Mon, 17 May 2021 14:01:56 +0000 (10:01 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- Add base support for Marvell OcteonTX2 CN9130 DB (mostly done
  by Kostya)
- Sync Armada 8k MMU setup with Marvell version (misc Marvell
  authors)
- spi: kirkwood: Some fixes especially for baudrate generation
  (misc Marvell authors)
- mvebu: x530: Reduce SPL image size (Stefan)
- Rename "rx_training" to "mvebu_comphy_rx_training" (Stefan)

3 years agoriscv: Group assembly optimized implementation of memory routines into a submenu
Bin Meng [Thu, 13 May 2021 08:46:18 +0000 (16:46 +0800)]
riscv: Group assembly optimized implementation of memory routines into a submenu

Currently all assembly optimized implementation of memory routines
show up at the top level of the RISC-V architecture Kconfig menu.
Let's group them together into a submenu.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
3 years agoriscv: Fix memmove and optimise memcpy when misalign
Bin Meng [Thu, 13 May 2021 08:46:17 +0000 (16:46 +0800)]
riscv: Fix memmove and optimise memcpy when misalign

At present U-Boot SPL fails to boot on SiFive Unleashed board, due
to a load address misaligned exception happens when loading the FIT
image in spl_load_simple_fit(). The exception happens in memmove()
which is called by fdt_splice_().

Commit 8f0dc4cfd106 introduces an assembly version of memmove but
it does take misalignment into account (it checks if length is a
multiple of machine word size but pointers need also be aligned).
As a result it will generate misaligned load/store for the majority
of cases and causes significant performance regression on hardware
that traps misaligned load/store and emulate them using firmware.

The current behaviour of memcpy is that it checks if both src and
dest pointers are co-aligned (aka congruent modular SZ_REG). If
aligned, it will copy data word-by-word after first aligning
pointers to word boundary. If src and dst are not co-aligned,
however, byte-wise copy will be performed.

This patch was taken from the Linux kernel patch [1], which has not
been applied at the time being. It fixes the memmove and optimises
memcpy for misaligned cases. It will first align destination pointer
to word-boundary regardless whether src and dest are co-aligned or
not. If they indeed are, then wordwise copy is performed. If they
are not co-aligned, then it will load two adjacent words from src
and use shifts to assemble a full machine word. Some additional
assembly level micro-optimisation is also performed to ensure more
instructions can be compressed (e.g. prefer a0 to t6).

With this patch, U-Boot boots again on SiFive Unleashed board.

[1] https://patchwork.kernel.org/project/linux-riscv/patch/20210216225555.4976-1-gary@garyguo.net/

Fixes: 8f0dc4cfd106 ("riscv: assembler versions of memcpy, memmove, memset")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
3 years agoriscv: Fix arch_fixup_fdt always failing without /chosen
Sean Anderson [Sat, 15 May 2021 02:36:16 +0000 (22:36 -0400)]
riscv: Fix arch_fixup_fdt always failing without /chosen

If /chosen was missing, chosen_offset would never get updated with the new
/chosen node. This would cause fdt_setprop_u32 to fail. This patch fixes
this by setting chosen_offset. In addition, log any errors from setting
boot-hartid as well.

Fixes: 5370478d1c7 ("riscv: Add boot hartid to device tree")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
3 years agoriscv: Split SiFive CLINT support between SPL and U-Boot proper
Bin Meng [Tue, 11 May 2021 12:04:12 +0000 (20:04 +0800)]
riscv: Split SiFive CLINT support between SPL and U-Boot proper

At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.

This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.

To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
3 years agoriscv: ax25-ae350: doc: Fix minor format issues
Bin Meng [Wed, 12 May 2021 15:25:52 +0000 (23:25 +0800)]
riscv: ax25-ae350: doc: Fix minor format issues

This fixes two minor format issues of the ax25-ae350 reST file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-usb
Tom Rini [Sun, 16 May 2021 22:06:26 +0000 (18:06 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-usb

3 years agousb: dwc3-generic: Disable host driver definition if gadget only
Kunihiko Hayashi [Wed, 12 May 2021 14:11:14 +0000 (23:11 +0900)]
usb: dwc3-generic: Disable host driver definition if gadget only

Even if only USB gadget is defined, dwc3 generic driver enables
a definition and probe/remove functions for host driver.

This enables the definition if USB_HOST is enabled only.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
3 years agousb: musb-new: Extend and move Allwinner quirk into Kconfig
Andre Przywara [Wed, 5 May 2021 12:51:03 +0000 (13:51 +0100)]
usb: musb-new: Extend and move Allwinner quirk into Kconfig

All newer Allwinner SoCs (since about 2013) miss the CONFIGDATA register
in their MUSB implementation, so they need a quirk to hardcode this.

Currently this quirk depends on listing the SoCs affected in musb_reg.h,
which means that this list needs to grow with every new chip.

Move the quirk feature into Kconfig, next to PIO_ONLY, and change the
default to y (for Allwinner builds), while listing the early
implementations as exceptions.

This fixes USB peripheral operation on some newer SoCs, which were not
explicitly listed before.

Tested on H6, H616, R40 (which were broken before), and also on the H5
and A20, for regressions.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
3 years agoarm: octeontx2: Add Octeon TX2 CN913x DB support
Konstantin Porotchkin [Tue, 11 May 2021 06:11:25 +0000 (08:11 +0200)]
arm: octeontx2: Add Octeon TX2 CN913x DB support

This patch adds the base support for the Marvell Octeon TX2 CN913x DB.
Only one defconfig is added with this patch. Other board variants are
available (NAND, MMC booting) and images for these boards can be
generated by following the documentation added in the included README.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agoarm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DB
Konstantin Porotchkin [Tue, 11 May 2021 06:11:24 +0000 (08:11 +0200)]
arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DB

This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN913x DB. This is only the base port with not all
interfaces supported fully.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agocmd: mvebu: Rename rx_training to mvebu_comphy_rx_training
Stefan Roese [Wed, 5 May 2021 07:15:10 +0000 (09:15 +0200)]
cmd: mvebu: Rename rx_training to mvebu_comphy_rx_training

Rename the misleading cmd "rx_training" to "mvebu_comphy_rx_training" to
avoid confusion and mixup with DDR3/4 training. This makes it clear,
that this command is platform specific and handles the COMPHY RX
training.

Also depend this cmd on ARMADA_8K and not TARGET_MVEBU_ARMADA_8K to make
is available for OcteonTX2 CN913x.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pali Rohár <pali@kernel.org>
Cc: Marek Behun <marek.behun@nic.cz>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Marek Behún <marek.behun@nic.cz>
Acked-by: Pali Rohár <pali@kernel.org>
3 years agopcie: designware: mvebu: do not configure ATU for IO when not used
Marcin Wojtas [Fri, 30 Apr 2021 13:33:15 +0000 (15:33 +0200)]
pcie: designware: mvebu: do not configure ATU for IO when not used

The pcie_dw_mvebu configure ATU regions for memory, configuration
and IO space types. However the latter is not obligatory
and when not specified in the device tree, causes wrong
ATU configuration. Fix that by adding a dependency on the
detected PCIE regions count.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/18136
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
3 years agoarm64: mvebu: extend the mmio region
Grzegorz Jaszczyk [Fri, 30 Apr 2021 13:29:50 +0000 (15:29 +0200)]
arm64: mvebu: extend the mmio region

Some of the setups including cn9130 opens mmio window starting from
0xc0000000, reflect it in the u-boot code.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agoarm64: mvebu: a8k: move firmware related definitions to fw info
Grzegorz Jaszczyk [Fri, 30 Apr 2021 13:29:49 +0000 (15:29 +0200)]
arm64: mvebu: a8k: move firmware related definitions to fw info

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agoarm64: mvebu: do not map firmware RT service region
Grzegorz Jaszczyk [Fri, 30 Apr 2021 13:29:48 +0000 (15:29 +0200)]
arm64: mvebu: do not map firmware RT service region

There is region left by ATF, which needs to remain in memory to provide RT
services. To prevent overwriting it by u-boot, do not provide any mapping
for this memory region, so any attempt to access it will trigger
synchronous exception.

Update sr 2021-04-12:
Don't update armada3700/cpu.c mmu table, as this has specific changes
included in mainline.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agoarm64: mvebu: a8k: align memory regions
jinghua [Fri, 30 Apr 2021 13:29:47 +0000 (15:29 +0200)]
arm64: mvebu: a8k: align memory regions

1. RAM: base address 0x0 size 2Gbytes
2. MMIO: base address 0xf0000000 size 1Gbytes

Signed-off-by: Ofir Fedida <ofedida@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agospi: kirkwood: prevent limiting speed to 0
Grzegorz Jaszczyk [Fri, 30 Apr 2021 13:26:31 +0000 (15:26 +0200)]
spi: kirkwood: prevent limiting speed to 0

After commit 1fe929ed497bcc8975be8d37383ebafd22b99dd2
("spi: kirkwood: prevent configuring speed exceeding max controller freq")
the spi frequency could be set to 0 on platform where spi-max-frequency
is not defined (e.g. on armada-388-gp). Prevent limiting speed in
mentioned cases.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Marcin Wojtas <marcin@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agospi: kirkwood: prevent configuring speed exceeding max controller freq
Marcin Wojtas [Fri, 30 Apr 2021 13:26:30 +0000 (15:26 +0200)]
spi: kirkwood: prevent configuring speed exceeding max controller freq

This patch adds a limitation in the kirkwood_spi driver
set_speed hook, which prevents setting too high transfer
speed.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agospi: kirkwood: support extended baud rates
Ken Ma [Fri, 30 Apr 2021 13:26:29 +0000 (15:26 +0200)]
spi: kirkwood: support extended baud rates

The Armada SoC family implementation of this SPI hardware module has
extended the configuration register to allow for a wider range of SPI
clock rates. Specifically the Serial Baud Rate Pre-selection bits in the
SPI Interface Configuration Register now also use bits 6 and 7 as well.

Modify the baud rate calculation to handle these differences for the
Armada case. Potentially a baud rate can be setup using a number of
different pre-scalar and scalar combinations. This code tries all
possible pre-scalar divisors (8 in total) to try and find the most
accurate set.

Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomvebu: x530: Reduce SPL image size
Stefan Roese [Wed, 12 May 2021 07:18:37 +0000 (09:18 +0200)]
mvebu: x530: Reduce SPL image size

Currently, building U-Boot for x530 fails since the SPL image is too
big. This patch reduces the SPL size by changing the following Kconfig
options:

Enable CONFIG_SPL_TINY_MEMSET
Disable CONFIG_SPI_FLASH_BAR

By disabling CONFIG_SPI_FLASH_BAR, the tiny SPI NOR framework can be
used.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Pratyush Yadav <p.yadav@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
3 years agoconfigs: Resync with savedefconfig
Tom Rini [Sat, 15 May 2021 12:10:13 +0000 (08:10 -0400)]
configs: Resync with savedefconfig

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-sh
Tom Rini [Sat, 15 May 2021 03:00:24 +0000 (23:00 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-sh

3 years agoMerge tag 'u-boot-amlogic-20210514' of https://source.denx.de/u-boot/custodians/u...
Tom Rini [Sat, 15 May 2021 02:59:59 +0000 (22:59 -0400)]
Merge tag 'u-boot-amlogic-20210514' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro
- usb: dwc3-meson-g12a: skip phy on -ENODATA aswell
- net: dwmac_meson8b: do not set TX delay in TXID & RXID
- net: designware: meson8b: add g12a compatible

3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-riscv
Tom Rini [Sat, 15 May 2021 02:59:48 +0000 (22:59 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

3 years agonet: designware: meson8b: add g12a compatible
Neil Armstrong [Fri, 16 Apr 2021 12:52:06 +0000 (14:52 +0200)]
net: designware: meson8b: add g12a compatible

Add support for the Meson G12A dwmac glue compatible needed after Linux 5.12 sync.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agonet: dwmac_meson8b: do not set TX delay in TXID & RXID
Neil Armstrong [Wed, 5 May 2021 07:52:08 +0000 (09:52 +0200)]
net: dwmac_meson8b: do not set TX delay in TXID & RXID

When the PHY interface is set as TXID & RXID, the delays should be taken from DT,
but first they should not be hardcoded since the PHY driver will set them.

Fixes: 798424e857 ("net: designware: add Amlogic Meson8b & later glue driver")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
3 years agousb: dwc3-meson-g12a: skip phy on -ENODATA aswell
Neil Armstrong [Wed, 5 May 2021 08:38:57 +0000 (10:38 +0200)]
usb: dwc3-meson-g12a: skip phy on -ENODATA aswell

If the PHY isn't specified in the DT, -ENODATA means it should be skipped,
handle it like -ENOENT.

With that, devices without USB3 supported can have USB working (Odroid-HC4).

Fixes: adb049abf7 ("usb: dwc3: Add Meson G12A USB Glue")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoARM: dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro
Neil Armstrong [Tue, 20 Apr 2021 08:45:56 +0000 (10:45 +0200)]
ARM: dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro

This lacks the right u-boot specific DT include to make HDMI work.

Reported-by: B1oHazard <ty3uk@mail.ua>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoRevert "riscv: cpu: fu740: clear feature disable CSR"
Bin Meng [Mon, 10 May 2021 09:08:16 +0000 (17:08 +0800)]
Revert "riscv: cpu: fu740: clear feature disable CSR"

This reverts commit bc8bbb77f74f21582b3bfd790334397757f88575.

This commit breaks U-Boot booting on SiFive Unleashed board, as
there is no such CSR on U54 core.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
3 years agopwm: sifive: make set_config() and set_enable() work properly
Vincent Chen [Mon, 3 May 2021 07:26:49 +0000 (15:26 +0800)]
pwm: sifive: make set_config() and set_enable() work properly

The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work
properly due to the wrong implementations. It will cause the u-boot
PWM command to not work as expected. The bugs will be resolved in this
patch.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
3 years agoriscv: Don't reserve AI ram in k210 dts
Sean Anderson [Fri, 9 Apr 2021 02:13:13 +0000 (22:13 -0400)]
riscv: Don't reserve AI ram in k210 dts

It is no longer necessary to disallow ai ram, since it is enabled by the
sram driver.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoriscv: k210: Use AI as the parent clock of aisram, not PLL1
Sean Anderson [Fri, 9 Apr 2021 02:13:12 +0000 (22:13 -0400)]
riscv: k210: Use AI as the parent clock of aisram, not PLL1

Testing showed that disabling AI while leaving PLL1 enabled disabled the
aisram. This suggests that AI is a more appropriate clock for that ram
bank.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoriscv: k210: Rename airam to aisram
Sean Anderson [Fri, 9 Apr 2021 02:13:11 +0000 (22:13 -0400)]
riscv: k210: Rename airam to aisram

This is more consistent with the naming of other ram banks, and matches
what Linux is doing.

Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoriscv: Enable AI ram on K210
Sean Anderson [Fri, 9 Apr 2021 02:13:10 +0000 (22:13 -0400)]
riscv: Enable AI ram on K210

We just need to initialize all the clocks pre-reloc. The clock driver
creates a bunch of devices, so we need to increase the pre-reloc malloc
arena.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoriscv: Enable some devices pre-relocation
Sean Anderson [Fri, 9 Apr 2021 02:13:09 +0000 (22:13 -0400)]
riscv: Enable some devices pre-relocation

These devices are necessary for the clock driver, which is required by the
sram driver, to run pre-relocation.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoclk: Add support for the k210 clock driver pre-relocation
Sean Anderson [Fri, 9 Apr 2021 02:13:08 +0000 (22:13 -0400)]
clk: Add support for the k210 clock driver pre-relocation

Variables which had previously been stored in .bss are moved to .data. In
addition, probed needs to be reset when the clock driver is re-bound
post-relocation.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoclk: k210: Move the clint clock to under aclk
Sean Anderson [Fri, 9 Apr 2021 02:13:07 +0000 (22:13 -0400)]
clk: k210: Move the clint clock to under aclk

No other (real) clocks have the cpu clock as their parent; instead they are
children of aclk. Move the clint clock under aclk to match them.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoclk: k210: Remove k210_register_pll
Sean Anderson [Fri, 9 Apr 2021 02:13:06 +0000 (22:13 -0400)]
clk: k210: Remove k210_register_pll

This simplifies the PLL creation process, since we don't have to pass all
the parameters individually.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoclk: k210: Fix PLL enable always getting taken
Sean Anderson [Fri, 9 Apr 2021 02:13:05 +0000 (22:13 -0400)]
clk: k210: Fix PLL enable always getting taken

This conditional always evaluated as false, regardless of the value of reg.
Fix it so that it properly tests the bits in the PLL register. Also test
PLL_EN, now that we set it.

Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoclk: k210: Fix PLLs not being enabled
Sean Anderson [Fri, 9 Apr 2021 02:13:04 +0000 (22:13 -0400)]
clk: k210: Fix PLLs not being enabled

After starting or setting the rate of a PLL, the enable bit must be set.

This fixes a bug where the AI ram would not be accessible, because it
requires PLL1 to be running.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Damien Le Moal <damien.lemoal@wdc.com>
3 years agoclk: Warn on failure to assign rate
Sean Anderson [Fri, 9 Apr 2021 02:13:03 +0000 (22:13 -0400)]
clk: Warn on failure to assign rate

If the user/dev explicitly requests a clock be assigned a certain rate,
then we should warn them if we can't do it. This makes it clear if the
clock is running at the default rate.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoMAINTAINERS: Add a co-maintainer for RISC-V
Rick Chen [Mon, 25 Jan 2021 06:08:31 +0000 (14:08 +0800)]
MAINTAINERS: Add a co-maintainer for RISC-V

Add Leo as co-maintainer for RISC-V.

Signed-off-by: Rick Chen <rick@andestech.com>
3 years agoMerge branch '2021-05-13-extension-board-detection-and-DT-overlay-application'
Tom Rini [Thu, 13 May 2021 17:09:14 +0000 (13:09 -0400)]
Merge branch '2021-05-13-extension-board-detection-and-DT-overlay-application'

- Improve support for various forms of extension boards and add DT
  overlay application support.

3 years agoam335x: add support for cape detect functionality
Kory Maincent [Tue, 4 May 2021 17:31:30 +0000 (19:31 +0200)]
am335x: add support for cape detect functionality

Update the Kconfig and the board file to make the am335x board compatible
with cape detection.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
3 years agoarm: am335x: add support for i2c2 bus
Kory Maincent [Tue, 4 May 2021 17:31:29 +0000 (19:31 +0200)]
arm: am335x: add support for i2c2 bus

The am335x from BeagleBone use i2c EEPROM to detect capes.
The memory is wired to i2c bus 2 therefore it need to be enabled.

Add i2c2 clock, pinmux description and pinmux enable function.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
3 years agoconfigs: CHIP: add support for DIP detect functionality
Kory Maincent [Tue, 4 May 2021 17:31:28 +0000 (19:31 +0200)]
configs: CHIP: add support for DIP detect functionality

This commit enables using the extension board detection mechanism on
CHIP boards

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Acked-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Andre Przywara <andre.przywara@arm.com>
3 years agoarm: sunxi: add support for DIP detection to CHIP board
Kory Maincent [Tue, 4 May 2021 17:31:27 +0000 (19:31 +0200)]
arm: sunxi: add support for DIP detection to CHIP board

Add the extension_board_scan specific function to scan the information
of the EEPROM on one-wire and fill the extension struct.
Add the Kconfig symbol to enable the needs to detect DIPs.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Andre Przywara <andre.przywara@arm.com>
3 years agow1: replace dt detection by automatic detection
Kory Maincent [Tue, 4 May 2021 17:31:26 +0000 (19:31 +0200)]
w1: replace dt detection by automatic detection

This patch changes the functioning of the detection of w1 devices.
The old way was a comparison between detected w1 and the ones described in
the device tree. Now it will just look for the driver matching the family
id of the w1 detected.

The patch is inspired from Maxime Ripard code.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Maxime Ripard <maxime@cerno.tech>
3 years agoam57xx: add support for cape detect functionality
Kory Maincent [Tue, 4 May 2021 17:31:25 +0000 (19:31 +0200)]
am57xx: add support for cape detect functionality

This commit enables using the extension board detection mechanism on
AM57xx based platforms.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
3 years agoti/common: add support for extension_scan_board function
Kory Maincent [Tue, 4 May 2021 17:31:24 +0000 (19:31 +0200)]
ti/common: add support for extension_scan_board function

The BeagleBone platforms all use a common mechanism to discover and
identify extension boards (called "capes"): each extension board has an
I2C-connected EEPROM describing itself.

This patch implements a generic extension_scan_board() feature that can
be used by all BeagleBone platforms to read those I2C EEPROMs and fill
in the list of "extension" structures.

Following commits will enable this common logic on two BeagleBone
platforms.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
3 years agopytest: add sandbox test for "extension" command
Kory Maincent [Tue, 4 May 2021 17:31:23 +0000 (19:31 +0200)]
pytest: add sandbox test for "extension" command

This commit extends the sandbox to implement a dummy
extension_board_scan() function and enables the extension command in
the sandbox configuration. It then adds a test that checks the proper
functionality of the extension command by applying two Device Tree
overlays to the sandbox Device Tree.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
[trini: Limit to running on sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agocmd: add support for a new "extension" command
Kory Maincent [Tue, 4 May 2021 17:31:22 +0000 (19:31 +0200)]
cmd: add support for a new "extension" command

This patch adds a new "extension" command, which aims at detecting
extension boards connected to the hardware platform, and apply the
Device Tree overlays that describe the hardware present on those
extension boards.

In order to enable this mechanism, board-specific code must implement
the extension_board_scan() function that fills in a linked list of
"struct extension", each describing one extension board. In addition,
the board-specific code must select the SUPPORT_EXTENSION_SCAN Kconfig
boolean.

Based on this:

 - "extension scan" makes the generic code call the board-specific
   extension_board_scan() function to retrieve the list of detected
   extension boards.

 - "extension list" allows to list the detected extension boards.

 - "extension apply <number>|all" allows to apply the Device Tree
   overlay(s) corresponding to one, or all, extension boards

The latter requires two environment variables to exist and set one variable
to run:

 - extension_overlay_addr: the RAM address where to load the Device
   Tree overlays

 - extension_overlay_cmd: the U-Boot command to load one overlay.
   Indeed, the location and mechanism to load DT overlays is very setup
   specific.

 - extension_overlay_name: set by the command: the name of the DT which
   will be load during the execution.

When calling the command described in the extension_overlay_cmd
variable, the variable extension_overlay_name will be defined. So a
typical extension_overlay_cmd will look like this:

  extension_overlay_cmd=load mmc 0:1 $extension_overlay_addr /boot/$extension_overlay_name

Here is an example on how to use it:
=> run loadfdt
=> fdt addr $fdtaddr
=> setenv extension_overlay_addr 0x1000
=> setenv extension_overlay_cmd 'load mmc 0:1 ${extension_overlay_addr} /boot/${extension_overlay_name}'
=> extension scan
Found 1 extension board(s).
=> extension apply 0
519 bytes read in 3 ms (168.9 KiB/s)

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Maxime Ripard <maxime@cerno.tech>
3 years agofdt_support: move fdt_valid from cmd_fdt.c to fdt_support.c
Kory Maincent [Tue, 4 May 2021 17:31:21 +0000 (19:31 +0200)]
fdt_support: move fdt_valid from cmd_fdt.c to fdt_support.c

Move the fdt_valid function to fdt_support.
This changes allow to be able to test the validity of a devicetree in
other c files.

Update code syntax.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Maxime Ripard <maxime@cerno.tech>
3 years agoARM: renesas: Scrub duplicate memory nodes from DT on Gen3
Marek Vasut [Sat, 3 Apr 2021 14:58:49 +0000 (16:58 +0200)]
ARM: renesas: Scrub duplicate memory nodes from DT on Gen3

Scrub duplicate /memory@* node entries here. Some R-Car DTs might
contain multiple /memory@* nodes, however fdt_fixup_memory_banks()
either generates single /memory node or updates the first /memory
node. Any remaining memory nodes are thus potential duplicates.

However, it is not possible to delete all the memory nodes right
away, since some of those might not be DRAM memory nodes, but some
sort of other memory. Thus, delete only the memory nodes which are
in the R-Car3 DBSC ranges.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
3 years agoARM: rmobile: Add missing rcar-common/common.c to Beacon RZG2M kit
Marek Vasut [Wed, 12 May 2021 19:34:11 +0000 (21:34 +0200)]
ARM: rmobile: Add missing rcar-common/common.c to Beacon RZG2M kit

The rcar-common/common.c contains various common board functions shared
by all R-Car and RZG boards. This board is not compiling the file in, so
add it. This way, part of the board code can be de-duplicated too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
3 years agoMerge tag 'ti-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ti
Tom Rini [Wed, 12 May 2021 14:07:21 +0000 (10:07 -0400)]
Merge tag 'ti-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ti

- Initial support for AM64 EVM and SK
- K3 DDR driver unification for J7 and AM64 platforms.
- Minor fixes for TI clock driver

3 years agoARM: dts: k3-am642-sk: Add ethernet related DT nodes
Vignesh Raghavendra [Mon, 10 May 2021 14:36:13 +0000 (20:06 +0530)]
ARM: dts: k3-am642-sk: Add ethernet related DT nodes

Add CPSW related nodes for AM642 SK. There are two CPSW ports on the
board but U-Boot supports only the first port.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agoARM: dts: k3-am64-main: Add CPSW DT nodes
Vignesh Raghavendra [Mon, 10 May 2021 14:36:12 +0000 (20:06 +0530)]
ARM: dts: k3-am64-main: Add CPSW DT nodes

AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same
(based on kernel DT).

Disable second port as its by default set to ICSS usage on EVM.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agonet: ti: am65-cpsw-nuss: Add a new compatible for AM64
Vignesh Raghavendra [Mon, 10 May 2021 14:36:11 +0000 (20:06 +0530)]
net: ti: am65-cpsw-nuss: Add a new compatible for AM64

Add a new compatible to support AM64 SoC

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agonet: ti: am65-cpsw-nuss: Don't cache disabled port ID
Vignesh Raghavendra [Mon, 10 May 2021 14:36:10 +0000 (20:06 +0530)]
net: ti: am65-cpsw-nuss: Don't cache disabled port ID

Currently driver may end up caching disabled port ID as active
interface. Fix this by bailing out earlier in case port is marked
disabled in the DT.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agonet: ti: am65-cpsw-nuss: Prepare to support non primary ext port
Vignesh Raghavendra [Mon, 10 May 2021 14:36:09 +0000 (20:06 +0530)]
net: ti: am65-cpsw-nuss: Prepare to support non primary ext port

CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8)
Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port)
as preparation to allow any one of the 8 ports to be used as ethernet
interface in U-Boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agodma: ti: k3-udma: Add BCDMA and PKTDMA support
Vignesh Raghavendra [Mon, 10 May 2021 14:36:08 +0000 (20:06 +0530)]
dma: ti: k3-udma: Add BCDMA and PKTDMA support

Sync BCDMA and PKTDMA support from Kernel for AM64 SoC

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agodma: ti: k3-psil-am64: Add AM64 PSIL endpoint data
Vignesh Raghavendra [Mon, 10 May 2021 14:36:07 +0000 (20:06 +0530)]
dma: ti: k3-psil-am64: Add AM64 PSIL endpoint data

Add AM64 SoC specific channel mapping and endpoint data.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agodma: ti: k3-psil: Extend PSIL EP data extension for AM64
Vignesh Raghavendra [Mon, 10 May 2021 14:36:06 +0000 (20:06 +0530)]
dma: ti: k3-psil: Extend PSIL EP data extension for AM64

Extend PSIL EP data to include AM64 DMA specific information

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agodma: ti: k3-psil-am654: Drop unused PSIL EP static data
Vignesh Raghavendra [Mon, 10 May 2021 14:36:05 +0000 (20:06 +0530)]
dma: ti: k3-psil-am654: Drop unused PSIL EP static data

ICSSG Ethernet driver uses two src threads per port (one per slice).
Similarly CPSW uses one src thread.

Drop PSIL EP static data for other src threads in order to reduce
R5 SPL footprint. This makes AM65x board bootable again.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agosoc: ti: k3-navss-ringacc: Remove unused ring modes
Vignesh Raghavendra [Mon, 10 May 2021 14:36:04 +0000 (20:06 +0530)]
soc: ti: k3-navss-ringacc: Remove unused ring modes

With AM64x supporting only K3_NAV_RINGACC_RING_MODE_RING or the exposed
ring mode, all other K3 SoCs have also been moved to this common
baseline. Therefore drop other modes such as
K3_NAV_RINGACC_RING_MODE_MESSAGE (and proxy) to save on SPL footprint.

There is a saving of ~800 bytes with this change for am65x_evm_r5_defconfig.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
3 years agosoc: ti: k3-navss-ringacc: Add AM64 ringacc support
Vignesh Raghavendra [Mon, 10 May 2021 14:36:03 +0000 (20:06 +0530)]
soc: ti: k3-navss-ringacc: Add AM64 ringacc support

AM64 dual mode rings are modeled as pair of Rings objects which has common
configuration and memory buffer, but separate real-time control register
sets for each direction mem2dev (forward) and dev2mem (reverse).

AM64 rings must be requested only using k3_ringacc_request_rings_pair(),
and forward ring must always be initialized/configured. After this any
other Ringacc APIs can be used without any callers changes.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agofirmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latest
Vignesh Raghavendra [Mon, 10 May 2021 14:36:02 +0000 (20:06 +0530)]
firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latest

Update struct ti_sci_msg_rm_udmap_tx_ch_cfg_req to latest ABI to support
AM64x BCDMA Block copy channels.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>