Alison Wang [Fri, 17 Oct 2014 07:26:33 +0000 (15:26 +0800)]
arm: ls102xa: Remove bit reversing for SCFG registers
SCFG_SCFGREVCR is SCFG bit reverse register. This register
must be written with 0xFFFFFFFF before writing to any other
SCFG register. Then other SCFG register could be written in
big-endian mode.
Address: 157_0000h base + 200h offset = 157_0200h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W/R SCFGREV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0-31
SCFGREV SCFG Bit Reverse Control Filed
32'h 0000_0000 - No bit reverse is applied
32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as
0:31
This patch removes the bit reversing for SCFG registers in
u-boot. It will be implemented through PBI commands in RCW
.pbi
write 0x570200, 0xffffffff
.end
So other SCFG register could be written in big-endian mode
in u-boot or kernel directly.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Jason Jin [Fri, 17 Oct 2014 07:26:32 +0000 (15:26 +0800)]
arm: ls102xa: Add snoop disable for slave port 0, 1 and 2
Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.
Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Move USB Errata checking code from "arch/powerpc" to architecture independent
file "fsl_usb.h" so that errata(s) become independent of the architecture.
For each erratum checking function for PPC arch, define a nop function for
non PPC arch for successful compilation in either case
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Bo Shen [Mon, 10 Nov 2014 07:46:22 +0000 (15:46 +0800)]
ARM: atmel: add sama5d4 xplained ultra board support
The code for this board supports following features:
- Boot media support: NAND flash/SD card/SPI flash
- Support LCD display (optional, disabled by default)
- Support ethernet
- Support USB mass storage
Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bo Shen [Mon, 10 Nov 2014 07:24:02 +0000 (15:24 +0800)]
ARM: atmel: add sama5d4ek board support
The code for this board supports following features:
- Boot media support: NAND flash/SD card/SPI flash
- Support LCD display
- Support ethernet
- Support USB mass storage
Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bo Shen [Mon, 10 Nov 2014 07:24:01 +0000 (15:24 +0800)]
net: macb: enable GMAC IP without GE feature support
The User Register in GMAC IP is used to select interface type.
When with GE feature, it is used to select interface between
RGMII and GMII. If without GE feature, it is used to select
interface between MII and RMII.
Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Josh Wu [Mon, 10 Nov 2014 07:24:00 +0000 (15:24 +0800)]
mtd: atmel_nand: runtime to build gf table for pmecc
As in SAMA5D4 SoC, the gf table in ROM code can not be seen.
So, when we try to use PMECC, we need to build it when do
initialization.
Add a macro NO_GALOIS_TABLE_IN_ROM in soc header file. If it
is defined we will build gf table runtime.
The PMECC use the BCH algorithm, so based on the build_gf_tables()
function in lib/bch.c, we can build the Galois Field lookup table.
Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
device ready pin is signalling that the device is ready on state 1
not on 0. Simmiliar as it is in drivers/mtd/nand/nand_spl_simple.c
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Heiko Schocher [Fri, 31 Oct 2014 07:31:02 +0000 (08:31 +0100)]
spl, nand, atmel_nand: add erase one block function
erase one nand block in spl code. keep it simple, as size matters
This is used on the upcoming taurus spl support.
Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Heiko Schocher [Fri, 31 Oct 2014 07:31:00 +0000 (08:31 +0100)]
spl, nand: add option to boot raw u-boot.bin image only
enable to boot only a raw u-boot.bin image from nand with the
CONFIG_SPL_NAND_RAW_ONLY define. This option saves space on
boards where spl space is low.
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Heiko Schocher [Fri, 31 Oct 2014 07:30:58 +0000 (08:30 +0100)]
arm, at91: compile mpddrc ram init code also for AT91SAM9M10G45
- compile mpddrc ram init code also for AT91SAM9M10G45
based boards.
- in CONFIG_SAMA5D3 case, look for the ATMEL_MPDDRC_CR_DECOD_INTERLEAVED
in the cr configuration
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Heiko Schocher [Fri, 31 Oct 2014 07:30:57 +0000 (08:30 +0100)]
arm, at91, mpddrc: fix typo in ddr2_init()
use the configure value for computing the ba_off value
not the value from the cr register. This leaded in a
wrong ram configuration on the upcoming corvus spl board
support.
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Heiko Schocher [Fri, 31 Oct 2014 07:30:55 +0000 (08:30 +0100)]
spi, atmel: move CONFIG_SYS_SPI_WRITE_TOUT into common header
move CONFIG_SYS_SPI_WRITE_TOUT into drivers/spi/atmel_spi.h
and define a default value. Delete this define in the board
config files, where it is possible (all boards use currently
the same value).
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bo Shen [Fri, 24 Oct 2014 08:13:26 +0000 (16:13 +0800)]
ARM: atmel: spl: make css field configurable
The clock source for master clock can be slow clock, main clock,
plla clock or upll clock. So, make the clock source selection
field in mckr can be configured.
Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bo Shen [Wed, 22 Oct 2014 10:01:23 +0000 (18:01 +0800)]
ARM: at91 series: convert to generic board
Signed-off-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bo Shen [Wed, 22 Oct 2014 06:45:56 +0000 (14:45 +0800)]
net: macb: write mac address when initialization
When boot up without mac address setting, it will give the warning
message like: "Warning: failed to set MAC address", however when
execute network related command, it still execute them without any
warning information.
With this patch, it will exit directly with following information:
"gmac0: mac address is not valid"
It also solve the problem after bootup then set mac address and the
mac address won't set to net device issue.
Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
arm: rmobile: configs: Collect up common part of config for R-Car SoCs
The lager, koelsch, alt, gose board supported in rmobile is
distinguished as the R-Car Gen2 series and has much common setting.
This collect up the common part of config as rcar-gen2-common.h.
Yangbo Lu [Thu, 16 Oct 2014 02:58:55 +0000 (10:58 +0800)]
powerpc/85xx: enable some P1/P2 boards mtdparts for nor flash
Enable these boards mtdparts for nor flash:
p1020rdb-pd, p1021rdb-pc, p1022ds, p1025twr, and p2020rdb-pc.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Scott Wood <scottwood@freescale.com>
powerpc/mpc83xx: Zero boot_flags arg for calling board_init_f()
The argument boot_flags of board_init_f() is not used at all in the
powerpc specific board.c init sequence. Now with the generic init
sequence, this boot_flags arg is used by board_init_f().
This patch sets the r3 register that is used to pass the boot_flags
argument from the start.S board_init_f() call to 0 prior to the function
call to avoid unknown content to end up in gd->flags.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
Ashish Kumar [Tue, 7 Oct 2014 12:32:23 +0000 (18:02 +0530)]
powerpc/BSC9131RDB: Enable creation of dynamic partitions for NAND
* fdt_fixup_mtdparts is called from ft_board_setup
* Run "mtdparts default" to create NAND partition on uboot
* Use mtdparts to create partitions dynamically rather
than using static partitions in device tree
Signed-off-by: Ashish Kumar <Ashish.Kumar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Ashish Kumar [Mon, 6 Oct 2014 12:54:56 +0000 (18:24 +0530)]
powerpc/BSC9132QDS: Enable creation of dynamic partition for NAND and NOR
* fdt_fixup_mtdparts is called from ft_board_setup
* run "mtdparts default" to create NAND, NOR partition on uboot
* Use mtdparts to create partitions dynamically rather
than using static partitions in device tree
Signed-off-by: Ashish Kumar <Ashish.Kumar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg
-A_007662 states that for x1 link width, PCIe2 controller trains in
Gen1 speed while configured for Gen2 speed.
Workaround:Set the width to x1 and speed to Gen2 by writing to
CCSR registers in PBI phase
-A_008007 states that PVR register may show random value.
Workaround: Reset PVR register using DCSR space in PBI phase
Add PBI based software workaround for A_007662 and A_008007
in t104x_pbi.cfg. This is required for SPL-based bootloaders
like NAND-boot, SD-boot, SPI-boot
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
ramneek mehresh [Thu, 21 Aug 2014 12:22:17 +0000 (17:52 +0530)]
85xx/b4:Correct USB DR controller liodn entry
LIODN entry for B4860/B4420 mentions USB controller as "mph"
insread of "dr". This results in PAMU not permitting bus
transactions for USB DR controller on B4860 resulting in
USB function failure. Replacing "fsl-usb2-mph" with
"fsl-usb2-dr" allows USB DR controller bus transactions
PCIe1: Root Complex, x1 gen1, regs @ 0xe000a000
02:00.0 - 1148:9e00 - Network controller
PCIe1: Bus 01 - 02
In: serial
Out: serial
Err: serial
Net: eTSEC0 [PRIME], eTSEC1
Hit any key to stop autoboot: 0
=> ver
Shaohui Xie [Wed, 13 Aug 2014 10:38:09 +0000 (18:38 +0800)]
driver/net/fm/memac_phy: set NEG bit for external MDIOs
NEG bit default is '1' for external MDIOs as per FMAN-v3 RM, but on some
platforms, e.g. T2080QDS, this bit is '0', which leads to MDIO failure
on XAUI PHY, so set this bit definitely to align with the RM.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Wed, 13 Aug 2014 10:32:19 +0000 (18:32 +0800)]
Fman/mEMAC: mEMAC fix for 10G MAC and PHY
1. use Payload length check disable when enable MAC;
2. add XGMII support for setting MAC interface mode;
3. only enable auto negotiation for Non-XGMII mode;
4. return 0xffff if clause 22 is used to read 10G phy_id;
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-By: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
Until now this defined to be 512KB and the total binary size actually
was on the edge of this limit. Most of the powerpc boards have thus
moved to 768KB.
Since on the current kmp204x boards there is 1MB reserved for u-boot on
the SPI boot flash, there is no problem to set the limit to 768KB as
well to be on line with the other powerpc boards and to eventually
configure in some additional features (and binary size) to u-boot.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
Ye.Li [Wed, 12 Nov 2014 06:02:05 +0000 (14:02 +0800)]
imx: mx6q/dlsabreauto: And NAND flash support
The i.MX6Q/DL sabreauto board has one NAND socket, set the
CONFIG_NAND_MXS and relevant NAND configurations to enable the
MXS NAND flash driver.
Add board level codes to set IOMUX and clock for GPMI-NAND and
BCH module.
Ye.Li [Wed, 12 Nov 2014 06:02:04 +0000 (14:02 +0800)]
imx: mx6q/dl sabre_common: Move MMC ENV offset to 512KB position
Set the CONFIG_ENV_OFFSET from 384KB to 512KB offset, so we will have larger space
for u-boot image.
When enabling NAND flash support feature, the u-boot image size has exceeded the
384KB, which causes overlay to the environment variables storage.
Today I got the final board and found out that a different
connector is used as the one on my development board. The
new connector has swaped pins for cd and wp.
This change is tested on a production ready board.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
CPU: Freescale i.MX6D rev1.2 at 792 MHz
Reset cause: WDOG
Board: ot1200
I2C: ready
DRAM: 1 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB
In: serial
Out: serial
Err: serial
Net: using phy at 0
FEC [PRIME]
Hit any key to stop autoboot: 0
=> usb start
(Re)start USB...
USB0: Port not available.
USB1: USB EHCI 1.00
scanning bus 1 for devices... 4 USB Device(s) found
=> usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
| u-boot EHCI Host Controller
|
+-2 Hub (480 Mb/s, 2mA)
|
+-3 Mass Storage (480 Mb/s, 80mA)
| USBest Technology USB Mass Storage Device 0000000000028B
|
+-4 Vendor specific (480 Mb/s, 2mA)
=>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Hans de Goede [Fri, 7 Nov 2014 15:09:00 +0000 (16:09 +0100)]
sunxi: ehci: Add proper Kconfig options to select the usb Vbus gpio-s
Add proper Kconfig options to select the usb Vbus gpio-s, besides moving to
Kconfig being the right thing to do, an added advantage of this is that it
allows for boards without Vbus gpio-s.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 25 Oct 2014 18:27:23 +0000 (20:27 +0200)]
sun6i: Add dram initialization code
Add full support for dram initialization, using a fixed clock and autodetection
of the memory organization (numbers of channels, bus-width, etc.).
This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK,
extended with extra initialization sequences and the autodetect algorithm
from boot0.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Oliver Schinagl [Fri, 26 Jul 2013 10:56:58 +0000 (12:56 +0200)]
sun6i: Add basic axp221 driver
The A31 uses the AXP221 pmic for various voltages.
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
--
Changes in v2:
-Rebase
Changes in v3:
-Add support for all dldo and aldo-s
-Add Kconfig option to select building AXP221 and to select voltage of
dldo and aldo-s
Changes in v4:
-Add axp221_setbits helper function
-Use symbolic names for enabled bits in CTRL1 - CTRL3 registers
Oliver Schinagl [Thu, 25 Jul 2013 12:07:42 +0000 (14:07 +0200)]
sun6i: Add new p2wi controller driver
The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very little use and thus is
limited to single byte transmission only.
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Michal Simek [Thu, 13 Nov 2014 12:22:40 +0000 (13:22 +0100)]
zynq: zybo: Move CONFIG_DEFAULT_DEVICE_TREE to defconfig
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Move CONFIG_DEFAULT_DEVICE_TREE from board config
directly to defconfig.
This patch removes compilation warning:
include/configs/zynq_zybo.h:24:0: warning: "CONFIG_DEFAULT_DEVICE_TREE"
redefined [enabled by default]
#define CONFIG_DEFAULT_DEVICE_TREE zynq-zybo
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Thu, 6 Nov 2014 06:55:21 +0000 (15:55 +0900)]
sh: move CONFIG_{SH2, SH2A, SH3, SH4} to Kconfig
This commit moves CONFIG_SH2, CONFIG_SH2A, CONFIG_SH3, CONFIG_SH4
to Kconfig renaming into CONFIG_CPU_SH2, CONFIG_CPU_SH2A,
CONFIG_CPU_SH3, CONFIG_CPU_SH4, respectively because
arch/sh/Kconfig of Linux uses CONFIG_CPU_SH* convention.
Nikita Kiryanov [Tue, 11 Nov 2014 13:46:05 +0000 (15:46 +0200)]
powerpc: remove orphaned boards mcc200 and prs200
mcc200 and prs200 are old and have no maintainer. Remove the boards.
This also removes the mcc200 specific 1bpp BMP support from
common/lcd.c
Cc: Wolfgang Denk <wd@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Nikita Kiryanov [Wed, 29 Oct 2014 17:28:33 +0000 (19:28 +0200)]
arm: imx: make bmode command work with SPL/U-Boot combo
The bmode command forces the SoC to use a specific boot device
by writing its boot mode into SRC_GPR9, and notifying the SoC of
the change using SRC_GPR10[28] bit: if the bit is on, bootROM
uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine
the boot device.
SPL on the other hand is oblivious to this distinction, so once
the bootROM loads SPL from the device configured in SRC_GPR10,
SPL will attempt to load U-Boot from the device configured in
SRC_SMBR1, which is not updated by the bootROM to the value in
SRC_GPR9.
The result is that the selected boot device is not used across all
the boot stages.
Update spl_boot_device() to look at gpr9 when necessary.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Heiko Schocher <hs@denx.de>
projects / u-boot.git / log