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3 years agoefi_loader: loosen buffer parameter check in efi_file_read_int
Peng Fan [Wed, 28 Apr 2021 13:54:01 +0000 (21:54 +0800)]
efi_loader: loosen buffer parameter check in efi_file_read_int

This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
but that fix was wrongly partial reverted.

When reading a directory, EFI_BUFFER_TOO_SMALL should be returned when
the supplied buffer is too small, so a use-case is to call
EFI_FILE_PROTOCOL.Read() with *buffer_size=0 and buffer=NULL to
obtain the needed size before doing the actual read.

So remove the check only for directory reading, file reading already
do the check by itself.

Fixes: db12f518edb0("efi_loader: implement non-blocking file services")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefan Sørensen <stefan.sorensen@spectralink.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: capsule: Remove the check for capsule_authentication_enabled environment...
Sughosh Ganu [Mon, 12 Apr 2021 15:05:23 +0000 (20:35 +0530)]
efi_loader: capsule: Remove the check for capsule_authentication_enabled environment variable

The current capsule authentication code checks if the environment
variable capsule_authentication_enabled is set, for authenticating the
capsule. This is in addition to the check for the config symbol
CONFIG_EFI_CAPSULE_AUTHENTICATE. Remove the check for the environment
variable. The capsule will now be authenticated if the config symbol
is set.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviwed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agohash: Kconfig option for SHA512 hardware acceleration
Heinrich Schuchardt [Fri, 14 May 2021 05:08:27 +0000 (07:08 +0200)]
hash: Kconfig option for SHA512 hardware acceleration

Commit a479f103dc1c ("hash: Allow for SHA512 hardware implementations")
defined function definitions for hardware accelerated SHA384 and SHA512.
If CONFIG_SHA_HW_ACCEL=y, these functions are used.

We already have boards using CONFIG_SHA_HW_ACCEL=y but none implements the
new functions hw_sha384() and hw_sha512().

For implementing the EFI TCG2 protocol we need SHA384 and SHA512. The
missing hardware acceleration functions lead to build errors on boards like
peach-pi_defconfig.

Introduce a new Kconfig symbol CONFIG_SHA512_HW_ACCEL to control if the
functions hw_sha384() and hw_sha512() shall be used to implement the SHA384
and SHA512 algorithms.

Fixes: a479f103dc1c ("hash: Allow for SHA512 hardware implementations")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoefi_loader: build warning in efi_tcg2_hash_log_extend_event
Heinrich Schuchardt [Wed, 12 May 2021 15:37:20 +0000 (17:37 +0200)]
efi_loader: build warning in efi_tcg2_hash_log_extend_event

Building 32bit boards with the TCG2 protocol enabled leads to a build
warning due to a missing conversion.

    lib/efi_loader/efi_tcg2.c:774:27:
    error: cast to pointer from integer of different size
    [-Werror=int-to-pointer-cast]
    774 |  ret = tcg2_create_digest((u8 *)data_to_hash, data_to_hash_len,
        |                           ^

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
3 years agodoc: extension.rst missing in doc/usage/index.rst
Heinrich Schuchardt [Sat, 15 May 2021 22:34:28 +0000 (00:34 +0200)]
doc: extension.rst missing in doc/usage/index.rst

'make htmldocs' results in a build warning

    checking consistency... doc/usage/extension.rst:
    WARNING: document isn't included in any toctree

Add the document to the index.

Fixes: 2f84e9cf06d3 ("cmd: add support for a new "extension" command")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agodoc: man-page for size command
Heinrich Schuchardt [Sat, 15 May 2021 11:08:57 +0000 (13:08 +0200)]
doc: man-page for size command

Provide a man-page for the size command.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-marvell
Tom Rini [Mon, 17 May 2021 14:01:56 +0000 (10:01 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- Add base support for Marvell OcteonTX2 CN9130 DB (mostly done
  by Kostya)
- Sync Armada 8k MMU setup with Marvell version (misc Marvell
  authors)
- spi: kirkwood: Some fixes especially for baudrate generation
  (misc Marvell authors)
- mvebu: x530: Reduce SPL image size (Stefan)
- Rename "rx_training" to "mvebu_comphy_rx_training" (Stefan)

3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-usb
Tom Rini [Sun, 16 May 2021 22:06:26 +0000 (18:06 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-usb

3 years agousb: dwc3-generic: Disable host driver definition if gadget only
Kunihiko Hayashi [Wed, 12 May 2021 14:11:14 +0000 (23:11 +0900)]
usb: dwc3-generic: Disable host driver definition if gadget only

Even if only USB gadget is defined, dwc3 generic driver enables
a definition and probe/remove functions for host driver.

This enables the definition if USB_HOST is enabled only.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
3 years agousb: musb-new: Extend and move Allwinner quirk into Kconfig
Andre Przywara [Wed, 5 May 2021 12:51:03 +0000 (13:51 +0100)]
usb: musb-new: Extend and move Allwinner quirk into Kconfig

All newer Allwinner SoCs (since about 2013) miss the CONFIGDATA register
in their MUSB implementation, so they need a quirk to hardcode this.

Currently this quirk depends on listing the SoCs affected in musb_reg.h,
which means that this list needs to grow with every new chip.

Move the quirk feature into Kconfig, next to PIO_ONLY, and change the
default to y (for Allwinner builds), while listing the early
implementations as exceptions.

This fixes USB peripheral operation on some newer SoCs, which were not
explicitly listed before.

Tested on H6, H616, R40 (which were broken before), and also on the H5
and A20, for regressions.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
3 years agoarm: octeontx2: Add Octeon TX2 CN913x DB support
Konstantin Porotchkin [Tue, 11 May 2021 06:11:25 +0000 (08:11 +0200)]
arm: octeontx2: Add Octeon TX2 CN913x DB support

This patch adds the base support for the Marvell Octeon TX2 CN913x DB.
Only one defconfig is added with this patch. Other board variants are
available (NAND, MMC booting) and images for these boards can be
generated by following the documentation added in the included README.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agoarm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DB
Konstantin Porotchkin [Tue, 11 May 2021 06:11:24 +0000 (08:11 +0200)]
arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DB

This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN913x DB. This is only the base port with not all
interfaces supported fully.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agocmd: mvebu: Rename rx_training to mvebu_comphy_rx_training
Stefan Roese [Wed, 5 May 2021 07:15:10 +0000 (09:15 +0200)]
cmd: mvebu: Rename rx_training to mvebu_comphy_rx_training

Rename the misleading cmd "rx_training" to "mvebu_comphy_rx_training" to
avoid confusion and mixup with DDR3/4 training. This makes it clear,
that this command is platform specific and handles the COMPHY RX
training.

Also depend this cmd on ARMADA_8K and not TARGET_MVEBU_ARMADA_8K to make
is available for OcteonTX2 CN913x.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pali Rohár <pali@kernel.org>
Cc: Marek Behun <marek.behun@nic.cz>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Marek Behún <marek.behun@nic.cz>
Acked-by: Pali Rohár <pali@kernel.org>
3 years agopcie: designware: mvebu: do not configure ATU for IO when not used
Marcin Wojtas [Fri, 30 Apr 2021 13:33:15 +0000 (15:33 +0200)]
pcie: designware: mvebu: do not configure ATU for IO when not used

The pcie_dw_mvebu configure ATU regions for memory, configuration
and IO space types. However the latter is not obligatory
and when not specified in the device tree, causes wrong
ATU configuration. Fix that by adding a dependency on the
detected PCIE regions count.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/18136
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
3 years agoarm64: mvebu: extend the mmio region
Grzegorz Jaszczyk [Fri, 30 Apr 2021 13:29:50 +0000 (15:29 +0200)]
arm64: mvebu: extend the mmio region

Some of the setups including cn9130 opens mmio window starting from
0xc0000000, reflect it in the u-boot code.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agoarm64: mvebu: a8k: move firmware related definitions to fw info
Grzegorz Jaszczyk [Fri, 30 Apr 2021 13:29:49 +0000 (15:29 +0200)]
arm64: mvebu: a8k: move firmware related definitions to fw info

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agoarm64: mvebu: do not map firmware RT service region
Grzegorz Jaszczyk [Fri, 30 Apr 2021 13:29:48 +0000 (15:29 +0200)]
arm64: mvebu: do not map firmware RT service region

There is region left by ATF, which needs to remain in memory to provide RT
services. To prevent overwriting it by u-boot, do not provide any mapping
for this memory region, so any attempt to access it will trigger
synchronous exception.

Update sr 2021-04-12:
Don't update armada3700/cpu.c mmu table, as this has specific changes
included in mainline.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agoarm64: mvebu: a8k: align memory regions
jinghua [Fri, 30 Apr 2021 13:29:47 +0000 (15:29 +0200)]
arm64: mvebu: a8k: align memory regions

1. RAM: base address 0x0 size 2Gbytes
2. MMIO: base address 0xf0000000 size 1Gbytes

Signed-off-by: Ofir Fedida <ofedida@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agospi: kirkwood: prevent limiting speed to 0
Grzegorz Jaszczyk [Fri, 30 Apr 2021 13:26:31 +0000 (15:26 +0200)]
spi: kirkwood: prevent limiting speed to 0

After commit 1fe929ed497bcc8975be8d37383ebafd22b99dd2
("spi: kirkwood: prevent configuring speed exceeding max controller freq")
the spi frequency could be set to 0 on platform where spi-max-frequency
is not defined (e.g. on armada-388-gp). Prevent limiting speed in
mentioned cases.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Marcin Wojtas <marcin@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agospi: kirkwood: prevent configuring speed exceeding max controller freq
Marcin Wojtas [Fri, 30 Apr 2021 13:26:30 +0000 (15:26 +0200)]
spi: kirkwood: prevent configuring speed exceeding max controller freq

This patch adds a limitation in the kirkwood_spi driver
set_speed hook, which prevents setting too high transfer
speed.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agospi: kirkwood: support extended baud rates
Ken Ma [Fri, 30 Apr 2021 13:26:29 +0000 (15:26 +0200)]
spi: kirkwood: support extended baud rates

The Armada SoC family implementation of this SPI hardware module has
extended the configuration register to allow for a wider range of SPI
clock rates. Specifically the Serial Baud Rate Pre-selection bits in the
SPI Interface Configuration Register now also use bits 6 and 7 as well.

Modify the baud rate calculation to handle these differences for the
Armada case. Potentially a baud rate can be setup using a number of
different pre-scalar and scalar combinations. This code tries all
possible pre-scalar divisors (8 in total) to try and find the most
accurate set.

Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
3 years agomvebu: x530: Reduce SPL image size
Stefan Roese [Wed, 12 May 2021 07:18:37 +0000 (09:18 +0200)]
mvebu: x530: Reduce SPL image size

Currently, building U-Boot for x530 fails since the SPL image is too
big. This patch reduces the SPL size by changing the following Kconfig
options:

Enable CONFIG_SPL_TINY_MEMSET
Disable CONFIG_SPI_FLASH_BAR

By disabling CONFIG_SPI_FLASH_BAR, the tiny SPI NOR framework can be
used.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Pratyush Yadav <p.yadav@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
3 years agoconfigs: Resync with savedefconfig
Tom Rini [Sat, 15 May 2021 12:10:13 +0000 (08:10 -0400)]
configs: Resync with savedefconfig

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-sh
Tom Rini [Sat, 15 May 2021 03:00:24 +0000 (23:00 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-sh

3 years agoMerge tag 'u-boot-amlogic-20210514' of https://source.denx.de/u-boot/custodians/u...
Tom Rini [Sat, 15 May 2021 02:59:59 +0000 (22:59 -0400)]
Merge tag 'u-boot-amlogic-20210514' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro
- usb: dwc3-meson-g12a: skip phy on -ENODATA aswell
- net: dwmac_meson8b: do not set TX delay in TXID & RXID
- net: designware: meson8b: add g12a compatible

3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-riscv
Tom Rini [Sat, 15 May 2021 02:59:48 +0000 (22:59 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

3 years agonet: designware: meson8b: add g12a compatible
Neil Armstrong [Fri, 16 Apr 2021 12:52:06 +0000 (14:52 +0200)]
net: designware: meson8b: add g12a compatible

Add support for the Meson G12A dwmac glue compatible needed after Linux 5.12 sync.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agonet: dwmac_meson8b: do not set TX delay in TXID & RXID
Neil Armstrong [Wed, 5 May 2021 07:52:08 +0000 (09:52 +0200)]
net: dwmac_meson8b: do not set TX delay in TXID & RXID

When the PHY interface is set as TXID & RXID, the delays should be taken from DT,
but first they should not be hardcoded since the PHY driver will set them.

Fixes: 798424e857 ("net: designware: add Amlogic Meson8b & later glue driver")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
3 years agousb: dwc3-meson-g12a: skip phy on -ENODATA aswell
Neil Armstrong [Wed, 5 May 2021 08:38:57 +0000 (10:38 +0200)]
usb: dwc3-meson-g12a: skip phy on -ENODATA aswell

If the PHY isn't specified in the DT, -ENODATA means it should be skipped,
handle it like -ENOENT.

With that, devices without USB3 supported can have USB working (Odroid-HC4).

Fixes: adb049abf7 ("usb: dwc3: Add Meson G12A USB Glue")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoARM: dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro
Neil Armstrong [Tue, 20 Apr 2021 08:45:56 +0000 (10:45 +0200)]
ARM: dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro

This lacks the right u-boot specific DT include to make HDMI work.

Reported-by: B1oHazard <ty3uk@mail.ua>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agoRevert "riscv: cpu: fu740: clear feature disable CSR"
Bin Meng [Mon, 10 May 2021 09:08:16 +0000 (17:08 +0800)]
Revert "riscv: cpu: fu740: clear feature disable CSR"

This reverts commit bc8bbb77f74f21582b3bfd790334397757f88575.

This commit breaks U-Boot booting on SiFive Unleashed board, as
there is no such CSR on U54 core.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
3 years agopwm: sifive: make set_config() and set_enable() work properly
Vincent Chen [Mon, 3 May 2021 07:26:49 +0000 (15:26 +0800)]
pwm: sifive: make set_config() and set_enable() work properly

The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work
properly due to the wrong implementations. It will cause the u-boot
PWM command to not work as expected. The bugs will be resolved in this
patch.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
3 years agoriscv: Don't reserve AI ram in k210 dts
Sean Anderson [Fri, 9 Apr 2021 02:13:13 +0000 (22:13 -0400)]
riscv: Don't reserve AI ram in k210 dts

It is no longer necessary to disallow ai ram, since it is enabled by the
sram driver.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoriscv: k210: Use AI as the parent clock of aisram, not PLL1
Sean Anderson [Fri, 9 Apr 2021 02:13:12 +0000 (22:13 -0400)]
riscv: k210: Use AI as the parent clock of aisram, not PLL1

Testing showed that disabling AI while leaving PLL1 enabled disabled the
aisram. This suggests that AI is a more appropriate clock for that ram
bank.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoriscv: k210: Rename airam to aisram
Sean Anderson [Fri, 9 Apr 2021 02:13:11 +0000 (22:13 -0400)]
riscv: k210: Rename airam to aisram

This is more consistent with the naming of other ram banks, and matches
what Linux is doing.

Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoriscv: Enable AI ram on K210
Sean Anderson [Fri, 9 Apr 2021 02:13:10 +0000 (22:13 -0400)]
riscv: Enable AI ram on K210

We just need to initialize all the clocks pre-reloc. The clock driver
creates a bunch of devices, so we need to increase the pre-reloc malloc
arena.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoriscv: Enable some devices pre-relocation
Sean Anderson [Fri, 9 Apr 2021 02:13:09 +0000 (22:13 -0400)]
riscv: Enable some devices pre-relocation

These devices are necessary for the clock driver, which is required by the
sram driver, to run pre-relocation.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoclk: Add support for the k210 clock driver pre-relocation
Sean Anderson [Fri, 9 Apr 2021 02:13:08 +0000 (22:13 -0400)]
clk: Add support for the k210 clock driver pre-relocation

Variables which had previously been stored in .bss are moved to .data. In
addition, probed needs to be reset when the clock driver is re-bound
post-relocation.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoclk: k210: Move the clint clock to under aclk
Sean Anderson [Fri, 9 Apr 2021 02:13:07 +0000 (22:13 -0400)]
clk: k210: Move the clint clock to under aclk

No other (real) clocks have the cpu clock as their parent; instead they are
children of aclk. Move the clint clock under aclk to match them.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoclk: k210: Remove k210_register_pll
Sean Anderson [Fri, 9 Apr 2021 02:13:06 +0000 (22:13 -0400)]
clk: k210: Remove k210_register_pll

This simplifies the PLL creation process, since we don't have to pass all
the parameters individually.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoclk: k210: Fix PLL enable always getting taken
Sean Anderson [Fri, 9 Apr 2021 02:13:05 +0000 (22:13 -0400)]
clk: k210: Fix PLL enable always getting taken

This conditional always evaluated as false, regardless of the value of reg.
Fix it so that it properly tests the bits in the PLL register. Also test
PLL_EN, now that we set it.

Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoclk: k210: Fix PLLs not being enabled
Sean Anderson [Fri, 9 Apr 2021 02:13:04 +0000 (22:13 -0400)]
clk: k210: Fix PLLs not being enabled

After starting or setting the rate of a PLL, the enable bit must be set.

This fixes a bug where the AI ram would not be accessible, because it
requires PLL1 to be running.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Damien Le Moal <damien.lemoal@wdc.com>
3 years agoclk: Warn on failure to assign rate
Sean Anderson [Fri, 9 Apr 2021 02:13:03 +0000 (22:13 -0400)]
clk: Warn on failure to assign rate

If the user/dev explicitly requests a clock be assigned a certain rate,
then we should warn them if we can't do it. This makes it clear if the
clock is running at the default rate.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
3 years agoMAINTAINERS: Add a co-maintainer for RISC-V
Rick Chen [Mon, 25 Jan 2021 06:08:31 +0000 (14:08 +0800)]
MAINTAINERS: Add a co-maintainer for RISC-V

Add Leo as co-maintainer for RISC-V.

Signed-off-by: Rick Chen <rick@andestech.com>
3 years agoMerge branch '2021-05-13-extension-board-detection-and-DT-overlay-application'
Tom Rini [Thu, 13 May 2021 17:09:14 +0000 (13:09 -0400)]
Merge branch '2021-05-13-extension-board-detection-and-DT-overlay-application'

- Improve support for various forms of extension boards and add DT
  overlay application support.

3 years agoam335x: add support for cape detect functionality
Kory Maincent [Tue, 4 May 2021 17:31:30 +0000 (19:31 +0200)]
am335x: add support for cape detect functionality

Update the Kconfig and the board file to make the am335x board compatible
with cape detection.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
3 years agoarm: am335x: add support for i2c2 bus
Kory Maincent [Tue, 4 May 2021 17:31:29 +0000 (19:31 +0200)]
arm: am335x: add support for i2c2 bus

The am335x from BeagleBone use i2c EEPROM to detect capes.
The memory is wired to i2c bus 2 therefore it need to be enabled.

Add i2c2 clock, pinmux description and pinmux enable function.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
3 years agoconfigs: CHIP: add support for DIP detect functionality
Kory Maincent [Tue, 4 May 2021 17:31:28 +0000 (19:31 +0200)]
configs: CHIP: add support for DIP detect functionality

This commit enables using the extension board detection mechanism on
CHIP boards

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Acked-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Andre Przywara <andre.przywara@arm.com>
3 years agoarm: sunxi: add support for DIP detection to CHIP board
Kory Maincent [Tue, 4 May 2021 17:31:27 +0000 (19:31 +0200)]
arm: sunxi: add support for DIP detection to CHIP board

Add the extension_board_scan specific function to scan the information
of the EEPROM on one-wire and fill the extension struct.
Add the Kconfig symbol to enable the needs to detect DIPs.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Andre Przywara <andre.przywara@arm.com>
3 years agow1: replace dt detection by automatic detection
Kory Maincent [Tue, 4 May 2021 17:31:26 +0000 (19:31 +0200)]
w1: replace dt detection by automatic detection

This patch changes the functioning of the detection of w1 devices.
The old way was a comparison between detected w1 and the ones described in
the device tree. Now it will just look for the driver matching the family
id of the w1 detected.

The patch is inspired from Maxime Ripard code.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Maxime Ripard <maxime@cerno.tech>
3 years agoam57xx: add support for cape detect functionality
Kory Maincent [Tue, 4 May 2021 17:31:25 +0000 (19:31 +0200)]
am57xx: add support for cape detect functionality

This commit enables using the extension board detection mechanism on
AM57xx based platforms.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
3 years agoti/common: add support for extension_scan_board function
Kory Maincent [Tue, 4 May 2021 17:31:24 +0000 (19:31 +0200)]
ti/common: add support for extension_scan_board function

The BeagleBone platforms all use a common mechanism to discover and
identify extension boards (called "capes"): each extension board has an
I2C-connected EEPROM describing itself.

This patch implements a generic extension_scan_board() feature that can
be used by all BeagleBone platforms to read those I2C EEPROMs and fill
in the list of "extension" structures.

Following commits will enable this common logic on two BeagleBone
platforms.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
3 years agopytest: add sandbox test for "extension" command
Kory Maincent [Tue, 4 May 2021 17:31:23 +0000 (19:31 +0200)]
pytest: add sandbox test for "extension" command

This commit extends the sandbox to implement a dummy
extension_board_scan() function and enables the extension command in
the sandbox configuration. It then adds a test that checks the proper
functionality of the extension command by applying two Device Tree
overlays to the sandbox Device Tree.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
[trini: Limit to running on sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agocmd: add support for a new "extension" command
Kory Maincent [Tue, 4 May 2021 17:31:22 +0000 (19:31 +0200)]
cmd: add support for a new "extension" command

This patch adds a new "extension" command, which aims at detecting
extension boards connected to the hardware platform, and apply the
Device Tree overlays that describe the hardware present on those
extension boards.

In order to enable this mechanism, board-specific code must implement
the extension_board_scan() function that fills in a linked list of
"struct extension", each describing one extension board. In addition,
the board-specific code must select the SUPPORT_EXTENSION_SCAN Kconfig
boolean.

Based on this:

 - "extension scan" makes the generic code call the board-specific
   extension_board_scan() function to retrieve the list of detected
   extension boards.

 - "extension list" allows to list the detected extension boards.

 - "extension apply <number>|all" allows to apply the Device Tree
   overlay(s) corresponding to one, or all, extension boards

The latter requires two environment variables to exist and set one variable
to run:

 - extension_overlay_addr: the RAM address where to load the Device
   Tree overlays

 - extension_overlay_cmd: the U-Boot command to load one overlay.
   Indeed, the location and mechanism to load DT overlays is very setup
   specific.

 - extension_overlay_name: set by the command: the name of the DT which
   will be load during the execution.

When calling the command described in the extension_overlay_cmd
variable, the variable extension_overlay_name will be defined. So a
typical extension_overlay_cmd will look like this:

  extension_overlay_cmd=load mmc 0:1 $extension_overlay_addr /boot/$extension_overlay_name

Here is an example on how to use it:
=> run loadfdt
=> fdt addr $fdtaddr
=> setenv extension_overlay_addr 0x1000
=> setenv extension_overlay_cmd 'load mmc 0:1 ${extension_overlay_addr} /boot/${extension_overlay_name}'
=> extension scan
Found 1 extension board(s).
=> extension apply 0
519 bytes read in 3 ms (168.9 KiB/s)

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Maxime Ripard <maxime@cerno.tech>
3 years agofdt_support: move fdt_valid from cmd_fdt.c to fdt_support.c
Kory Maincent [Tue, 4 May 2021 17:31:21 +0000 (19:31 +0200)]
fdt_support: move fdt_valid from cmd_fdt.c to fdt_support.c

Move the fdt_valid function to fdt_support.
This changes allow to be able to test the validity of a devicetree in
other c files.

Update code syntax.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Maxime Ripard <maxime@cerno.tech>
3 years agoARM: renesas: Scrub duplicate memory nodes from DT on Gen3
Marek Vasut [Sat, 3 Apr 2021 14:58:49 +0000 (16:58 +0200)]
ARM: renesas: Scrub duplicate memory nodes from DT on Gen3

Scrub duplicate /memory@* node entries here. Some R-Car DTs might
contain multiple /memory@* nodes, however fdt_fixup_memory_banks()
either generates single /memory node or updates the first /memory
node. Any remaining memory nodes are thus potential duplicates.

However, it is not possible to delete all the memory nodes right
away, since some of those might not be DRAM memory nodes, but some
sort of other memory. Thus, delete only the memory nodes which are
in the R-Car3 DBSC ranges.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
3 years agoARM: rmobile: Add missing rcar-common/common.c to Beacon RZG2M kit
Marek Vasut [Wed, 12 May 2021 19:34:11 +0000 (21:34 +0200)]
ARM: rmobile: Add missing rcar-common/common.c to Beacon RZG2M kit

The rcar-common/common.c contains various common board functions shared
by all R-Car and RZG boards. This board is not compiling the file in, so
add it. This way, part of the board code can be de-duplicated too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
3 years agoMerge tag 'ti-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ti
Tom Rini [Wed, 12 May 2021 14:07:21 +0000 (10:07 -0400)]
Merge tag 'ti-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ti

- Initial support for AM64 EVM and SK
- K3 DDR driver unification for J7 and AM64 platforms.
- Minor fixes for TI clock driver

3 years agoARM: dts: k3-am642-sk: Add ethernet related DT nodes
Vignesh Raghavendra [Mon, 10 May 2021 14:36:13 +0000 (20:06 +0530)]
ARM: dts: k3-am642-sk: Add ethernet related DT nodes

Add CPSW related nodes for AM642 SK. There are two CPSW ports on the
board but U-Boot supports only the first port.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agoARM: dts: k3-am64-main: Add CPSW DT nodes
Vignesh Raghavendra [Mon, 10 May 2021 14:36:12 +0000 (20:06 +0530)]
ARM: dts: k3-am64-main: Add CPSW DT nodes

AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same
(based on kernel DT).

Disable second port as its by default set to ICSS usage on EVM.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agonet: ti: am65-cpsw-nuss: Add a new compatible for AM64
Vignesh Raghavendra [Mon, 10 May 2021 14:36:11 +0000 (20:06 +0530)]
net: ti: am65-cpsw-nuss: Add a new compatible for AM64

Add a new compatible to support AM64 SoC

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agonet: ti: am65-cpsw-nuss: Don't cache disabled port ID
Vignesh Raghavendra [Mon, 10 May 2021 14:36:10 +0000 (20:06 +0530)]
net: ti: am65-cpsw-nuss: Don't cache disabled port ID

Currently driver may end up caching disabled port ID as active
interface. Fix this by bailing out earlier in case port is marked
disabled in the DT.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agonet: ti: am65-cpsw-nuss: Prepare to support non primary ext port
Vignesh Raghavendra [Mon, 10 May 2021 14:36:09 +0000 (20:06 +0530)]
net: ti: am65-cpsw-nuss: Prepare to support non primary ext port

CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8)
Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port)
as preparation to allow any one of the 8 ports to be used as ethernet
interface in U-Boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agodma: ti: k3-udma: Add BCDMA and PKTDMA support
Vignesh Raghavendra [Mon, 10 May 2021 14:36:08 +0000 (20:06 +0530)]
dma: ti: k3-udma: Add BCDMA and PKTDMA support

Sync BCDMA and PKTDMA support from Kernel for AM64 SoC

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agodma: ti: k3-psil-am64: Add AM64 PSIL endpoint data
Vignesh Raghavendra [Mon, 10 May 2021 14:36:07 +0000 (20:06 +0530)]
dma: ti: k3-psil-am64: Add AM64 PSIL endpoint data

Add AM64 SoC specific channel mapping and endpoint data.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agodma: ti: k3-psil: Extend PSIL EP data extension for AM64
Vignesh Raghavendra [Mon, 10 May 2021 14:36:06 +0000 (20:06 +0530)]
dma: ti: k3-psil: Extend PSIL EP data extension for AM64

Extend PSIL EP data to include AM64 DMA specific information

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agodma: ti: k3-psil-am654: Drop unused PSIL EP static data
Vignesh Raghavendra [Mon, 10 May 2021 14:36:05 +0000 (20:06 +0530)]
dma: ti: k3-psil-am654: Drop unused PSIL EP static data

ICSSG Ethernet driver uses two src threads per port (one per slice).
Similarly CPSW uses one src thread.

Drop PSIL EP static data for other src threads in order to reduce
R5 SPL footprint. This makes AM65x board bootable again.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agosoc: ti: k3-navss-ringacc: Remove unused ring modes
Vignesh Raghavendra [Mon, 10 May 2021 14:36:04 +0000 (20:06 +0530)]
soc: ti: k3-navss-ringacc: Remove unused ring modes

With AM64x supporting only K3_NAV_RINGACC_RING_MODE_RING or the exposed
ring mode, all other K3 SoCs have also been moved to this common
baseline. Therefore drop other modes such as
K3_NAV_RINGACC_RING_MODE_MESSAGE (and proxy) to save on SPL footprint.

There is a saving of ~800 bytes with this change for am65x_evm_r5_defconfig.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
3 years agosoc: ti: k3-navss-ringacc: Add AM64 ringacc support
Vignesh Raghavendra [Mon, 10 May 2021 14:36:03 +0000 (20:06 +0530)]
soc: ti: k3-navss-ringacc: Add AM64 ringacc support

AM64 dual mode rings are modeled as pair of Rings objects which has common
configuration and memory buffer, but separate real-time control register
sets for each direction mem2dev (forward) and dev2mem (reverse).

AM64 rings must be requested only using k3_ringacc_request_rings_pair(),
and forward ring must always be initialized/configured. After this any
other Ringacc APIs can be used without any callers changes.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agofirmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latest
Vignesh Raghavendra [Mon, 10 May 2021 14:36:02 +0000 (20:06 +0530)]
firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latest

Update struct ti_sci_msg_rm_udmap_tx_ch_cfg_req to latest ABI to support
AM64x BCDMA Block copy channels.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agoboard: ti: am64x: Parse MAC address from board EEPROM
Vignesh Raghavendra [Mon, 10 May 2021 18:14:22 +0000 (23:44 +0530)]
board: ti: am64x: Parse MAC address from board EEPROM

Parse MAC addresses from EEPROM and set them in the env. This is needed
to get MAC address for additional ethernet ports on the EVM.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
3 years agoconfigs: am64x_evm_a53: Enable support for building multiple dtbs
Lokesh Vutla [Thu, 6 May 2021 11:15:05 +0000 (16:45 +0530)]
configs: am64x_evm_a53: Enable support for building multiple dtbs

Enable all relevant configs for building multiple dtbs into a single fit
image and load the right dtb for next stage.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoconfigs: am64x_evm_a53: Enable support for reading eeprom
Lokesh Vutla [Thu, 6 May 2021 11:15:04 +0000 (16:45 +0530)]
configs: am64x_evm_a53: Enable support for reading eeprom

Enable relevant configs for reading eeprom data and updating env
variables.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoconfigs: am64x_evm_a53: Enable configs for printing cpuinfo
Lokesh Vutla [Thu, 6 May 2021 11:15:03 +0000 (16:45 +0530)]
configs: am64x_evm_a53: Enable configs for printing cpuinfo

Enable all relevant configs for printing CPU info.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoconfigs: am64x_evm_r5: Enable support for building multiple device trees
Lokesh Vutla [Thu, 6 May 2021 11:15:02 +0000 (16:45 +0530)]
configs: am64x_evm_r5: Enable support for building multiple device trees

Enable defconfigs for building multiple device trees into a single FIT
image.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoconfigs: am64x_evm_r5: Enable checks for spl and stack sizes
Lokesh Vutla [Thu, 6 May 2021 11:15:01 +0000 (16:45 +0530)]
configs: am64x_evm_r5: Enable checks for spl and stack sizes

Enable relevant configs that checks for the size of image and stack:
BSS: 4KB
Initial MALLOC: 512KB
Initial Stack: 8K
SPL Image size can be: ~960KB

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoarm: dts: am642-r5-sk: Add r5 specific dts
Lokesh Vutla [Thu, 6 May 2021 11:15:00 +0000 (16:45 +0530)]
arm: dts: am642-r5-sk: Add r5 specific dts

Add R5 specific dts for AM64 SK

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
3 years agoarm: dts: am642-sk: Add initial sk dts
Lokesh Vutla [Thu, 6 May 2021 11:14:59 +0000 (16:44 +0530)]
arm: dts: am642-sk: Add initial sk dts

AM642 StarterKit (SK) board is a low cost, small form factor board
designed for TI’s AM642 SoC. It supports the following interfaces:
* 2 GB LPDDR4 RAM
* x2 Gigabit Ethernet interfaces capable of working in switch and MAC mode
* x1 USB 3.0 Type-A port
* x1 UHS-1 capable µSD card slot
* 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837
* 512 Mbit OSPI flash
* x2 UART through UART-USB bridge
* XDS110 for onboard JTAG debug using USB
* Temperature sensors, user push buttons and LEDs
* 40-pin Raspberry Pi compatible GPIO header
* 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO)
* 54-pin header for Programmable Realtime Unit (PRU) IO pins
* Interface for remote automation. Includes:
* power measurement and reset control
* boot mode change

Add basic support for AM642 SK.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoarm: dts: am642-evm: Add I2C nodes
Lokesh Vutla [Thu, 6 May 2021 11:14:58 +0000 (16:44 +0530)]
arm: dts: am642-evm: Add I2C nodes

Add I2C nodes for AM64 and enable pinmux for i2c0 for reading eeprom data.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoarm: dts: k3-am642-r5-evm: Do not use power-domains for I2C
Lokesh Vutla [Thu, 6 May 2021 11:14:57 +0000 (16:44 +0530)]
arm: dts: k3-am642-r5-evm: Do not use power-domains for I2C

I2C EEPROM will be probed before SYSFW is available.
So drop the power-domains property for I2C.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoarm: dts: k3-am64-evm: Make chip id available before pre-reloc
Lokesh Vutla [Thu, 6 May 2021 11:14:56 +0000 (16:44 +0530)]
arm: dts: k3-am64-evm: Make chip id available before pre-reloc

Chipid will be needed for SoC detection for all stages of U-Boot.
So make it u-boot,dm-spl

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoinclude: configs: Update env for selecting right dtb
Lokesh Vutla [Thu, 6 May 2021 11:14:55 +0000 (16:44 +0530)]
include: configs: Update env for selecting right dtb

Now that single defconfig can be used for booting AM64 EVM and SK,
default device tree will not work for selecting dtb for kernel.
Update the env to select right dtb based on eeprom.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoinclude: configs: am64x_evm: Optimize size of SPL BSS
Lokesh Vutla [Thu, 6 May 2021 11:14:54 +0000 (16:44 +0530)]
include: configs: am64x_evm: Optimize size of SPL BSS

Current BSS allocation of SPL is as below:
size spl/u-boot-spl
   text    data     bss     dec     hex filename
 144572    5484    1752  151808   25100 spl/u-boot-spl

But 20KB is allocated currently for BSS. Reduce it to 4KB and
save some space for stack.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoinclude: configs: am64x: Avoid overlap of BSS and stack area
Lokesh Vutla [Thu, 6 May 2021 11:14:53 +0000 (16:44 +0530)]
include: configs: am64x: Avoid overlap of BSS and stack area

Avoid R5 SPL stack writing into ROM index table. Re-use the same space
for storing EEPROM data.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoarm: am64x: Add support for selecting DT based on EEPROM
Lokesh Vutla [Thu, 6 May 2021 11:14:52 +0000 (16:44 +0530)]
arm: am64x: Add support for selecting DT based on EEPROM

Enable support for selecting DTB within SPL based on EEPROM.
This will help to use single defconfig for both EVM and SK

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoboard: ti: am64x: Add support for detecting multiple device trees
Lokesh Vutla [Thu, 6 May 2021 11:14:51 +0000 (16:44 +0530)]
board: ti: am64x: Add support for detecting multiple device trees

Update the board_fit_config_name_match() to choose the right dtb.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoboard: ti: am64x: Enable support for reading EEPROM in R5 SPL
Lokesh Vutla [Thu, 6 May 2021 11:14:50 +0000 (16:44 +0530)]
board: ti: am64x: Enable support for reading EEPROM in R5 SPL

Include the relevant configs to enable support for reading EEPROM in
R5SPL.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoboard: ti: am64x: Add support for reading eeprom data
Lokesh Vutla [Thu, 6 May 2021 11:14:49 +0000 (16:44 +0530)]
board: ti: am64x: Add support for reading eeprom data

I2C EEPROM data contains the board name and its revision.
Add support for:
- Reading EEPROM data and store a copy at end of SRAM
- Updating env variable with relevant board info
- Printing board info during boot.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agosoc: ti: k3-socinfo: Add entry for AM64X SoC family
Lokesh Vutla [Thu, 6 May 2021 11:14:48 +0000 (16:44 +0530)]
soc: ti: k3-socinfo: Add entry for AM64X SoC family

Add support for AM64 SoC identification.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
3 years agoconfigs: am64x_evm_r5: Enable GPIO regulator
Nishanth Menon [Tue, 4 May 2021 23:00:56 +0000 (18:00 -0500)]
configs: am64x_evm_r5: Enable GPIO regulator

Enable GPIO regulator.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoarm: dts: k3-am642-r5-evm: Add GPIO DDR VTT regulator
Nishanth Menon [Tue, 4 May 2021 23:00:55 +0000 (18:00 -0500)]
arm: dts: k3-am642-r5-evm: Add GPIO DDR VTT regulator

Add DDR VTT regulator.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoarm: dts: k3-am64-main: Add GPIO nodes
Nishanth Menon [Tue, 4 May 2021 23:00:54 +0000 (18:00 -0500)]
arm: dts: k3-am64-main: Add GPIO nodes

Add main domain GPIO nodes.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoarm: mach-k3: am642: Add support for triggering ddr init from SPL
Dave Gerlach [Tue, 4 May 2021 23:00:53 +0000 (18:00 -0500)]
arm: mach-k3: am642: Add support for triggering ddr init from SPL

In SPL, DDR should be made available by the end of board_init_f()
so that apis in board_init_r() can use ddr. Adding support for
triggering DDR initialization from board_init_f().

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoarm: dts: k3-am642: Add ddr node
Dave Gerlach [Tue, 4 May 2021 23:00:52 +0000 (18:00 -0500)]
arm: dts: k3-am642: Add ddr node

Introduce ddr node for am642 needed for all ddr configurations.

Also, introduce the 1600MTs DDR4 configuration that is supported on the
am642-evm.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoram: k3-ddrss: Enable vtt regulator if present
Lokesh Vutla [Tue, 11 May 2021 15:22:13 +0000 (10:22 -0500)]
ram: k3-ddrss: Enable vtt regulator if present

Attempt to get and enable a vtt regulator if one is provided from the
dts. If we do not find one, continue as not all platforms have this.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoram: k3-ddrss: Introduce support for AM642 SoCs
Dave Gerlach [Tue, 11 May 2021 15:22:12 +0000 (10:22 -0500)]
ram: k3-ddrss: Introduce support for AM642 SoCs

Introduce support for the AM64 DDRSS controller which uses the 16bit
variation of the controller. This controller shares much functionality
with the existing J721e support, so this patch introduces only the new
code needed for am64 specific support from "_16bit_" files with headers
under "16bit/" include path/.

Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use
with CONFIG_K3_DDRSS to allow selecting AM64 support.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoram: k3-ddrss: Introduce common driver with J7 SoC support
Dave Gerlach [Tue, 11 May 2021 15:22:11 +0000 (10:22 -0500)]
ram: k3-ddrss: Introduce common driver with J7 SoC support

Introduce a new version of the ddr driver which has the ability to
support different variations of the controller. Also introduce support
for the 32bit variation of the controller which is what was already
supported by the previous version used for J721e and J7200.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSS
Dave Gerlach [Tue, 11 May 2021 15:22:10 +0000 (10:22 -0500)]
ram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSS

Create a new CONFIG_K3_DDRSS option to select the common parts of the
k3-ddrss driver. Also introduce a choice that depends on the top level
option to select CONFIG_K3_J721E_DDRSS for j721e support, and update
corresponding Kconfig as required.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoram: k3-j721e: Rename to k3-ddrss
Dave Gerlach [Tue, 11 May 2021 15:22:09 +0000 (10:22 -0500)]
ram: k3-j721e: Rename to k3-ddrss

Rename the k3-j721e folder under drivers/ram to k3-ddrss in preparation
of introducing additional support for other platforms to the same
driver.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoram: k3-j721e: lpddr4_ctl_regs: Fix checkpatch issue for types
Dave Gerlach [Tue, 11 May 2021 15:22:08 +0000 (10:22 -0500)]
ram: k3-j721e: lpddr4_ctl_regs: Fix checkpatch issue for types

Use Linux style u32 instead of uint32_t.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>