Tom Rini [Fri, 10 Nov 2023 13:44:18 +0000 (08:44 -0500)]
Merge branch '2023-11-10-assorted-fixes'
- Fix some issues Coverity has reported, update MAINTAINERS file,
another bootstd fix, typo fix in error message, gitignore fix and
update TI's URL in many places.
Sam Protsenko [Thu, 26 Oct 2023 21:00:15 +0000 (16:00 -0500)]
tools: gitignore: Fix tools/generated path
'git status' shows 'tools/generated/' after running the build, which is
wrong. The corresponding .gitignore rule was already added in commit c623642d29be ("Adjust gitignore for tools/generated/"), but because of
superfluous 'tools/' part it wasn't in effect. Remove incorrect 'tools/'
part to fix it.
While at it, remove tools/ path incorrectly added to the top-level
.gitignore in commit 801c482207c7 (".gitignore: ignore misc include,
simple-bin, and tools/generated build artifacts"), as it's required in
the comment on the top of .gitignore:
# NOTE! Don't add files that are generated in specific
# subdirectories here. Add them in the ".gitignore" file
# in that subdirectory instead.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Fixes: c623642d29be ("Adjust gitignore for tools/generated/") Fixes: 801c482207c7 (".gitignore: ignore misc include, simple-bin, and tools/generated build artifacts")
Tony Dinh [Thu, 2 Nov 2023 18:51:15 +0000 (11:51 -0700)]
bootstd: Skip over bad device during bootflows scanning
During bootstd scanning for bootdevs, if bootdev_hunt_drv() encounters
a device not found error (e.g. ENOENT), let it return a successful status
so that bootstd will continue scanning the next devices, not stopping
prematurely.
Background:
During scanning for bootflows, it's possible for bootstd to encounter a
faulty device controller. Also when the same u-boot is used for another
variant of the same board, some device controller such as SATA might
not exist.
I've found this issue while converting the Marvell Sheevaplug board to
use bootstd. This board has 2 variants, the original Sheevaplug has MMC and
USB only, but the later variant comes with USB, MMC, and eSATA ports. We
have been using the same u-boot (starting with CONFIG_IDE and later with DM
CONFIG_SATA) for both variants. This worked well with the old
envs-scripting booting scheme.
Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 8 Nov 2023 19:28:11 +0000 (14:28 -0500)]
scsi: Have scsi_init_dev_desc_priv() use memset
When we do not have CONFIG_BOUNCE_BUFFER enabled, inside of
scsi_init_dev_desc_priv we never set the 'bb' field to false, we only
initialize it to true when CONFIG_BOUNCE_BUFFER is set. Given that we
have a number of other fields here we had been explicitly setting to
zero, change to first calling memset to clear the struct and then
initialize only the fields that need non-zero default values.
Addresses-Coverity-ID: 467407 ("Uninitialized variables (UNINIT)") Fixes: 81bd22e935dc ("rockchip: block: blk-uclass: add bounce buffer flag to blk_desc") Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Keep track of the re-entries with help of the lr register.
This binary can be re-used and called from various BROM functions.
Only when it's called from the part that handles SPI, NAND or EMMC
hardware it needs to early return to BROM ones.
In download mode when it handles data on USB OTG and UART0
this section must be skipped.
Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in
support to enter download mode on return to BROM. This binary must check
the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set.
It then returns to BROM to the end of the function that reads boot blocks.
From there the BROM code goes into a download mode and waits for data
on USB OTG and UART0.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Fri, 3 Nov 2023 09:28:13 +0000 (10:28 +0100)]
rockchip: ringneck-px30: enable SPL_BOARD_INIT
Now that Ringneck requires some board-specific code (namely resetting
the MCU companion controller) to be run during SPL stage, let's enable
SPL_BOARD_INIT.
Quentin Schulz [Fri, 3 Nov 2023 09:28:12 +0000 (10:28 +0100)]
rockchip: ringneck-px30: always reset STM32 companion controller on boot
It's happened that glitches on the STM32_RST and STM32_BOOT lines have
put the STM32 companion microcontroller into DFU mode making it not boot
its FW, rendering it useless for the user.
Considering that the STM32 companion microcontroller is always reset on
a reboot or power cycle, resetting it once again in U-Boot SPL isn't
going to hurt it any more.
For ATtiny companion microcontroller, the situation is a bit different
because a reboot or power cycle doesn't reset it. Additionally, since it
can only be reset with a UPDI reset on the STM32_RST line, and that is
virtually impossible to mistakenly trigger, the ATtiny is unlikely to be
in unwanted reset or enter reset because U-Boot toggles STM32_RST line.
Tim Lunn [Mon, 30 Oct 2023 13:12:41 +0000 (00:12 +1100)]
rockchip: dts: fix bootph tags for rv1126
RV1126 fails to boot on 2024.01-rc1.
Commit 9e644284ab81 ("dm: core: Report bootph-pre-ram/sram node as
pre-reloc after relocation") changed the behaviour of bootph-pre-ram, to
limit nodes to spl phase. This caused rv1126 boards to fail to boot with
the current dts.
This patch updates the pmu/grf nodes to bootph-all tags as they are
needed in all phases. This fixes the boot issue on rv1126 boards.
Signed-off-by: Tim Lunn <tim@feathertop.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
QuartzPro64 is a Rockchip RK3588 based SBC by Pine64.
UART and boot over SD/eMMC/RJ45 are tested to work.
Linux commits from next-20231013: 8152d3d070a9 ("arm64: dts: rockchip: Add QuartzPro64 SBC device tree")
Signed-off-by: Tom Fitzhenry <tom@tom-fitzhenry.me.uk> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Cc: Eugen Hristev <eugen.hristev@collabora.com> Cc: Jonas Karlman <jonas@kwiboo.se> Cc: Ondrej Jirman <megi@xff.cz>
Michal Simek [Wed, 1 Nov 2023 12:06:15 +0000 (13:06 +0100)]
arm64: zynqmp: Add description for nvmem efuse layout
Based on discussion with DT folks at link below there is not going to be
any name restrictions for child names. That's why add description for
current nvmem layout.
Michal Simek [Wed, 1 Nov 2023 11:22:14 +0000 (12:22 +0100)]
ARM: zynq: Add partition description
Xilinx is using standard mtd partition layout for quite a long time. It is
used for testing purpose on evaluation boards.
Also #address/size-cells shouldn't be present without nodes which should
use them that's why move them from zynq-7000.dtsi to nand/nor nodes
directly.
The patch was tested on zc706 and zedboard(with also increasing max
frequency and rx bus width).
Michal Simek [Wed, 1 Nov 2023 08:01:03 +0000 (09:01 +0100)]
arm64: zynqmp: Comment all smmu entries
SMMU is disabled by default and not all masters can be enabled at the same
time because of limited number of entries. That's why comment all iommu
properties but keep them for reference in DT. In XEN case they should be
added back and Xen should have SMMU enabled by default.
Also add IDs for DP and DPDMA.
Michal Simek [Thu, 26 Oct 2023 14:04:52 +0000 (16:04 +0200)]
arm64: versal-net: Add DTSes for mini qspi/ospi configuration
Mini U-Boot is running out of OCM and it's only purpose is to program non
volatile memories. There are different configurations which ospi/qspi can
be that's why describe them via DT.
DT binding is already approved that's why there is no reason not to add it.
Michal Simek [Thu, 26 Oct 2023 14:04:51 +0000 (16:04 +0200)]
arm64: versal: Add DTSes for mini qspi/ospi configuration
Mini U-Boot is running out of OCM and it's only purpose is to program non
volatile memories. There are different configurations which ospi/qspi can
be that's why describe them via DT.
DT binding is already approved that's why there is no reason not to add it.
Michal Simek [Thu, 26 Oct 2023 14:04:50 +0000 (16:04 +0200)]
ARM: zynq: Add DTSes for mini qspi configurations
Mini U-Boot is running out of OCM and it's only purpose is to program non
volatile memories. There are different configurations which qspi can be
that's why describe them via DT.
DT binding is already approved that's why there is no reason not to add it.
Michal Simek [Thu, 26 Oct 2023 14:04:49 +0000 (16:04 +0200)]
ARM: zynq: Add DTSes for mini qspi configurations
Mini U-Boot is running out of OCM and it's only purpose is to program non
volatile memories. There are different configurations which qspi can be
that's why describe them via DT.
DT binding is already approved that's why there is no reason not to add it.
The Standard Host Controller Interface (SDHCI) specification version
3.00 adds support for Advanced DMA (ADMA) for both 64 and 32 bit
widths of DMA. This significantly improves read and write throughput.
Tejas Bhumkar [Fri, 20 Oct 2023 05:06:22 +0000 (10:36 +0530)]
arm64: zynqmp: Disable Tri-state for MIO38 Pin
gpio38 is used in SOM's kv260 to reset the Ethernet PHY.
At present, HW reset is not working properly as Tri-state
is enabled for MIO38, causing inappropriate PHY register reads.
Disabled Tri-state for MIO38 to make HW reset work.
arm64: dts: zynqmp: make hw-ecc as the default ecc mode
Except for Linux no other component (i.e., u-boot, fsbl or BootRom) of the
software stack supports software ecc engine. So, make hw-ecc as the default
ecc mode.
This power domain shouldn't be enabled by default. Power domain behavior
should be handled on case by case basis. Adding this property to
zynqmp.dtsi is breaking some suspend/resume cases that's why remove it
from this file.
Michal Simek [Thu, 12 Oct 2023 08:22:16 +0000 (10:22 +0200)]
arm64: zynqmp: Remove fclk driver
fclk will never go upstream that's why removing this node from DT.
All PL (programmable logic) based IPs should handle clocks self without
using this workaround.
spi: cadence_ospi_versal: Add support for 64-bit address
When 64-bit address is passed only lower 32-bit address
is getting updated. Program the upper 32-bit address in the
DMA destination memory address MSBs register.
drivers: firmware: Handle error case in the zynqmp_pm_feature
Unhandled error coming from xilinx_pm_request() but return
value is not read back that's why getting sparse warning
as below:
warning: variable 'ret' set but not used [-Wunused-but-set-variable].
In case of error return the "ret" value.
Provide an explicit configuration option to disable default "lock"
of any flash chip which supports locking. By disabling the lock
config will save some amount of memory and also don't expose the
lock functionality to the users i.e., via sf protect command.
serial: zynqmp: Fetch baudrate from dtb and update
The baudrate configured in .config is taken by default by serial. If
change of baudrate is required then the .config needs to changed and
u-boot recompilation is required or the u-boot environment needs to be
updated.
To avoid this, support is added to fetch the baudrate directly from the
device tree file and update.
The serial, prints the log with the configured baudrate in the dtb.
The commit c4df0f6f315c ("arm: mvebu: Espressobin: Set default value for
$fdtfile env variable") is taken as reference for changing the default
environment variable.
The default environment stores the default baudrate value, When default
baudrate and dtb baudrate are not same glitches are seen on the serial.
So, the environment also needs to be updated with the dtb baudrate to
avoid the glitches on the serial.
configs: Add support in Kconfig and convert for armada boards
Move the DEFAULT_ENV_IS_RW to Kconfig for easier configuration.
Hence, add the CONFIG_DEFAULT_ENV_IS_RW config to the defconfig files
to allow enabling them for armada boards.
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230921112043.3144726-2-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
Dmitry Rokosov [Wed, 1 Nov 2023 14:04:57 +0000 (17:04 +0300)]
drivers: sm: bind child sm devices in the device tree
One well-known sm child device that provides secure power control is the
Secure Power Controller. This device utilizes SMC calls to communicate
with power domains on the secure monitor side.
Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Signed-off-by: Alexey Romanov <avromanov@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231101140500.9025-3-avromanov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Baruch Siach [Wed, 25 Oct 2023 08:08:44 +0000 (11:08 +0300)]
net: designware: add DMA offset awareness
Older DesignWare Ethernet MAC versions that this driver supports can
only work with 32-bit DMA source/destination addresses. Some platforms
have no physical RAM at the lowest 4GB address space. For these
platforms the driver must translate DMA addresses to/from physical
memory addresses.
Call translation routines so that properly configured platforms can use
the DesignWare Ethernet MAC. For platforms using device-tree this
usually means adding dma-ranges property to the bus the device node is
in.
Bin Meng [Wed, 11 Oct 2023 10:58:25 +0000 (18:58 +0800)]
net: e1000: Drop e1000_eth_ids[]
e1000_eth_ids holds compatible strings for e1000 devices, but it
is meaningless as e1000 is a PCI device and there is no such
compatible string assigned to e1000 by the DT bindings community.
Drop it.
Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sun, 8 Oct 2023 01:53:12 +0000 (21:53 -0400)]
net: Add option for tracing packets
Add an option to trace all packets send/received. This can be helpful when
debugging protocol issues, as the packets can then be imported into
wireshark [1] and analyzed further.
net: phy: TI DP83869 fix invalid clock delay configuration
Setting the clock delay from the device tree settings
rx-internal-delay-ps and tx-internal-delay-ps was broken:
- The expected value in the device tree is suppose to be a
delay in picoseconds, but the driver only allowed an array index.
- Driver converted this array index to the actual delay in
picoseconds and tried to apply this in the device register. This
however is not a valid register value. The actual logic here was
reversed, it converted an register representation of the delay to
the device tree delay in picoseconds.
Only when the internal delays were NOT configured in the device tree
and they default value of 7 (=2000ps) was used, a valid value was
loaded in the register.
Signed-off-by: Frank de Brabander <debrabander@gmail.com>
Michal Simek [Fri, 15 Sep 2023 14:10:06 +0000 (16:10 +0200)]
net: eth-uclass: Setup ROM source only when ROM reading passes
There is no reason to setup ROM source if read_rom_hwaddr hook doesn't
exist or reading mac address fails. It is ending up with confusion about
mac address source.
It is nicely visible if you put mac address to DT as
local-mac-address = [ff ff ff ff ff ff];
but also save ethaddr to variables
setenv -f ethaddr 02:18:31:7e:3e:01
Before this patch U-Boot prints that source is ROM
Address in ROM is ff:ff:ff:ff:ff:ff
Address in environment is 02:18:31:7e:3e:01
After that source is DT:
Address in DT is ff:ff:ff:ff:ff:ff
Address in environment is 02:18:31:7e:3e:01
Signed-off-by: Michal Simek <michal.simek@amd.com>
Yang Xiwen [Tue, 22 Aug 2023 17:03:42 +0000 (01:03 +0800)]
net: add hifemac Ethernet driver for HiSilicon platform
It adds the driver for HIFEMAC Ethernet controller found on HiSilicon
SoCs like Hi3798MV200. It's based on the mainstream linux driver, but
quite a lot of code gets rewritten and cleaned up to adopt u-boot driver
model.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Robert Marko [Tue, 8 Aug 2023 16:05:16 +0000 (18:05 +0200)]
net: mv88e6xxx: add Clause 45 support
Marvell LinkStreet switches support Clause 45 MDIO on the internal bus.
C45 read or writes require the register address to be written first to
the SMI PHY Data register, and then a special C45 Write Address Register
OP is used on the SMI PHY Register before making a C45 Read Data Register
OP and being able to actually read the register.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Robert Marko [Tue, 8 Aug 2023 16:05:15 +0000 (18:05 +0200)]
net: mv88e6xxx: use generic bitfield macros for MDIO
Driver is currently defining the mask and bit shifting itself,
there is no need for that as U-Boot has generic bitfield macros that help
us achieve the same result but in a cleaner way.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Sean Edmond [Tue, 25 Jul 2023 23:13:29 +0000 (16:13 -0700)]
net: dhcp6: Fix OPT_BOOTFILE_PARAM parsing
RFC 5970 states that OPT_BOOTFILE_PARAM (option 60) can be
multiple parameters that start with a 16-bit length field followed
by the parameter. For example:
[ param-len 1 (16-bits) ] [ parameter 1 (variable length) ]
This fix ensure we're considering "param-len 1" in the parsing.
Signed-off-by: Sean Edmond <seanedmond@microsoft.com>
Svyatoslav Ryhel [Tue, 24 Oct 2023 07:49:03 +0000 (10:49 +0300)]
sysreset: tegra: create arch specific sysreset driver
Tegra uses built in Power Management Controller (PMC) to perform
CPU reset. Code to perform this was located in mach-tegra, so lest
create DM driver to handle this.
Svyatoslav Ryhel [Fri, 27 Oct 2023 08:26:09 +0000 (11:26 +0300)]
power: regulator: palmas: fix ldoln and ldousb detection
dev->driver_data will carry the tail of ldo if there is a number and
if there is no number it will be an error code, anyway it will not be
zero. This results in a wrong ldo regulator detection.
To avoid this check for non-numerical ldo first and then manipulate
dev->driver_data.
Svyatoslav Ryhel [Fri, 27 Oct 2023 08:26:08 +0000 (11:26 +0300)]
power: pmic: palmas: support TI TPS65913 PMIC
Existing PALMAS PMIC driver is fully compatible with TI TPS65913
PMIC found in many Tegra 4 devices, like Tegra Note 7 and ASUS
TF701T. TPS65913 shares same structure of regulators like TPS659038
so data can be reused.
Remove nvidia_board_late_init calls from board since this setup is
performed in board2 of mach-tegra. Call of nvidia_board_late_init
from within the board does not provide any additional data.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Transformer T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Board specific late init allows vendors to set up different device
or board specific env variables (like serial number, platform name).
In case this information is missing, u-boot will lack info regards
serial or platform.
To avoid this prior nvidia_board_late_init internal generic function
is called which fills required data. In this case platform name is
obtained from get_chip and serialno is filled with SoC id.
Though SoC id is not dedicated to be devices serial but it fits well
in case of restriction of data about device and since SoC is basically
a main chip of the device.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Transformers Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
ARM: tegra20: tegra30: support EBTUPDATE on non-encrypted devices
Re-crypt support was extended to devices without burnt SBK. In case
SBK is not set, place from where it is read is filled with zeroes.
This patch adds support for ebtupdate function to detect nosbk device
and avoid crypto operations for it.
Tested-by: Maksim Kurnosenko <asusx2@mail.ru> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
ARM: tegra114: enable base voltages setup from board
Tegra 4, same as Tegra 3, requires configuration of CPU and CORE
voltages in the SPL stage to boot properly. Expose function to be
able perform this configuration in the SPL section of the device
board.
projects / u-boot.git / log