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3 years agomtd: nand: raw: convert nand_dt_init() to ofnode_xx() interface
Patrice Chotard [Mon, 13 Sep 2021 14:25:53 +0000 (16:25 +0200)]
mtd: nand: raw: convert nand_dt_init() to ofnode_xx() interface

nand_dt_init() is still using fdtdec_xx() interface.
If OF_LIVE flag is enabled, dt property can't be get anymore.
Updating all fdtdec_xx() interface to ofnode_xx() to solve this issue.

For doing this, node parameter type must be ofnode.

First idea was to convert "node" parameter to ofnode type inside
nand_dt_init() using offset_to_ofnode(node). But offset_to_ofnode()
is not bijective, in case OF_LIVE flag is enabled, it performs an assert().

So, this leads to update nand_chip struct flash_node field from int to
ofnode and to update all nand_dt_init() callers.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agomtd: spi: Set CONFIG_SF_DEFAULT_MODE default to 0
Marek Vasut [Tue, 14 Sep 2021 18:28:24 +0000 (20:28 +0200)]
mtd: spi: Set CONFIG_SF_DEFAULT_MODE default to 0

Before e2e95e5e254 ("spi: Update speed/mode on change") most systems
silently defaulted to SF bus mode 0. Now the mode is always updated,
which causes breakage. It seems most SF which are used as boot media
operate in bus mode 0, so switch that as the default.

This should fix booting at least on Altera SoCFPGA, ST STM32, Xilinx
ZynqMP, NXP iMX and Rockchip SoCs, which recently ran into trouble
with mode 3. Marvell Kirkwood and Xilinx microblaze need to be checked
as those might need mode 3.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Cc: Andreas Biessmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
3 years agomtd: spi: nor: force mtd name to "nor%d"
Patrick Delaunay [Wed, 22 Sep 2021 16:29:08 +0000 (18:29 +0200)]
mtd: spi: nor: force mtd name to "nor%d"

Force the mtd name of spi-nor to "nor" + the driver sequence number:
"nor0", "nor1"... beginning after the existing nor devices.

This patch is coherent with existing "nand" and "spi-nand"
mtd device names.

When CFI MTD NOR device are supported, the spi-nor index is chosen after
the last CFI device defined by CONFIG_SYS_MAX_FLASH_BANKS.

When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated, this config
is replaced by to cfi_flash_num_flash_banks in the include file
mtd/cfi_flash.h.

This generic name "nor%d" can be use to identify the mtd spi-nor device
without knowing the real device name or the DT path of the device,
used with API get_mtd_device_nm() and is used in mtdparts command.

This patch also avoids issue when the same NOR device is present 2 times,
for example on STM32MP15F-EV1:

STM32MP> mtd list
SF: Detected mx66l51235l with page size 256 Bytes, erase size 64 KiB, \
total 64 MiB

List of MTD devices:
* nand0
  - type: NAND flash
  - block size: 0x40000 bytes
  - min I/O: 0x1000 bytes
  - OOB size: 224 bytes
  - OOB available: 118 bytes
  - ECC strength: 8 bits
  - ECC step size: 512 bytes
  - bitflip threshold: 6 bits
  - 0x000000000000-0x000040000000 : "nand0"
* mx66l51235l
  - device: mx66l51235l@0
  - parent: spi@58003000
  - driver: jedec_spi_nor
  - path: /soc/spi@58003000/mx66l51235l@0
  - type: NOR flash
  - block size: 0x10000 bytes
  - min I/O: 0x1 bytes
  - 0x000000000000-0x000004000000 : "mx66l51235l"
* mx66l51235l
  - device: mx66l51235l@1
  - parent: spi@58003000
  - driver: jedec_spi_nor
  - path: /soc/spi@58003000/mx66l51235l@1
  - type: NOR flash
  - block size: 0x10000 bytes
  - min I/O: 0x1 bytes
  - 0x000000000000-0x000004000000 : "mx66l51235l"

The same mtd name "mx66l51235l" identify the 2 instances
mx66l51235l@0 and mx66l51235l@1.

This patch fixes a ST32CubeProgrammer / stm32prog command issue
with nor0 target on STM32MP157C-EV1 board introduced by
commit b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when
DM is enabled").

Fixes: b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
[trini: Add <dm/device.h> to <mtd.h> for DM_MAX_SEQ_STR]
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agomtd: cfi_flash: use cfi_flash_num_flash_banks only when supported
Patrick Delaunay [Wed, 22 Sep 2021 16:29:07 +0000 (18:29 +0200)]
mtd: cfi_flash: use cfi_flash_num_flash_banks only when supported

When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated,
CONFIG_SYS_MAX_FLASH_BANKS is replaced by cfi_flash_num_flash_banks,
but this variable is defined in drivers/mtd/cfi_flash.c, which is
compiled only when CONFIG_FLASH_CFI_DRIVER is activated, in U-Boot
or in SPL when CONFIG_SPL_MTD_SUPPORT is activated.

This patch deactivates this feature CONFIG_SYS_MAX_FLASH_BANKS_DETECT
when flash cfi driver is not activated to avoid compilation issue in
the next patch, when CONFIG_SYS_MAX_FLASH_BANKS is used in spi_nor_scan().

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agoPrepare v2021.10-rc5
Tom Rini [Mon, 27 Sep 2021 13:34:20 +0000 (09:34 -0400)]
Prepare v2021.10-rc5

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-marvell
Tom Rini [Mon, 27 Sep 2021 11:41:03 +0000 (07:41 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- turris_omnia: fix leaked mtd device (Marek)
- phy: marvell: cp110: Fix SATA invert polarity (Denis)

3 years agophy: marvell: cp110: Support SATA invert polarity
Denis Odintsov [Wed, 15 Sep 2021 13:45:31 +0000 (15:45 +0200)]
phy: marvell: cp110: Support SATA invert polarity

In commit b24bb99d cp110 configuration initially done in u-boot
was removed and delegated to atf firmware as smc call.
That commit didn't account for later introduced in d13b740c SATA invert polarity support.

This patch adds support of passing SATA invert polarity flags to atf
firmware during the smc call.

Signed-off-by: Denis Odintsov <shiva@mail.ru>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: mvebu: turris_omnia: fix leaked mtd device
Marek Behún [Sat, 25 Sep 2021 00:49:18 +0000 (02:49 +0200)]
arm: mvebu: turris_omnia: fix leaked mtd device

After getting MTD device via get_mtd_device_nm(), we need to put it with
put_mtd_device(), otherwise we get

  Removing MTD device #0 (mx25l6405d) with use count 1

before booting kernel.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Tested-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoMerge tag 'efi-2021-10-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi
Tom Rini [Sun, 26 Sep 2021 18:15:14 +0000 (14:15 -0400)]
Merge tag 'efi-2021-10-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2021-10-rc5

Documentation:

* add /config bindings to HTML documentation

UEFI

* Fix number_of_algorithms field in TCG EFI Protocol

3 years agoefi_loader: Fix spec ID event creation
Ruchika Gupta [Tue, 14 Sep 2021 06:44:31 +0000 (12:14 +0530)]
efi_loader: Fix spec ID event creation

TCG EFI Protocol Specification defines the number_of_algorithms
field in spec ID event to be equal to the number of active
algorithms supported by the TPM device. In current implementation,
this field is populated with the count of all algorithms supported
by the TPM which leads to incorrect spec ID event creation.

Similarly, the algorithm array in spec ID event should be a variable
length array with length being equal to the number_of_algorithms field.
In current implementation this is defined as a fixed length array
which has been fixed.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
CC: Masahisa Kojima <masahisa.kojima@linaro.org>
CC: Ilias Apalodimas <ilias.apalodimas@linaro.org>
CC: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
3 years agodoc: Add mention of the /config binding
Simon Glass [Sun, 19 Sep 2021 21:51:10 +0000 (15:51 -0600)]
doc: Add mention of the /config binding

The devicetree binding files are in their own directory and use a simple
text format. Add a link for the binding for the /config node, since it
is otherwise hard to find.

Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoMerge branch '2021-09-24-assorted-minor-updates'
Tom Rini [Fri, 24 Sep 2021 18:28:54 +0000 (14:28 -0400)]
Merge branch '2021-09-24-assorted-minor-updates'

- Assorted bugfixes, MAINTAINER updates and dead code removal

3 years agoarm: orion5x: edminiv2: change maintainer
Simon Guinot [Wed, 15 Sep 2021 13:01:51 +0000 (15:01 +0200)]
arm: orion5x: edminiv2: change maintainer

Since Albert Aribaud is not maintaining anymore the LaCie Ethernet Disk
mini V2 board, then I am taking over.

Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agomtd: remove SPEAr flash driver st_smi
Patrick Delaunay [Wed, 22 Sep 2021 09:02:26 +0000 (11:02 +0200)]
mtd: remove SPEAr flash driver st_smi

Remove the driver st_smic.c used in SPEAr products and the associated
config CONFIG_ST_SMI; this driver is no more used in U-Boot after the
commit 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr
support").

Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
3 years agoTaking over responsibility for GE boards from Sebastian
Martyn Welch [Tue, 21 Sep 2021 16:35:06 +0000 (17:35 +0100)]
Taking over responsibility for GE boards from Sebastian

I am taking over responsibility for the GE board from Sebastian Reichel.
Updating the MAINTAINERS files to reflect this.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
3 years agoMAINTAINERS: remove SPEAR entry
Patrick Delaunay [Tue, 21 Sep 2021 16:18:51 +0000 (18:18 +0200)]
MAINTAINERS: remove SPEAR entry

As the lastest spear directories are removed, delete the associated entry
in the MAINTAINERS file:
- arch/arm/cpu/arm926ejs/spear/
- arch/arm/include/asm/arch-spear/

Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agofs: avoid superfluous messages
Heinrich Schuchardt [Mon, 20 Sep 2021 12:15:03 +0000 (14:15 +0200)]
fs: avoid superfluous messages

Output like the following is quite irritating:

    => bootefi hello
    Scanning disk mmc2.blk...
    No valid Btrfs found
    Bad magic number for SquashFS image.
    ** Unrecognized filesystem type **
    Scanning disk mmc1.blk...
    No valid Btrfs found
    Bad magic number for SquashFS image.
    ** Unrecognized filesystem type **
    Scanning disk mmc0.blk...
    No valid Btrfs found
    Bad magic number for SquashFS image.
    ** Unrecognized filesystem type **

Albeit a whole disk may be formatted with a filesystem in most cases
a partition table is used and the whole disk (partition number 0) doesn't
contain a filesytem. Some partitions may only contain a blob. Not seeing a
filesytem on the whole disk or on any partition is only worth a debug
message.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoscripts/mailmapper: enable running with Python 3
Heinrich Schuchardt [Thu, 16 Sep 2021 08:59:12 +0000 (10:59 +0200)]
scripts/mailmapper: enable running with Python 3

Our mailmapper script required Python 2 which is no longer maintained.
A main difference when converting to Python 3 is that byte strings are not
character strings. So add conversion and skip over conversion errors.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
3 years agotest/py: tpm2: Skip tpm pytest based on env variable
T Karthik Reddy [Fri, 23 Jul 2021 12:18:26 +0000 (06:18 -0600)]
test/py: tpm2: Skip tpm pytest based on env variable

Tpm test cases relies on tpm device setup. Provide an environment
variable "env__tpm_device_test_skip = True" to skip the test case
if tpm device is not present.
Only needed will have to add variable to the py-test framework.
Test runs successfully even this variable is absent.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
3 years agoMerge git://source.denx.de/u-boot-socfpga
Tom Rini [Thu, 23 Sep 2021 12:30:45 +0000 (08:30 -0400)]
Merge git://source.denx.de/u-boot-socfpga

Bugfixes for this one socfpga platform

3 years agoMerge branch 'master' of git://source.denx.de/u-boot-usb
Tom Rini [Thu, 23 Sep 2021 12:30:22 +0000 (08:30 -0400)]
Merge branch 'master' of git://source.denx.de/u-boot-usb

Late bunch of USB fixes (incl. the xhci usb 3.1 support)

3 years agoddr: altera: use KBUILD_BASENAME instead of __FILE__
Marek Vasut [Tue, 14 Sep 2021 03:20:19 +0000 (05:20 +0200)]
ddr: altera: use KBUILD_BASENAME instead of __FILE__

The KBUILD_BASENAME contains just the name of the compiled module,
in this case 'sequencer', rather than a full path to the compiled
file. Use it to prevent pulling the full path into the U-Boot binary,
which is useless and annoying.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
3 years agoarm: socfpga: vining: Let DWMAC configure PHY reset GPIO
Marek Vasut [Tue, 14 Sep 2021 03:25:36 +0000 (05:25 +0200)]
arm: socfpga: vining: Let DWMAC configure PHY reset GPIO

The DM DWMAC driver is perfectly capable of configuring the ethernet
PHY reset GPIO, let the driver do it instead of doing it in the board
file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
3 years agoarm: socfpga: vining: Enable DW I2C driver
Marek Vasut [Tue, 14 Sep 2021 03:25:35 +0000 (05:25 +0200)]
arm: socfpga: vining: Enable DW I2C driver

The Designware I2C IP is used to communicate with I2C peripherals on
SoCFPGA, and required to access I2C EEPROM on this board. Enable it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
3 years agoarm: socfpga: vining: Fix UDC controller phandle in DT
Marek Vasut [Tue, 14 Sep 2021 03:25:34 +0000 (05:25 +0200)]
arm: socfpga: vining: Fix UDC controller phandle in DT

The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
3 years agoarm: socfpga: vining: Un-disable WDT in DT
Marek Vasut [Tue, 14 Sep 2021 03:25:33 +0000 (05:25 +0200)]
arm: socfpga: vining: Un-disable WDT in DT

The WDT on this system should be enabled, make it so.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
3 years agoarm: socfpga: vining: Set default SPI NOR mode and frequency
Marek Vasut [Tue, 14 Sep 2021 03:25:32 +0000 (05:25 +0200)]
arm: socfpga: vining: Set default SPI NOR mode and frequency

The SPI NOR bus mode is 0 on this system, update it accordingly.
Increase frequency to 40 MHz and enable SFDP parsing, since the
flashes on this system support that and it is a huge performance
improvement.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
3 years agoarm: socfpga: vining: Set USB gadget manufacturer to Softing with capital S
Marek Vasut [Tue, 14 Sep 2021 03:25:31 +0000 (05:25 +0200)]
arm: socfpga: vining: Set USB gadget manufacturer to Softing with capital S

This was configured in downstream, so it is likely that most of the
custom software used around the device depends on it. Make upstream
compatible.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
3 years agoarm: socfpga: vining: Increase environment size
Marek Vasut [Tue, 14 Sep 2021 03:25:30 +0000 (05:25 +0200)]
arm: socfpga: vining: Increase environment size

Increase the environment size from 4k to 16k to prevent
environment from becoming full.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
3 years agoarm: socfpga: vining: Drop meaningless comment
Marek Vasut [Tue, 14 Sep 2021 03:25:29 +0000 (05:25 +0200)]
arm: socfpga: vining: Drop meaningless comment

The comment is no longer meaningful due to DT conversion, drop it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
3 years agousb: xhci-dwc3: Add support for USB 3.1 controllers
Mark Kettenis [Thu, 16 Sep 2021 14:00:09 +0000 (16:00 +0200)]
usb: xhci-dwc3: Add support for USB 3.1 controllers

This adds support for the DWC_sub31 controllers such as those
found on Apple's M1 SoC.  This version of the controller
seems to work fine with the existing driver.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
3 years agousb: ehci-mx6: use phy_type from device tree
Matthias Schiffer [Mon, 20 Sep 2021 13:37:25 +0000 (15:37 +0200)]
usb: ehci-mx6: use phy_type from device tree

Allow using different PHY interfaces for multiple USB controllers. When no
value is set in DT, we fall back to CONFIG_MXC_USB_PORTSC for now to stay
compatible with current board configurations.

This also adds support for the HSIC mode of the i.MX7.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
3 years agousb: ehci-ci: remove redundant PORTSC flag definitions
Matthias Schiffer [Mon, 20 Sep 2021 13:37:24 +0000 (15:37 +0200)]
usb: ehci-ci: remove redundant PORTSC flag definitions

These definitions are unused, all boards that define portsc flags use
the equivalent PORT_* definitions instead.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
3 years agoinclude/configs: replace MXC_EHCI_MODE_SERIAL with PORT_PTS_SERIAL
Matthias Schiffer [Mon, 20 Sep 2021 13:37:23 +0000 (15:37 +0200)]
include/configs: replace MXC_EHCI_MODE_SERIAL with PORT_PTS_SERIAL

The MXC_EHCI_MODE_ definitions are redundant. Replace MXC_EHCI_MODE_SERIAL
with the equivalent PORT_PTS_SERIAL.

Only the zmx25 platform is affected.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
3 years agousb: add support for ULPI/SERIAL/HSIC PHY modes
Matthias Schiffer [Mon, 20 Sep 2021 13:37:22 +0000 (15:37 +0200)]
usb: add support for ULPI/SERIAL/HSIC PHY modes

Import usb_phy_interface enum values and DT match strings from the Linux
kernel.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
3 years agoconfigs: Enable USB3 on Allwinner H6 boards
Samuel Holland [Mon, 5 Jul 2021 12:29:04 +0000 (13:29 +0100)]
configs: Enable USB3 on Allwinner H6 boards

Pine H64 and Orange Pi 3 both provide a USB3 type A port.
Enable it in U-Boot.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
3 years agousb: xhci-dwc3: Add support for clocks/resets
Samuel Holland [Mon, 5 Jul 2021 12:29:03 +0000 (13:29 +0100)]
usb: xhci-dwc3: Add support for clocks/resets

Some platforms, like the Allwinner H6, do not have a separate glue layer
around the dwc3. Instead, they rely on the clocks/resets/phys referenced
from the dwc3 DT node itself. Add support for enabling the clocks/resets
referenced from the dwc3 DT node.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
3 years agousb: xhci-pci: Move reset logic out of XHCI core
Samuel Holland [Mon, 5 Jul 2021 12:29:02 +0000 (13:29 +0100)]
usb: xhci-pci: Move reset logic out of XHCI core

Resetting an XHCI controller inside xhci_register undoes any register
setup performed by the platform driver. And at least on the Allwinner
H6, resetting the XHCI controller also resets the PHY, which prevents
the controller from working. That means the controller must be taken out
of reset before initializing the PHY, which must be done before calling
xhci_register.

The logic in the XHCI core was added to support the Raspberry Pi 4
(although this was not mentioned in the commit log!), which uses the
xhci-pci platform driver. Move the reset logic to the platform driver,
where it belongs, and where it cannot interfere with other platform
drivers.

This also fixes a failure to call reset_free if xhci_register failed.

Fixes: 0b80371b350e ("usb: xhci: Add reset controller support")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
3 years agophy: sun50i-usb3: Add a driver for the H6 USB3 PHY
Samuel Holland [Mon, 5 Jul 2021 12:29:01 +0000 (13:29 +0100)]
phy: sun50i-usb3: Add a driver for the H6 USB3 PHY

This driver is needed for XHCI to work on the Allwinner H6 SoC. The
driver is copied from Linux v5.10.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-x86
Tom Rini [Wed, 22 Sep 2021 15:43:12 +0000 (11:43 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-x86

- Small fixes to eMMC and SDHCI for Intel Edison

3 years agox86: tangier: acpi: Add GPIO card detection to SDHCI #2
Andy Shevchenko [Sat, 11 Sep 2021 18:27:42 +0000 (21:27 +0300)]
x86: tangier: acpi: Add GPIO card detection to SDHCI #2

On Intel Tangier the SDHCI #2 provides SD card connection.
Add GPIO card detection for it.

Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier")
BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
3 years agox86: edison: Mark eMMC non-removable
Andy Shevchenko [Fri, 10 Sep 2021 07:59:27 +0000 (10:59 +0300)]
x86: edison: Mark eMMC non-removable

eMMC is non-removable on Intel Edison board. Fix the DTS accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agoMerge tag 'u-boot-stm32-20210921' of https://source.denx.de/u-boot/custodians/u-boot-stm
Tom Rini [Wed, 22 Sep 2021 13:38:48 +0000 (09:38 -0400)]
Merge tag 'u-boot-stm32-20210921' of https://source.denx.de/u-boot/custodians/u-boot-stm

- stm32mp15: fix the used partition name for U-Boot environement with SPL

3 years agoarm: dts: stm32mp1: use ssbl partition name for U-Boot
Patrick Delaunay [Tue, 14 Sep 2021 12:14:52 +0000 (14:14 +0200)]
arm: dts: stm32mp1: use ssbl partition name for U-Boot

Continue to use the "ssbl" name for GPT partition of secondary boot
stage = U-Boot for basic boot with SPL to avoid to disturb existing user.

The "fip" partition name is only used for TFA_BOOT with FIP, it is a TF-A
BL2 requirement; it the default configuration for STMicroelectronics
boards.

Fixes: b73e8bf453f8 ("arm: stm32mp: add defconfig for trusted boot with FIP")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-marvell
Tom Rini [Mon, 20 Sep 2021 12:45:26 +0000 (08:45 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- wdt: dw: Fix passing NULL pointer to reset functions (Sean)

3 years agowdt: dw: Fix passing NULL pointer to reset functions
Sean Anderson [Sat, 11 Sep 2021 19:11:30 +0000 (15:11 -0400)]
wdt: dw: Fix passing NULL pointer to reset functions

reset_*_bulk expects a real pointer.

Fixes: 4f7abafe1c ("driver: watchdog: reset watchdog in designware_wdt_stop() function")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoMerge tag 'dm-pull-18sep21' of https://source.denx.de/u-boot/custodians/u-boot-dm
Tom Rini [Sun, 19 Sep 2021 14:38:20 +0000 (10:38 -0400)]
Merge tag 'dm-pull-18sep21' of https://source.denx.de/u-boot/custodians/u-boot-dm

Revert the public-key-embedded-in-executable patches so this does not form
part of an official release before it is agreed.

3 years agoRevert "efi_capsule: Move signature from DTB to .rodata"
Simon Glass [Mon, 2 Aug 2021 14:44:31 +0000 (08:44 -0600)]
Revert "efi_capsule: Move signature from DTB to .rodata"

This was unfortunately applied despite much discussion about it beiong
the wrong way to implement this feature.

Revert it before too many other things are built on top of it.

This reverts commit ddf67daac39de76d2697d587148f4c2cb768f492.
Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agoRevert "mkeficapsule: Remove dtb related options"
Simon Glass [Mon, 2 Aug 2021 14:44:30 +0000 (08:44 -0600)]
Revert "mkeficapsule: Remove dtb related options"

This reverts commit f86caab058ff062ce72b24cd1ab9ec1253cc1352.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agoRevert "doc: Update CapsuleUpdate READMEs"
Simon Glass [Mon, 2 Aug 2021 14:44:29 +0000 (08:44 -0600)]
Revert "doc: Update CapsuleUpdate READMEs"

This reverts commit 316ab801c0d91c02b21b8be1e3db7e69555364e9.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agoMerge branch '2021-09-17-TI-platform-updates'
Tom Rini [Fri, 17 Sep 2021 22:51:57 +0000 (18:51 -0400)]
Merge branch '2021-09-17-TI-platform-updates'

- Assorted bugfixes for TI platforms

3 years agoarm: mach-k3: common: Make sure firmware sections are loaded prior to armv8 startup
Nishanth Menon [Tue, 31 Aug 2021 18:20:48 +0000 (13:20 -0500)]
arm: mach-k3: common: Make sure firmware sections are loaded prior to armv8 startup

With Device Manager firmware in an elf file form, we cannot load the FIT
image to the exact same address as any of the executable sections of the
elf file itself is located.

However, the device tree descriptions for the ARMV8 bootloader/OS
includes DDR regions only the final sections in DDR where the Device
Manager firmware is actually executing out of.

As the R5 uC is usually operating at a slower rate than an ARMv8 MPU,
by starting the Armv8 ahead of parsing the elf and copying the correct
sections to the required memories creates a race condition where the
ARMv8 could overwrite the elf image loaded from the FIT image prior to
the R5 completing parsing and putting the correct sections of elf in
the required memory locations. OR create rather obscure debug conditions
where data in the section is being modified by ARMV8 OS while the elf
copy is in progress.

To prevent all these conditions, lets make sure that the elf parse and
copy operations are completed ahead of ARMv8 being released to execute.

We will pay a penalty of elf copy time, but that is a valid tradeoff in
comparison to debug of alternate scenarios.

Signed-off-by: Nishanth Menon <nm@ti.com>
3 years agoarm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge
Roger Quadros [Wed, 8 Sep 2021 20:28:59 +0000 (15:28 -0500)]
arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge

NB0 is bridge to SRAM and NB1 is bridge to DDR.

To ensure that SRAM transfers are not stalled due to delays during DDR
refreshes, SRAM traffic should be higher priority (threadmap=2) than
DDR traffic (threadmap=0).

This fixup is critical to provide deterministic access latency to
MSMC from ICSSG, it applies to all AM65 silicon revisions and is due
to incorrect reset values (has no erratum id) and statically setting
things up should be done independent of usecases and board.

This specific style of Northbridge configuration is specific only to
AM65x devices, follow-on K3 devices have different data prioritization
schemes (ASEL and the like) and hence the fixup applies purely to
AM65x.

Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in
case of SR1 devices, on SR2 devices, lockups were not observed so far
but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower
throughput.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Benoit Parrot <bparrot@ti.com>
[Jan: rebased, dropped used define, extended commit log]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
[Nishanth: Provide relevant context in the commit message]
Signed-off-by: Nishanth Menon<nm@ti.com>
3 years agoclk: ti: k3: Update driver to account for divider flags
Suman Anna [Tue, 7 Sep 2021 22:16:58 +0000 (17:16 -0500)]
clk: ti: k3: Update driver to account for divider flags

The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in
turn serve as inputs to other HSDIV output clocks. These clocks use
the actual value to compute the divider clock rate, and need to be
registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk
driver and data lacks the infrastructure to pass in divider flags.
Update the driver and data to account for these divider flags.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoclk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write
Dave Gerlach [Tue, 7 Sep 2021 22:16:57 +0000 (17:16 -0500)]
clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write

There are three different divider values in the DIV_CTRL register
controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate
function writes the entire register when programming plld, even though
plld only resides in the lower 6 bits.

Change the plld programming to read-modify-write to only affect the
relevant bits for plld and to preserve the other two divider values
present in the upper 16 bits, otherwise they will always get set to zero
when programming plld.

Fixes: 0aa2930ca192 ("clk: add support for TI K3 SoC PLL")
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoarm: mach-k3: Add note to auto-generated files
Dave Gerlach [Tue, 7 Sep 2021 22:16:56 +0000 (17:16 -0500)]
arm: mach-k3: Add note to auto-generated files

Add a note to the automatically generated clk-data and dev-data files
for j721e and j7200 to indicate that they are in fact auto-generated and
should not be hand edited.

Also adjust TI URL to use https instead of http and also add an empty
line before first header inclusion.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoarm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocks
Suman Anna [Tue, 7 Sep 2021 22:16:55 +0000 (17:16 -0500)]
arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocks

The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.

The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.

Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoarm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks
Suman Anna [Tue, 7 Sep 2021 22:16:54 +0000 (17:16 -0500)]
arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks

The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.

The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.

Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoarm: mach-k3: common: Add a release_resources_for_core_shutdown() stub
Suman Anna [Tue, 27 Jul 2021 23:24:40 +0000 (18:24 -0500)]
arm: mach-k3: common: Add a release_resources_for_core_shutdown() stub

Add a weak release_resources_for_core_shutdown() stub implementation
that can be overridden by actual implementation if a SoC supports that
function.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
3 years agofirmware: ti_sci: Include linux/err.h in ti_sci_protocol.h
Suman Anna [Tue, 27 Jul 2021 23:24:39 +0000 (18:24 -0500)]
firmware: ti_sci: Include linux/err.h in ti_sci_protocol.h

The common TI SCI header file uses some macros from err.h and these
get exercised when CONFIG_TI_SCI_PROTOCOL is not defined. Include
the linux/err.h header file in this header file directly rather
than relying on source files to include it to eliminate any
potential build errors.

While at this, reorder the existing header file include to the
beginning of the file.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
3 years agoMAINTAINERS: POWERPC MPC8XX: Update email address
Christophe Leroy [Wed, 13 May 2020 05:30:03 +0000 (05:30 +0000)]
MAINTAINERS: POWERPC MPC8XX: Update email address

Our email addresses have changed from @c-s.fr to @csgroup.eu

Update entry in MAINTAINERS

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
3 years agoMerge branch 'rpi-next' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
Tom Rini [Wed, 15 Sep 2021 19:22:46 +0000 (15:22 -0400)]
Merge branch 'rpi-next' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi

Ivan's patch fixes a kernel warning when booting RPi2, as the firmware
already
provides a frambebuffer node.

Marek's patch fixes random crashes on 32 bit RPi4 with newer firmware.

My SMBIOS patchesfixes an issue that show up with
e4f8e543f1 ("smbios: Drop the unused Kconfig options").
Basically the SMBIOS table broke and wasn't readable anymore.

3 years agorpi: Conditionally add simple-framebuffer node
Ivan T. Ivanov [Tue, 10 Aug 2021 14:31:14 +0000 (16:31 +0200)]
rpi: Conditionally add simple-framebuffer node

It appears that RPi firmware has already added framebuffer
node under /chosen, at least on RPi 2 versions. So check
for this and don't add duplicate node.

Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
3 years agoARM: bcm283x: change the virtual address of the XHCI PCI device base
Marek Szyprowski [Thu, 17 Jun 2021 09:22:03 +0000 (11:22 +0200)]
ARM: bcm283x: change the virtual address of the XHCI PCI device base

Move the XHCI PCI device base up in the virtual address space. This fixes
initialization failure observed with newer Raspberry Pi firmware, later
than 63b1922311 ("firmware: arm_loader: Update armstubs with those from
PR 117). It looks that chosing 0xff800000 as the XHCI PCI device base
conflicts with the updated ARM/VideoCore firmware.

This also requires to reduce the size of the mapped PCI device region
from 8MiB to 4MiB to fit into 32bit address space. This is still enough
for the XHCI PCI device.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
3 years agoconfigs: rpi: Enable SMBIOS sysinfo driver
Matthias Brugger [Mon, 12 Apr 2021 13:38:52 +0000 (15:38 +0200)]
configs: rpi: Enable SMBIOS sysinfo driver

Enable this driver to allow U-Boot to get SMBIOS table information from
a device tree node.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Acked-by: Fabian Vogt <fvogt@suse.com>
3 years agoarm: dts: bcm283x: Add minimal smbios information
Matthias Brugger [Mon, 12 Apr 2021 13:38:51 +0000 (15:38 +0200)]
arm: dts: bcm283x: Add minimal smbios information

At present SMBIOS tables are empty, which breaks some use-cases that
rely on that. Add some minimal information to fulfill this.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
3 years agoPrepare v2021.10-rc4
Tom Rini [Tue, 14 Sep 2021 22:58:10 +0000 (18:58 -0400)]
Prepare v2021.10-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoconfigs: Resync with savedefconfig
Tom Rini [Tue, 14 Sep 2021 22:48:05 +0000 (18:48 -0400)]
configs: Resync with savedefconfig

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoimage: Avoid erroneous double byte-swap in CRC value
Alexandru Gagniuc [Tue, 14 Sep 2021 20:53:33 +0000 (15:53 -0500)]
image: Avoid erroneous double byte-swap in CRC value

The hash algorithm selection was streamlined in commit 92055e138f28
("image: Drop if/elseif hash selection in calculate_hash()"). Said
commit kept the call to cpu_to_uimage() to convert the CRC to big
endian format.

This would have been correct when calling crc32_wd(). However, the
->hash_func_ws member of crc32 points to crc32_wd_buf(), which already
converts the CRC to big endian. On a little endian host, doing both
conversions results in a little-endian CRC. This is incorrect.

To remedy this, simply drop the call to cpu_to_uimage(), thus only
doing the byte-order conversion once.

Fixes: 92055e138f28 ("image: Drop if/elseif hash selection in
       calculate_hash()")
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agoMerge branch '2021-09-14-assorted-fixes'
Tom Rini [Tue, 14 Sep 2021 19:47:07 +0000 (15:47 -0400)]
Merge branch '2021-09-14-assorted-fixes'

- Assorted bugfixes

3 years agoimage: rsa: Move padding_algos to linker lists
Alexandru Gagniuc [Wed, 18 Aug 2021 22:49:02 +0000 (17:49 -0500)]
image: rsa: Move padding_algos to linker lists

We are not guaranteed to have the padding_pkcs_15_verify symbol since
commit 92c960bc1d ("lib: rsa: Remove #ifdefs from rsa.h"), and
commit 61416fe9df ("Kconfig: FIT_SIGNATURE should not select RSA_VERIFY")

The padding_algos only make sense with RSA verification, which can now
be disabled in lieu of ECDSA. In fact this will lead to build failures
because of the missing symbol mentioned earlier.

To resolve this, move the padding_algos to a linker list, with
declarations moved to rsa_verify.c. This is consistent with commit
6909edb4ce ("image: rsa: Move verification algorithm to a linker list")

One could argue that the added #ifdef USE_HOSTCC is ugly, and should
be hidden within the U_BOOT_PADDING_ALGO() macro. However, this would
be inconsistent with the "cryptos" list. This logic for was not
previously explored:

Without knowledge of the U_BOOT_PADDING_ALGO() macro, its use is
similar to something being declared. However, should #ifndef
USE_HOSTCC be part of the macro, it would not be obvious that it
behaves differently on host code and target code. Having the #ifndef
outside the macro makes this obvious.

Also, the #ifdef is not always necessary. For example ecda-verify
makes use of U_BOOT_CRYPTO_ALGO() without any accompanying #ifdefs.
The fundamental issue is a lack of separation of host and target code
in rsa_verify. Therefore, the declaration of a padding algo with the
external #ifdef is more readable and consistent.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agopinctrl: fix typo
Yuan Fang [Wed, 8 Sep 2021 11:06:48 +0000 (19:06 +0800)]
pinctrl: fix typo

fix typo in pinctrl Kconfig file to avoid git commit failure on
some commit hooks check.

Signed-off-by: Yuan Fang <fangyuanseu@gmail.com>
3 years agolib: fix typos in Kconfig
Oleksandr Suvorov [Wed, 1 Sep 2021 13:05:08 +0000 (16:05 +0300)]
lib: fix typos in Kconfig

There are trivial typos in the Kconfig file. Fixed them.
Also, fixed grammar in the descriptions with typos.

Fixes: d56b4b1974 ("configs: Migrate RBTREE, LZO, CMD_MTDPARTS, CMD_UBI and CMD_UBIFS")
Fixes: 7264f2928b ("spl: fit: Eanble GZIP support for image decompression")
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agolib/rsa: don't use NULL as key_id
Heinrich Schuchardt [Sat, 28 Aug 2021 10:13:05 +0000 (12:13 +0200)]
lib/rsa: don't use NULL as key_id

If keydir is not provided but name is we want to use name as key_id.

But with the current coding name is only used on its own if it is NULL
and keydir is provided which never occurs.

Fixes: 824ee745fbca ("lib/rsa: Use the 'keyfile' argument from mkimage")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoMerge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
Tom Rini [Tue, 14 Sep 2021 01:03:36 +0000 (21:03 -0400)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi

- a fix for U-Boot 2021.10 to bring back MMC boot on older boards.

3 years agosunxi: mmc: A20: Fix MMC optimisation
Andre Przywara [Fri, 3 Sep 2021 15:49:16 +0000 (16:49 +0100)]
sunxi: mmc: A20: Fix MMC optimisation

Some SoCs (as seen on A20) seem to misreport the MMC FIFO level if the
FIFO is completely full: the level size reads as zero, but the FIFO_FULL
bit is set. We won't do a single iteration of the read loop in this
case, so will be stuck forever.

Check for this situation and use a safe minimal FIFO size instead when
we hit this case.

This fixes MMC boot on A20 devices after the MMC FIFO optimisation
(9faae5457f52).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
3 years agoMerge branch '2021-09-09-finish-pre-DM_PCI-removal'
Tom Rini [Mon, 13 Sep 2021 22:23:24 +0000 (18:23 -0400)]
Merge branch '2021-09-09-finish-pre-DM_PCI-removal'

- Finish removing the non-DM_PCI legacy code.

3 years agopci: Drop DM_PCI
Simon Glass [Mon, 2 Aug 2021 00:54:44 +0000 (18:54 -0600)]
pci: Drop DM_PCI

This option has not effect now. Drop it, using PCI instead where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agopci: Drop PCI_INDIRECT_BRIDGE
Simon Glass [Mon, 2 Aug 2021 00:54:43 +0000 (18:54 -0600)]
pci: Drop PCI_INDIRECT_BRIDGE

This does not work with driver model so can be removed.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agonet: Drop DM_PCI check from designware driver
Simon Glass [Mon, 2 Aug 2021 00:54:34 +0000 (18:54 -0600)]
net: Drop DM_PCI check from designware driver

We don't need this check anymore since when PCI is enabled, driver model
is always used.

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agopci: acpi: Drop DM_PCI check from ahci
Simon Glass [Mon, 2 Aug 2021 00:54:25 +0000 (18:54 -0600)]
pci: acpi: Drop DM_PCI check from ahci

We don't need these checks anymore since when PCI is enabled, driver model
is always used.

Drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agopci: Drop DM_PCI check from fdtdec
Simon Glass [Mon, 2 Aug 2021 00:54:18 +0000 (18:54 -0600)]
pci: Drop DM_PCI check from fdtdec

We don't need this check anymore since when PCI is enabled, driver model
is always used.

Sadly this doesn't work with nds32 for some reason to do with the
toolchain. Add a work-around for that.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agopci: Drop old code from header file
Simon Glass [Mon, 2 Aug 2021 00:54:16 +0000 (18:54 -0600)]
pci: Drop old code from header file

We don't need this code anymore since when PCI is enabled, driver model is
always used.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agoppc: Remove UCP1020 board
Simon Glass [Mon, 2 Aug 2021 00:54:15 +0000 (18:54 -0600)]
ppc: Remove UCP1020 board

This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.

Note that we have to add CONFIG_SPIFLASH to scripts/config_whitelist.txt
because it's not really migrated at this point.

Acked-by: Michael Durrant <mdurrant@arcturusnetworks.com>
Acked-by: Oleksandr Zhadan <oleks@arcturusnetworks.com>
Acked-by: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Handle CONFIG_SPIFLASH differently and delete Kconfig file]
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoMerge tag 'mmc-2021-9-13' of https://source.denx.de/u-boot/custodians/u-boot-mmc
Tom Rini [Mon, 13 Sep 2021 12:31:41 +0000 (08:31 -0400)]
Merge tag 'mmc-2021-9-13' of https://source.denx.de/u-boot/custodians/u-boot-mmc

Support using mmc command for enumerating mmc card in a given mode
Fix device_remove in mmc
Fix switch issue with send_status disabled
Drop 1ms delay in fsl_esdhc command sending
Revert "mmc: sdhci: set to INT_DATA_END when there are data"

3 years agommc: fsl_esdhc: remove 1ms sleep in esdhc_send_cmd_common()
Michael Walle [Fri, 10 Sep 2021 09:20:52 +0000 (11:20 +0200)]
mmc: fsl_esdhc: remove 1ms sleep in esdhc_send_cmd_common()

Since the beginning of this driver which was initially for the MPC8379
and MPC8536 SoCs, there is this spurious 1ms delay. According to the
comment it should actually be only 8 clock cycles. Esp. during EFI block
transfers, this 1ms add up to a significant delay and slows down EFI
boot.

I couldn't find any mention in the MPC8536 that there should be a delay
of 8 clock cycles between commands. The SD card specification mentions that
the clock has to be left enabled for 8 cycles after a command or
response. But I don't see how this delay will help with this.

Go ahead and just remove it. If there will ever be any regression we can
introduce a compile time flag, but for now I'd like to keep it simple.

In the split off imx driver this delay was also removed in commit
9098682200e6 ("mmc: fsl_esdhc_imx: remove the 1ms delay before sending
command").

Signed-off-by: Michael Walle <michael@walle.cc>
3 years agoMerge tag 'efi-2021-10-rc4-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Tom Rini [Mon, 13 Sep 2021 00:33:21 +0000 (20:33 -0400)]
Merge tag 'efi-2021-10-rc4-2' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2021-10-rc4-2

Documentation:

* improve documentation of U-Boot for /config DT node
* integrate bloblist documentation

UEFI:

* correct usage of EFI_CALL()
* code tidy up

3 years agoMerge branch '2021-09-10-assorted-TI-updates'
Tom Rini [Sat, 11 Sep 2021 12:15:56 +0000 (08:15 -0400)]
Merge branch '2021-09-10-assorted-TI-updates'

- A number of TI platform bugfixes

3 years agoefi_loader: simplify efi_watchdog_timer_notify()
Heinrich Schuchardt [Thu, 9 Sep 2021 05:47:05 +0000 (07:47 +0200)]
efi_loader: simplify efi_watchdog_timer_notify()

We can call do_reset() directly without invoking the UEFI API.
This decreases the code size.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: eliminate EFI_CALL() in nvedit_efi.c
Heinrich Schuchardt [Thu, 9 Sep 2021 05:39:40 +0000 (07:39 +0200)]
efi_loader: eliminate EFI_CALL() in nvedit_efi.c

Reduce the code size by avoiding using the external UEFI API and using our
internal functions instead.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: Remove incorrect calls of EFI_CALL in TCG2
Ilias Apalodimas [Wed, 8 Sep 2021 21:30:49 +0000 (00:30 +0300)]
efi_loader: Remove incorrect calls of EFI_CALL in TCG2

There is two unneeded EFI_CALL references in tcg2_measure_pe_image().
The first one in efi_search_protocol() and the second on in the device path
calculation.  The second isn't even a function we should be calling, but a
pointer assignment, which happens to work with the existing macro.

While at it switch the malloc call to a calloc, remove the unnecessary cast
and get rid of an unneeded if statement before copying the device path

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: require CONFIG_BLK
Heinrich Schuchardt [Tue, 7 Sep 2021 06:56:47 +0000 (08:56 +0200)]
efi_loader: require CONFIG_BLK

The move to driver model should by now be completed. To be able to remove
pre-driver model code from our block IO code require CONFIG_BLK=y for UEFI
support.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: boot_service_capability_min should be capitalized
Masahisa Kojima [Mon, 6 Sep 2021 03:04:12 +0000 (12:04 +0900)]
efi_loader: boot_service_capability_min should be capitalized

boot_service_capability_min is constant, it should be capitalized.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agodoc: Complete the list of available runtime-config options
Simon Glass [Thu, 9 Sep 2021 20:10:32 +0000 (14:10 -0600)]
doc: Complete the list of available runtime-config options

The current list is missing a few items. Add them.

Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agodoc: Tidy up the bindings for the config/ node
Simon Glass [Thu, 9 Sep 2021 20:10:31 +0000 (14:10 -0600)]
doc: Tidy up the bindings for the config/ node

Sort these and add a type so it is clear how to set the value. Add a note
about usage to the top. Correct the 'no-keyboard' binding which is missing
a prefix.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agobloblist: Move to rST format
Simon Glass [Wed, 8 Sep 2021 13:33:52 +0000 (07:33 -0600)]
bloblist: Move to rST format

Move this documentation to the new format.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
3 years agodoc: board: toradex: fix file names
Oleksandr Suvorov [Thu, 9 Sep 2021 19:12:09 +0000 (22:12 +0300)]
doc: board: toradex: fix file names

Fix the documentation file names: s/apalix/apalis/.

Fixes: e98ea49a0e ("toradex: MAINTAINERS: entries for new reST docs")
Fixes: 3730106cf0 ("doc: board: apalis-imx8x: add documentation")
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoconfigs: j72*_evm: Define the buffer sizes for dfu
Aswath Govindraju [Thu, 26 Aug 2021 15:58:59 +0000 (21:28 +0530)]
configs: j72*_evm: Define the buffer sizes for dfu

On J721e R5 SPL, dfu buffer for loading sysfw.itb image gets allocated
before DRAM gets initialized. So, the buffer gets allocated in MCU L3
RAM. The current buffer size to be allocated is 256KB  and the available
total heap memory is 0x70000 (448KB). This leads to NOMEM errors during
allocation.

In other cases when constraints such as above are not present fix the size
of buffers to the sector size in OSPI for proper functioning.

Also, if CONFIG_SYS_DFU_DATA_BUF_SIZE is defined and
CONFIG_SYS_DFU_MAX_FILE_SIZE is not defined then the max file size for dfu
transfer is defined as CONFIG_SYS_DFU_DATA_BUF_SIZE.

Fix these by setting appropriate buffer sizes in their respective defconfig
files and defining the max file size as 8 MB which is the default dfu
buffer size.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
3 years agoenvironment: ti: k3_dfu: Increase the size allocated for bootloader images in dfu_alt...
Aswath Govindraju [Thu, 26 Aug 2021 15:58:58 +0000 (21:28 +0530)]
environment: ti: k3_dfu: Increase the size allocated for bootloader images in dfu_alt_info_ram

The size of u-boot.img is above 1MB and that of tispl.bin is close to 1MB,
in case of j721e. Therefore, increase the sizes allocated for tispl.bin and
u-boot.img to 2 MB and 4 MB respectively, in dfu_alt_info_ram environment
variable.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
3 years agoarm: dts: k3-j721e-r5-*.dts: Fix clock-names property in the usb0 instance
Aswath Govindraju [Thu, 26 Aug 2021 15:58:57 +0000 (21:28 +0530)]
arm: dts: k3-j721e-r5-*.dts: Fix clock-names property in the usb0 instance

In the cdns3 usb driver, the clock name looked for is ref. Therefore, fix
the clock-names property in usb0 instance for proper initialization of
cdns3 usb gadget driver.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>