Peng Fan [Wed, 31 Dec 2014 03:01:40 +0000 (11:01 +0800)]
imx:mx6sxsabresd add qspi support
Configure the pad setting and enable qspi clock to support qspi
flashes access.
Add QSPI related macro in configuration header file.
Note:
mx6sxsabresd Revb board, 32M flash is used, but in header file,
CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M.
The LUT initialization qspi_set_lut function uses 32BIT addr,
however CONFIG_SPI_FLASH_BAR and 24BIT addr should be used to
access bigger than 16MB size flash, and BRRD/BRWR should also
be supported. Future patches will fix this.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Peng Fan [Wed, 31 Dec 2014 03:01:39 +0000 (11:01 +0800)]
imx:qspi add 4K erase support
Add 4k erase command support for qspi driver. reuse the 64k erase function,
but change the function name from qspi_op_se to qspi_op_erase, since it
supports 64k and 4k erase.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Peng Fan [Wed, 31 Dec 2014 03:01:37 +0000 (11:01 +0800)]
QuadSPI: use correct amba_base
According cs, use different amba_base to choose the corresponding
flash devices. If not, `sf probe 1:0` and `sf probe 1:1` will
choose the same flash device, but not different flash devices.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Marek Vasut [Tue, 16 Dec 2014 13:09:20 +0000 (14:09 +0100)]
arm: mx6: novena: Minor config file fix
Sequence like the following is completely useless and results from
an errorneous ordering of the statements during development. Zap it.
#ifdef FOO
#define FOO
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
Marek Vasut [Tue, 16 Dec 2014 13:09:18 +0000 (14:09 +0100)]
arm: mx6: novena: Define CONFIG_SYS_MALLOC_F_LEN
This board uses setup_i2c() in SPL. The setup_i2c() function internally
calls gpio_request(), which in turn internally calls strdup(). The strdup()
requires a running mallocator, so this patch makes the mallocator available.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
This board uses setup_i2c() in SPL. The setup_i2c() function internally
calls gpio_request(), which in turn internally calls strdup(). The strdup()
requires a running mallocator, so this patch makes the mallocator available.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
Marek Vasut [Tue, 16 Dec 2014 13:09:16 +0000 (14:09 +0100)]
imx: i2c: Zap unnecessary malloc() calls
The malloc() calls are unnecessary, just allocate the stuff on stack.
While at it, reorder the code a little, so that only one variable is
used for the text, use snprintf() instead of sprintf() and use %01d
as a formatting string to avoid any possible overflows.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Iain Paton [Sun, 14 Dec 2014 14:51:46 +0000 (14:51 +0000)]
embestmx6boards: convert to use config_distro_bootcmd.h
Since the Riot & Mars boards are dev boards it's likely people will want to
run standard distros on them. So replace the current boot scripts with the
standard one from config_distro_bootcmd.h
Signed-off-by: Iain Paton <ipaton0@gmail.com> Tested-by: Nikolay Dimitrov <picmaster@mail.bg>
Masahiro Yamada [Fri, 19 Dec 2014 11:20:53 +0000 (20:20 +0900)]
ARM: UniPhier: add dump command of DDR PHY parameters
This commit adds a dump command of DDR PHY parameters of UniPhier
SoC family. It might not be used very often for the regular operation
but it would be useful when something goes wrong with DDR memories.
Sjoerd Simons [Mon, 29 Dec 2014 21:17:10 +0000 (22:17 +0100)]
Exynos: Move down common USB configuration
USB is a pretty common feature on exynos 5 board, so it seems sensible
to configure it directly from exynos5-common. As a side-effect this
makes USB available from u-boot on exynos 5420 based boards.
While there enable support for common USB ethernet cards to make it more
likely the default config allows booting for network and enable XHCI on
SMDK5420 which has it defined in the dts but not in its config.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Nikolay Dimitrov [Fri, 12 Dec 2014 18:01:23 +0000 (20:01 +0200)]
Fix hash verification
Fix issue in parse_verify_sum() which swaps handling of env-var and *address.
Move hash_command() argc check earlier.
Cosmetic change on do_hash() variable declaration.
Improved help message for "hash" command.
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Reviewed-by: Simon Glass <sjg@chromium.org>
Alexey Brodkin [Sat, 27 Dec 2014 22:35:57 +0000 (01:35 +0300)]
initcall: add explicit hint if initcall was relocated
Commit "initcall: Improve debugging support" makes sense and indeed
simplifies process of matching initcalls executed with static
disassembly.
Until you are debugging relocation functionality.
Existign output may make you think that at some point execution somehow
returned back to non-relocated area. And there're many reasons/problems
that may provoke this behavior.
Note "unexpected" jump from 0x8f... area to 0x81... area.
Without explanation this raises many questions: execution jumped in
relocated area right as expected and then for some reason returned back?
But I hope comment in brackets will save some time for those curious
developers who are careful enough to catch "unexpected jump to pre-reloc
area" or those unlucky ones who'll have to deal with relocation
debugging.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com>
Masahiro Yamada [Thu, 25 Dec 2014 02:09:44 +0000 (11:09 +0900)]
scripts: fix binutils-version.sh
The current binutils-version.sh expects the version string at the end
of the first line. It turned out to not work with Linaro toolchain:
It has "Linaro 2014.09" at the back.
To fix this issue, let's parse the word right after the close
parenthesis.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reported-by: York Sun <yorksun@freescale.com> Acked-by: Dirk Behme <dirk.behme@gmail.com>
Stephen Warren [Wed, 24 Dec 2014 03:01:44 +0000 (20:01 -0700)]
ARM: rpi: consolidate board rev error checking
Create a fake model table entry with default values, so we can error
check the board rev value once when querying it from the firmware, rather
than error-checking for invalid board rev values every time the model
table is used.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sat, 6 Dec 2014 03:56:46 +0000 (20:56 -0700)]
ARM: rpi: only set usbethaddr on relevant systems
Model A and CM RPis don't have an on-board USB Ethernet device. Hence,
there's no point setting $usbethaddr based on the device fuses. Use the
model detection code to gate this. Note that the fuses are actually
programmed even on those devices though.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Linus Walleij [Mon, 15 Dec 2014 10:06:05 +0000 (11:06 +0100)]
arm: semihosting: get rid of forward declarations
By rearranging the functions in the semihosting code we can
avoid forward-declaration of the internal static functions.
This puts the stuff in a logical order: read/open/close/len
and then higher-order functions follow at the end.
Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Mon, 15 Dec 2014 10:05:56 +0000 (11:05 +0100)]
arm: semihosting: fix up compile bugs
There is currently a regression when using newer ARM64 compilers
for semihosting: the way long types are inferred from context
is no longer the same.
The semihosting runtime uses long and size_t, so use this
explicitly in the semihosting code and interface, and voila:
the code now works again.
Tested with aarch64-linux-gnu-gcc: Linaro GCC 4.9-2014.09.
Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Suggested-by: Mark Hambleton <mark.hambleton@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Mon, 15 Dec 2014 10:05:43 +0000 (11:05 +0100)]
arm: semihosting: staticize internal functions
The semihosting code exposes internal file handle handling
functions to read(), open(), close() and get the length of
a certain file handle.
However the code using it is only interested in either
reading and entire named file into memory or getting the
file length of a file referred by name. No file handles
are used.
Thus make the file handle code internal to this file by
removing these functions from the semihosting header file
and staticize them.
This gives us some freedom to rearrange the semihosting
code without affecting the external interface.
Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sjoerd Simons [Fri, 5 Dec 2014 20:46:41 +0000 (21:46 +0100)]
ARM: exynos5420: Leave VBUS GPIO configuration up to common code
Since commit 4a271cb1b4ffdf330 (exynos: usb: Switch USB VBUS GPIOs to be
device tree configured) it's not needed for the board specific files to
turn on the VBUS GPIO by hand as that gets done based on device tree. So
drop the redundant code from the SMDK5420 board file.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sjoerd Simons [Fri, 5 Dec 2014 20:26:10 +0000 (21:26 +0100)]
odroid-XU3: Add entry for DTS EHCI GPIO
Add samsung,vbus-gpio information for the XU3. This allows the usage of
the EHCI controller on the XU3, which is connected to the SMSC LAN9514
chip (usb hub + network).
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sjoerd Simons [Fri, 5 Dec 2014 17:12:22 +0000 (18:12 +0100)]
exynos5420: fix compilation without parade video
Not all exynos 5420 based devices with an LCD also have a parade LVDS
bridge. So make sure compilation doesn't break if CONFIG_LCD is enabled
and CONFIG_VIDEO_PARADE is not.
As a side-effect move the parade functions from the exynos system header
file to its own file.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Hyungwon Hwang [Fri, 12 Dec 2014 05:45:46 +0000 (14:45 +0900)]
Odroid-XU3: Add documentation for Odroid-XU3
This patch adds documentation for Odroid-XU3. This documentation is
based on that of Odroid (doc/README-odroid) made by Przemyslaw Marczak.
The documentation includes basic information about boot media layout,
environment, partition layout, and the instruction to burn the u-boot
image to boot media.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Hyungwon Hwang [Fri, 12 Dec 2014 05:45:44 +0000 (14:45 +0900)]
config: exynos5420: move non common configs to specific board files
The media for boot and environment is a board-specific feature, not a
processor-specific. This is same to console port number and some
other addresses. This patch moves the that kinds of configs to each
board-specific files from the common config file for Exynos5420.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Stefan Roese [Fri, 19 Dec 2014 12:49:10 +0000 (13:49 +0100)]
arm: socfpga: Change watchdog timeout
The current current watchdog timeout of 12 seconds is a bit small for
booting into Linux, especially when using a NFS based rootfs. So lets
change this timeout to a more defensive value of 30 seconds.
Also we now call the hw_watchdog_init() function so that we override
the value already configured from the Preloader.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
Jan Luebbe [Sun, 14 Dec 2014 15:34:49 +0000 (16:34 +0100)]
arm: mxs: olinuxino: move DRAM config tuning to SPL
The weak mxs_adjust_memory_params function is called from spl_mem_init.c,
so it must be linked into the SPL to have an effect. Move it from
mx23_olinuxino.c to spl_boot.c.
This change was verified by reading back the register values.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Sun, 23 Nov 2014 03:52:20 +0000 (11:52 +0800)]
imx:mx6 fix return value of mxc_get_clock
mxc_get_clock's return type is unsigned int. 'return -1' is same with
'return 0xffffffff', so 0 should be used as the return value when
unsupported mxc_clock type is passed to mxc_get_clock.
Also include an err message when unsupported mxc_clock type is passed
to mxc_get_clock.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Simon Glass [Wed, 17 Dec 2014 03:21:02 +0000 (20:21 -0700)]
x86: Add a script to process Intel microcode files
Intel delivers microcode updates in a microcode.dat file which must be
split up into individual files for each CPU. Add a tool which performs
this task. It can list available microcode updates for each model and
produce a new microcode update in U-Boot's .dtsi format.
Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Wed, 17 Dec 2014 07:50:49 +0000 (15:50 +0800)]
x86: Clean up the FSP support codes
This is the follow-on patch to clean up the FSP support codes:
- Remove the _t suffix on the structures defines
- Use __packed for structure defines
- Use U-Boot's assert()
- Use standard bool true/false
- Remove read_unaligned64()
- Use memcmp() in the compare_guid()
- Remove the cast in the memset() call
- Replace some magic numbers with macros
- Use panic() when no valid FSP image header is found
- Change some FSP utility routines to use an fsp_ prefix
- Add comment blocks for asm_continuation and fsp_init_done
- Remove some casts in find_fsp_header()
- Change HOB access macros to static inline routines
- Add comments to mention find_fsp_header() may be called in a
stackless environment
- Add comments to mention init(¶ms) in fsp_init() cannot
be removed
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Dec 2014 07:50:48 +0000 (15:50 +0800)]
x86: Add a README.x86 for U-Boot on x86 support
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
(Use 'Link' as the name for the Chromebook Pixel consistently)
Bin Meng [Wed, 17 Dec 2014 07:50:46 +0000 (15:50 +0800)]
x86: crownbay: Add SDHCI support
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Dec 2014 07:50:45 +0000 (15:50 +0800)]
x86: crownbay: Enable Intel E1000 NIC support
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Dec 2014 07:50:44 +0000 (15:50 +0800)]
x86: crownbay: Add SPI flash support
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Dec 2014 07:50:38 +0000 (15:50 +0800)]
x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.
Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 17 Dec 2014 07:50:37 +0000 (15:50 +0800)]
x86: Convert microcode format to device-tree-only
To avoid having two microcode formats, adjust the build system to support
obtaining the microcode from the device tree, even in the case where it
must be made available before the device tree can be accessed.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 16 Dec 2014 05:02:41 +0000 (22:02 -0700)]
x86: Correct problems in the microcode loading
There are several problems in the code. The device tree decode is incorrect
in ways that are masked due to a matching bug. Both are fixed. Also
microcode_read_rev() should be inline and called before the microcode is
written.
Note: microcode writing does not work correctly on ivybridge for me. Further
work is needed to resolve this. But this patch tidies up the existing code
so that will be easier.
Simon Glass [Tue, 16 Dec 2014 05:02:38 +0000 (22:02 -0700)]
x86: ifdtool: Add support for early microcode access
Some Intel CPUs use an 'FSP' binary blob which provides an inflexible
means of starting up the CPU. One result is that microcode updates can only
be done before RAM is available and therefore parsing of the device tree
is impracticle.
Worse, the addess of the microcode update must be stored in ROM since a
pointer to its start address and size is passed to the 'FSP' blob. It is
not possible to perform any calculations to obtain the address and size.
To work around this, ifdtool is enhanced to work out the address and size of
the first microcode update it finds in the supplied device tree. It then
writes these into the correct place in the ROM. U-Boot can then start up
the FSP correctly.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Thierry Reding [Wed, 10 Dec 2014 05:25:26 +0000 (22:25 -0700)]
net: rtl8169: Use non-cached memory if available
To work around potential issues with explicit cache maintenance of the
RX and TX descriptor rings, allocate them from a pool of uncached memory
if the architecture supports it.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Wed, 10 Dec 2014 05:25:25 +0000 (22:25 -0700)]
net: rtl8169: Properly align buffers
RX and TX descriptor rings should be aligned to 256 byte boundaries. Use
the DEFINE_ALIGN_BUFFER() macro to define the buffers so that they don't
have to be manually aligned later on. Also make sure that the buffers do
align to cache-line boundaries in case the cache-line is higher than the
256 byte alignment requirements of the NIC.
Also add a warning if the cache-line size is larger than the descriptor
size, because the driver may discard changes to descriptors made by the
hardware when requeuing RX buffers.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Wed, 10 Dec 2014 05:25:23 +0000 (22:25 -0700)]
ARM: tegra: Enable non-cached memory
Some boards, most notably those with a PCIe ethernet NIC, require this
to avoid cache coherency problems. Since the option adds very little
code and overhead enable it across all Tegra generations. Other drivers
may also start supporting this functionality at some point, so enabling
it now will automatically reap the benefits later on.
Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Wed, 10 Dec 2014 05:25:22 +0000 (22:25 -0700)]
ARM: Implement non-cached memory support
Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).
The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting.
Boards can set this to the size to be used for the non-cached area. The
area will typically be right below the malloc() area, but architectures
should take care of aligning the beginning and end of the area to honor
any mapping restrictions. Architectures must also ensure that mappings
established for this area do not overlap with the malloc() area (which
should remain cached for improved performance).
While the API is currently only implemented for ARM v7, it should be
generic enough to allow other architectures to implement it as well.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Wed, 10 Dec 2014 05:25:21 +0000 (22:25 -0700)]
ARM: tegra: Enable PCIe on Jetson TK1
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes
the second root port to a miniPCIe slot. Enable the PCIe controller and
the network driver to allow the device to boot over the network.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Wed, 10 Dec 2014 05:25:19 +0000 (22:25 -0700)]
ARM: tegra: Add GIC for Tegra124
Add a device tree node for the GIC v2 found on the Cortex-A15 CPU
complex of Tegra124. U-Boot doesn't use this but subsequent patches will
add device tree nodes that reference it by phandle.
Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Wed, 10 Dec 2014 05:25:18 +0000 (22:25 -0700)]
ARM: tegra: Enable PCIe on Beaver
The Beaver has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network device driver so that the device can
boot over the network.
In addition the board has a mini-PCIe expansion slot.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
projects / u-boot.git / log