Stefan Bosch [Fri, 10 Jul 2020 17:07:31 +0000 (19:07 +0200)]
pwm: add driver for nexell
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- Since drivers/pwm/pwm-nexell.c is an adapted version of
s5p-common/pwm.c an appropriately changed version of s5p-common/pwm.c
is used instead. Therefore arch/arm/mach-s5pc1xx/include/mach/pwm.h
copied to arch/arm/mach-nexell/include/mach and s5p-common/Makefile
changed appropriately.
- '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where
possible (and similar).
Stefan Bosch [Fri, 10 Jul 2020 17:07:30 +0000 (19:07 +0200)]
pinctrl: add nexell driver
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- livetree API (dev_read_...) is used instead of fdt one (fdt...).
- doc/device-tree-bindings/pinctrl/nexell,s5pxx18-pinctrl.txt added.
Stefan Bosch [Fri, 10 Jul 2020 17:07:29 +0000 (19:07 +0200)]
mmc: add nexell driver
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- driver changed to DM.
- pinctrl-driver/dt is used now instead of configuring the mmc I/O-pins
in the mmc-driver.
- nexell_dwmmc_ofdata_to_platdata() reworked, i.e. valid default values
are used now (where possible) and the appropriate if-blocks have
been removed.
- new dt-property "mmcboost" is used now instead of "CONFIG_BOOST_MMC"
which was not defined anywhere.
Stefan Bosch [Fri, 10 Jul 2020 17:07:28 +0000 (19:07 +0200)]
i2c: add nexell driver
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- i2c/nx_i2c.c: Some adaptions mainly because of changes in
"struct udevice".
- several Bugfixes in nx_i2c.c.
- the driver has been for s5p6818 only. Code extended appropriately
in order s5p4418 is also working.
- "probe_chip" added.
- pinctrl-driver/dt is used instead of configuring the i2c I/O-pins
in the i2c-driver.
- '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where
possible (and similar).
- livetree API (dev_read_...) is used instead of fdt one (fdt...).
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- SPL not supported yet --> no spl-directory in arch/arm/mach-nexell.
Appropriate line in Makefile removed.
- clock.c: 'section(".data")' added to declaration of clk_periphs[] and
core_hz.
- Kconfig: Changes to have a structure like in mach-bcm283x/Kconfig,
e.g. "config ..." entries moved from other Kconfig.
- timer.c: 'section(".data")' added to declaration of timestamp and
lastdec.
- arch/arm/mach-nexell/serial.c removed because this is for the UARTs
of the S5P6818 SoC which is not supported yet. S5P4418 UARTs are
different, here the (existing) PL011-code is used.
- '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where
possible (and similar).
arm: qemu: override flash accessors to use virtualizable instructions
Some instructions in the ARM ISA have multiple output registers, such
as ldrd/ldp (load pair), where two registers are loaded from memory,
but also ldr with indexing, where the memory base register is incremented
as well when the value is loaded to the destination register.
MMIO emulation under KVM is based on using the architecturally defined
syndrome information that is provided when an exception is taken to the
hypervisor. This syndrome information describes whether the instruction
that triggered the exception is a load or a store, what the faulting
address was, and which register was the destination register.
This syndrome information can only describe one destination register, and
when the trapping instruction is one with multiple outputs, KVM throws an
error like
kvm [615929]: Data abort outside memslots with no valid syndrome info
on the host and kills the QEMU process with the following error:
This means that, in order to run U-Boot in QEMU under KVM, we need to
avoid such instructions when accessing emulated devices. For the flash
in particular, which is a hybrid between a ROM (backed by a read-only
KVM memslot) when in array mode, and an emulated MMIO device (when in
write mode), we need to take care to only use instructions that KVM can
deal with when they trap.
So override the flash read accessors that are used when running on QEMU
under KVM. Note that the the 64-bit wide read and write accessors have
been omitted: they are never used when running under QEMU given that it
does not emulate CFI flash that supports it.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
arm: qemu: disable the EFI workaround for older GRUB
The QEMU/mach-virt targeted port of u-boot currently only runs on
QEMU under TCG emulation, which does not model the caches at all,
and so no users can exist that are relying on the GRUB hack for
EFI boot.
We will shortly enable support for running under KVM, but the GRUB
hack (which disables all caches without doing cache cleaning by VA
during ExitBootServices()) is likely to cause more problems than it
solves, given that KVM hosts require correct maintenance if they
incorporate non-architected system caches.
So let's disable the GRUB hack by default on the QEMU/mach-virt
port.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add an override for enable_caches to enable the I and D caches, along
with the cached 1:1 mapping of all of DRAM. This is needed for running
U-Boot under virtualization with QEMU/kvm.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
QEMU's mach-virt machine only supports selecting CPU models that
implement the virtualization extensions, and are therefore guaranteed
to support LPAE as well.
Initially, QEMU would not allow emulating these CPUs running in HYP
mode (or EL2, for AArch64), but today, it also contains a complete
implementation of the virtualization extensions themselves.
This means we could be running U-Boot in HYP mode, in which case the
LPAE long descriptor page table format is the only format that is
supported. If we are not running in HYP mode, we can use either.
So let's enable CONFIG_ARMV7_LPAE for qemu_arm_defconfig so that we
get the best support for running with the MMU and caches enabled at
any privilege level.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK/_WRITETHROUGH
The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently
defined as no-allocate for both reads and writes, which deviates from the
non-LPAE definition, and mostly defeats the purpose of enabling the caches
in the first place.
So align LPAE with !LPAE, and enable allocate-on-read for both. And while
at it, add some clarification about the meaning of the chosen values.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Robert Marko [Mon, 6 Jul 2020 08:37:55 +0000 (10:37 +0200)]
msm_serial: Read bit rate register value from DT
IPQ40xx and currently supported Snapdragon boards don't use the same one
so enable reading it from DT, if no DT property is found default value
is the same as the previous define.
Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Robert Marko [Mon, 6 Jul 2020 08:37:54 +0000 (10:37 +0200)]
arm: Add support for Qualcomm IPQ40xx family
This introduces initial support for the popular Qualcomm
IPQ40x8 and IPQ40x9 WiSoC series.
IPQ40xx series have 4x Cortex A7 ARM-v7A cores.
Supported are: IPQ4018, IPQ4019, IPQ4028 and IPQ4029.
IPQ40x8 and IPQ40x9 use the same cores, but differ in
addressable RAM size (1GB for IPQ40x9 and 256MB for IPQ40x8)
and supported peripherals (IPQ40x8 lacks RGMII, LCD controller
and EMMC/SDHCI controllers).
IQP4028/IPQ4029 models differ from IPQ4018/IPQ4019 only
by their rated temperatures rates with IPQ402X models being
rated for wider temperature ranges.
Initially this supports:
* Simple clock driver (Only for UART1 now, will be extended)
* Pinctrl driver (Supports UARTX and GPIO now, will be extended)
* GPIOs already supported by msm_gpio driver with updates
* UARTs already supported by serial_msm driver with updates
Further peripherals will come in later patches.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
David Woodhouse [Fri, 19 Jun 2020 11:40:20 +0000 (12:40 +0100)]
pinctrl: mediatek: add PUPD/R0/R1 support for MT7623
The pins for the MMC controller weren't being set up correctly because the
pinctrl driver only sets the GPIO pullup/pulldown config and doesn't
handle the special cases with PUPD/R0/R1 control.
Signed-off-by: David Woodhouse <dwmw2@infradead.org> Tested-by: Frank Wunderlich <frank-w@public-files.de>
MarkLee [Fri, 19 Jun 2020 11:17:16 +0000 (19:17 +0800)]
eth: mtk-eth: enable mt7629 sgmii mode support in mediatek eth driver
The sgmii mode init flow is almost the same for all mediatek SoC, the
only difference is the register offset(SGMSYS_GEN2_SPEED) is 0x2028
in the old chip(mt7622) but changed to 0x128 for the newer chip(mt7629
and the following chips).
Bin Meng [Tue, 28 Jul 2020 09:06:44 +0000 (02:06 -0700)]
azure: Switch to use the MSYS2 official installer as the CI base
Recent CI failures were seen [1] when building MSYS2 Windows host
tools. The error messages are something like:
downloading mingw32.db...
downloading mingw32.db.sig...
error: mingw32: key "4A6129F4E4B84AE46ED7F635628F528CF3053E04" is unknown
error: mingw32: signature from "David Macek <david.macek.0@gmail.com>" is unknown trust
error: failed to update mingw32 (invalid or corrupted database (PGP signature))
Per the MSYS2 official news [2], this was caused by a packager
switch and several solutions were suggested, e.g.: a new package
of msys2-keyring and a new msys2 installer that includes them are
released. However right now we have been using the MSYS2 github
CI base repo [3] for the MSYS2 build in U-Boot, but per the project
information on the github webpage, it says: "This repository is
unused/deprecated and will be remove after 2021-01-01". Since it is
unmaintained it's unlikely the new PGP keys will be included in the
git repo, and the only choice is to switch to use the MSYS2 official
installer as the CI base instead.
- Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a
- lx2-watchdog support
- layerscape: pci-endpoint support, spin table relocation fixes and
cleanups
- fsl-crypto: RNG support and bug fixes
Tom Rini [Mon, 27 Jul 2020 15:11:27 +0000 (11:11 -0400)]
travis: Install pyelftools via pip
With the migration to python3 for all of our tests, we need to install
pyelftools via pip now rather than the system tools as they will
otherwise not be present in our virtualenv.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
Changes in v2: Switch to pip
Neil Armstrong [Tue, 21 Jul 2020 11:41:14 +0000 (13:41 +0200)]
serial: meson: handle RX errors
This checks and handles RX errors on the Amlogic UART controller
after experiencing errors on the Khadas VIM3 & VIM3L when UART AO A
lines are not connected.
When the RX line is not connected, the first byte is erroneous and breaks
the U-Boot autoboot, breaking automatic boot.
This checks and drops any erroneous RX byte on pending and getc callbacks
to avoid returning true to pending when an error byte is in the FIFO.
Fixes: bfcef28ae4 ("arm: add initial support for Amlogic Meson and ODROID-C2") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Guillaume La Roque <glaroque@baylibre.com>
Tom Rini [Mon, 27 Jul 2020 13:25:53 +0000 (09:25 -0400)]
Merge branch '2020-07-27-misc-env-improvements'
- Assorted environment fixes.
- Enhance environment in MMC and controlled via OF_CONTROL
- Allow for environment in FAT to use the same device we boot from
rather than be hard-coded.
According to Server Base System Architecture (SBSA) specification,
the SBSA Generic Watchdog has two stage timeouts: the first signal
(WS0) is for alerting the system by interrupt, the second one (WS1) is a
real hardware reset.
More details about the hardware specification of this device:
ARM DEN0029B - Server Base System Architecture (SBSA)
This driver can operate ARM SBSA Generic Watchdog as a single stage
In the single stage mode, when the timeout is reached, your system
will be reset by WS1. The first signal (WS0) is ignored.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Xiaowei Bao [Thu, 9 Jul 2020 15:31:37 +0000 (23:31 +0800)]
pci_ep: layerscape: Add the workaround for errata A-009460
The VF_BARn_REG register's Prefetchable and Type bit fields
are overwritten by a write to VF's BAR Mask register.
workaround: Before writing to the VF_BARn_MASK_REG register,
write 0b to the PCIE_MISC_CONTROL_1_OFF register.
lx2160a rev2 requires 4KB space for type0 and 4KB
space for type1 iATU window. Increase configuration
size to 8KB to have sufficient space for type0
and type1 window.
Biwen Li [Thu, 2 Jul 2020 03:13:04 +0000 (11:13 +0800)]
freescale: ls1043aqds: drop ifdef CONFIG_SYS_I2C
- Drop ifdef CONFIG_SYS_I2C to initialize
baudrate of i2c
- Drop warning of i2c_early_init_f as follows,
warning: implicit declaration of function 'i2c_early_init_f'; did you
mean 'arch_early_init_r'? [-Wimplicit-function-declaration]
Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Biwen Li [Thu, 2 Jul 2020 03:13:02 +0000 (11:13 +0800)]
freescale: ls1046aqds: drop ifdef CONFIG_SYS_I2C
- Drop ifdef CONFIG_SYS_I2C to initialize
baudrate of i2c
- Drop warning of i2c_early_init_f as follows,
warning: implicit declaration of function 'i2c_early_init_f'; did you
mean 'arch_early_init_r'? [-Wimplicit-function-declaration]
Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Kuldeep Singh [Thu, 25 Jun 2020 07:26:22 +0000 (12:56 +0530)]
configs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN value
Previous attempt to increase CONFIG_SYS_MALLOC_LEN was done in commit c084a8edf4e2 ("configs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN size")
which increased malloc memory to ~1M.
PFE firmware alone requires 3M of dynamic memory allocation and
therefore, increase the config value to a larger value i.e 5M. This size
should be enough as of now to accommodate further memory requirements.
Yangbo Lu [Wed, 17 Jun 2020 10:08:58 +0000 (18:08 +0800)]
Move eSDHC adapter card identification to board files
The eSDHC adapter card identification and multiplexing configuration
through FPGA had been implemented in both common mmc driver and
fsl_esdhc driver. However it is proper to move these code to board
files and do it during board initialization. The FPGA registers are
also board specific.
This patch is to move eSDHC adapter card identification and
multiplexing configuration from mmc driver to specific board files.
And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
[Rebased, Removed T1040QDS change as board does not exist] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
The correct setting for the RGMII ports on LS1012ARDB is to
enable delay on both Rx and Tx so the interface mode used should
be PHY_INTERFACE_MODE_RGMII_ID
The compiler emits a "stur x1, [x0, #12]". x1 is might just be 32 bit
aligned pointer. Remove the unused u64 element from the union to drop
the minimal alignment to 32 bit. Also remove the union, because it is
no more needed.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:36 +0000 (21:53 +0200)]
armv8: layerscape: rework spin table
There are two issues:
(1) The spin table doesn't convert the endianness of the jump address.
Although there is code for it, the result isn't used at all (x0).
(2) If something goes wrong, the function returns. But that doesn't
make sense at all.
Use the actual converted jump address as destination to fix. If
there is an error, jump to a trap loop. And rearrange the code exception
level switching code to make it smaller and clearer.
This reduces the size of the spin table code section from 696 bytes to
424 bytes. If CONFIG_ARMV8_SWITCH_TO_EL1 the code size reduced from 696
bytes to 632 bytes.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:35 +0000 (21:53 +0200)]
armv8: layerscape: relocate spin table if EFI_LOADER is enabled
On ARM64, a 64kb region is reserved for the runtime services code.
Unfortunately, this code overlaps with the spin table code, which also
needs to be reserved. Thus now that the code is relocatable, allocate a
new page from EFI, copy the spin table code into it, update any pointers
to the old region and the start the secondary CPUs.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:34 +0000 (21:53 +0200)]
armv8: layerscape: clean exported symbols in spintable.S
Add a new variable secondary_boot_code_start, which holds a pointer to
the start of the spin table code. This will help to relocate the code
section. While at it, move the size variable from the end to the
beginning so there is a common section for the variables. Remove any
other symbols.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:28 +0000 (21:53 +0200)]
armv8: layerscape: load function pointer using ADR
Don't use LDR to load a pointer to a function. This will generate a
literal which cannot be relocated. Use ADR which is PC-relative and
therefore can easily be relocated.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:27 +0000 (21:53 +0200)]
armv8: layerscape: move spin table into own module
Move it out of lowlevel.S into spintable.S. On layerscape, the secondary
CPUs are brought up in main u-boot. This will make it possible to only
compile the spin table code for the main u-boot and omit it in SPL.
This saves about 720 bytes in the SPL.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:26 +0000 (21:53 +0200)]
armv8: layerscape: properly use CPU_RELEASE_ADDR
The generic armv8 code already has support to bring up the secondary
cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to
the spin table code; instead just return early and let the common armv8
code handle the jump. This way we can actually use the CPU_RELEASE_ADDR
feature.
Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased, Removed kontron_sl28.h change as file does not exist] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
projects / u-boot.git / log