]> git.dujemihanovic.xyz Git - u-boot.git/log
u-boot.git
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-marvell
Tom Rini [Fri, 12 Mar 2021 13:00:39 +0000 (08:00 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- Some more updates/sync's to A38x DDR3 code (Marek & Pali)
- marvell/ddr/AXP: Some type fixes found in the LTO work (Marek)
- Espressobin: Enable more options (Pali)
- pci-aardvark: Implement workaround for the readback value of
  VEND_ID (Paili)

3 years agoarm: mvebu: a38x: Remove dead code ARMADA_39X
Pali Rohár [Fri, 5 Mar 2021 14:52:42 +0000 (15:52 +0100)]
arm: mvebu: a38x: Remove dead code ARMADA_39X

Config option ARMADA_39X is never set so remove all dead code hidden under
ifdef CONFIG_ARMADA_39X blocks.

Also remove useless checks for CONFIG_ARMADA_38X define as this macro is
always defined for a38x code path.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: a37xx: pci: Implement workaround for the readback value of VEND_ID
Pali Rohár [Wed, 3 Mar 2021 13:37:59 +0000 (14:37 +0100)]
arm: a37xx: pci: Implement workaround for the readback value of VEND_ID

Marvell Armada 3720 Functional Errata, Guidelines, and Restrictions
document describes in erratum 4.1 PCIe value of vendor ID (Ref #: 243):

    The readback value of VEND_ID (RD0070000h [15:0]) is 1B4Bh, while it
    should read 11ABh.

    The firmware can write the correct value, 11ABh, through VEND_ID
    (RD0076044h [15:0]).

Implement this workaround in U-Boot PCIe controller driver aardvark for
both PCI vendor id and PCI subsystem vendor id.

This change affects PCI vendor id of PCIe root bridge emulated by Linux
kernel. With this change Linux kernel reports correct vendor id 11AB.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: mvebu: Espressobin: Enable additional options
Pali Rohár [Wed, 3 Mar 2021 10:34:53 +0000 (11:34 +0100)]
arm: mvebu: Espressobin: Enable additional options

Enable support for NVMe disks which can be connected to mPCIe slot via M.2
reduction. Enable btrfs and squashfs filesystems which are used by more
Linux distributions. And enable fsuuid and setexpr commands which can be
useful in scripting.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoddr: marvell: axp: fix array types have different bounds warning
Marek Behún [Sat, 6 Mar 2021 23:00:34 +0000 (00:00 +0100)]
ddr: marvell: axp: fix array types have different bounds warning

The arrays `pbs_dq_mapping`, `div_ratio1to1` and `div_ratio2to1` have
different bounds declared in header files where these variables are also
defined from the ones declared in source files.

This causes the compiler to complain (when building with LTO):
  ddr3_sdram.c:24:12: warning: type of ‘pbs_dq_mapping’ does not match
                               original declaration
       [-Wlto-type-mismatch]
  ddr3_patterns_64bit.h:911:5: note: array types have different bounds
  ddr3_patterns_64bit.h:911:5: note: ‘pbs_dq_mapping’ was previously
                                     declared here

ddr3_dfs.c:45:11: warning: type of ‘div_ratio1to1’ does not match
                           original declaration [-Wlto-type-mismatch]
ddr3_axp_vars.h:167:4: note: array types have different bounds
ddr3_axp_vars.h:167:4: note: ‘div_ratio1to1’ was previously declared
                             here

ddr3_dfs.c:46:11: warning: type of ‘div_ratio2to1’ does not match
                           original declaration [-Wlto-type-mismatch]
ddr3_axp_vars.h:196:4: note: array types have different bounds
ddr3_axp_vars.h:196:4: note: ‘div_ratio2to1’ was previously declared
                             here

CI managed to trigger this as an error when compiling with LTO for AXP.

Fix this by using values from the header files, which seem to be the
correct ones.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
3 years agoddr: marvell: axp: align signature of mv_xor_mem_init() with a38x
Marek Behún [Thu, 4 Mar 2021 10:23:14 +0000 (11:23 +0100)]
ddr: marvell: axp: align signature of mv_xor_mem_init() with a38x

In arch/arm/mach-mvebu/dram.c we always include axp's xor.h for common
XOR definitions, regardless whether we compile for axp or a38x.

But the declaration of this function has a different signature in axp's
xor.h from the one used in a38x' implementation - one parameter is u64
instead of u32. This can result in wrong argument's being passed to that
function on a38x with no one the wiser.

I discovered this when building U-Boot for Turris Omnia with LTO. The
compiler complains about the different signatures being thrown into the
same linking process:

  axp/xor.h:67:5: warning: type of ‘mv_xor_mem_init’ does not match
                           original declaration [-Wlto-type-mismatch]
   67 | int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size,
      |     ^
  a38x/xor.c:165:5: note: type mismatch in parameter 3
  165 | int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long
      |     ^
  a38x/xor.c:165:5: note: type ‘long long unsigned int’ should match
                          type ‘u32’

Fix this by changing the type of the block_size argument in the axp's
implementation and header file to the one used in a38x (and upstream
mv-ddr-marvell).

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository
Pali Rohár [Tue, 2 Mar 2021 10:17:41 +0000 (11:17 +0100)]
ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository

This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git up to the
commit 7c351731d196 ("Merge pull request #29 from pali/sync-a38x-uboot").

This patch was created by following steps:

1. Replace all a38x files in U-Boot tree by files from upstream github
   Marvell mv-ddr-marvell repository.

2. Run following command to omit portions not relevant for a38x and ddr3:

    files=drivers/ddr/marvell/a38x/*
    sed 's/#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)/#ifdef TRUE/' -i $files
    unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 -UCONFIG_APN806 \
        -UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
        -UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
        -UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DTRUE $files

3. Manually omit SPDX-License-Identifier changes from this patch as
   upstream license in  upstream github repository contains long license
   texts and U-Boot is using just SPDX-License-Identifier.

After applying this patch, a38x ddr3 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.

The only change in this patch is removal of dead code and some fixes with
include files.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoddr: marvell: a38x: Add more space for additional info from SPD
Sujeet Baranwal [Fri, 26 Feb 2021 10:56:59 +0000 (11:56 +0100)]
ddr: marvell: a38x: Add more space for additional info from SPD

commit 258be123226f8f5cd516b7813fe201fb7d7416e9 upstream.

At this moment, only page 0 of SPD is being read but to support
smbios, we need to read page 1 also which has more info. In order
to do that, we need to allocate more space.

Signed-off-by: Sujeet Baranwal <sujeet.baranwal@cavium.com>
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Sujeet Kumar Baranwal <Sujeet.Baranwal@cavium.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <judge.packham@gmail.com>
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-usb
Tom Rini [Wed, 10 Mar 2021 13:56:52 +0000 (08:56 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-usb

3 years agousb: mtu3: flush cache for next GPD
Chunfeng Yun [Wed, 3 Mar 2021 08:07:05 +0000 (16:07 +0800)]
usb: mtu3: flush cache for next GPD

When flush cache of the current GPD and resume QMU, the controller
will try to access the next GPD after processing the current one,
if not flush the next GPD, the controller may get wrong GPD status.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-x86
Tom Rini [Tue, 9 Mar 2021 12:21:51 +0000 (07:21 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-x86

- Various minor fixes for x86

3 years agox86: Select advanced Intel code only if allowed
Simon Glass [Tue, 23 Feb 2021 10:35:42 +0000 (05:35 -0500)]
x86: Select advanced Intel code only if allowed

At present most of the Intel-specific code is built on all devices, even
those which don't have software support for the features provided there.

This means that any board can enable CONFIG_INTEL_ACPIGEN even if it does
not have the required features.

Add a new INTEL_SOC option to control this access. This must be selected
by SoCs that can support the required features.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed a typo in arch/x86/Kconfig]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
3 years agox86: Move INTEL_ACPIGEN to arch/x86
Simon Glass [Tue, 23 Feb 2021 10:35:41 +0000 (05:35 -0500)]
x86: Move INTEL_ACPIGEN to arch/x86

This option is better placed in the x86 code since it is not generic
enough to be in the core code. Move it.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed a typo in arch/x86/Kconfig]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
3 years agox86: Fix member check in intel_gnvs
Simon Glass [Tue, 23 Feb 2021 10:35:40 +0000 (05:35 -0500)]
x86: Fix member check in intel_gnvs

When CONFIG_CHROMEOS is not enabled this currently does not build. Fix it.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agox86: sizeof-array-div error in lpc_common_early_init
Heinrich Schuchardt [Sat, 20 Feb 2021 09:05:24 +0000 (10:05 +0100)]
x86: sizeof-array-div error in lpc_common_early_init

Building qemu-x86_64_defconfig with GCC 11.0 fails with:

arch/x86/cpu/intel_common/lpc.c:
In function ‘lpc_common_early_init’:
arch/x86/cpu/intel_common/lpc.c:56:40:
error: expression does not compute the number of elements in this array;
element type is ‘struct reg_info’, not ‘u32’ {aka ‘unsigned int’}
[-Werror=sizeof-array-div]
   56 |                         sizeof(values) / sizeof(u32));
      |                                        ^
arch/x86/cpu/intel_common/lpc.c:56:40: note: add parentheses around the
second ‘sizeof’ to silence this warning
arch/x86/cpu/intel_common/lpc.c:50:11: note: array ‘values’ declared here
   50 |         } values[4], *ptr;
      |           ^~~~~~

Add parentheses to silence warning.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agoMerge tag 'u-boot-amlogic-20210308' of https://gitlab.denx.de/u-boot/custodians/u...
Tom Rini [Mon, 8 Mar 2021 12:41:50 +0000 (07:41 -0500)]
Merge tag 'u-boot-amlogic-20210308' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- button: adc: fix treshold typo
- configs: meson64: add fdtoverlay_addr_r

3 years agoMerge branch 'v2021.04-rc4' of https://github.com/lftan/u-boot
Tom Rini [Mon, 8 Mar 2021 12:11:26 +0000 (07:11 -0500)]
Merge branch 'v2021.04-rc4' of https://github.com/lftan/u-boot

- Add VAB support

3 years agoconfigs: meson64: add fdtoverlay_addr_r
Neil Armstrong [Wed, 10 Feb 2021 14:22:13 +0000 (15:22 +0100)]
configs: meson64: add fdtoverlay_addr_r

In order to support loading FTD Overlays when booting with the pxe
command (or extlinux.conf), supported with [1], add the missing
fdtoverlay_addr_r used to load the overlay before applying it to
the FDT loaded at fdt_addr_r.

[1] https://patchwork.ozlabs.org/project/uboot/patch/20210120085453.2783678-1-narmstrong@baylibre.com/

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
3 years agobutton: adc: fix treshold typo
Neil Armstrong [Tue, 23 Feb 2021 15:07:51 +0000 (16:07 +0100)]
button: adc: fix treshold typo

Fix the treshold typo in code by threshold.

Fixes: c0165c85c3 ("button: add a simple Analog to Digital Converter device based button driver")
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
3 years agoMakefile: socfpga: Add target to generate hex output for combined spl and dtb
Dalon Westergreen [Mon, 1 Mar 2021 12:04:16 +0000 (20:04 +0800)]
Makefile: socfpga: Add target to generate hex output for combined spl and dtb

Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel
SOCFPGA SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex"
is hex formatted spl with and offset of CONFIG_SPL_TEXT_BASE. It
combines the spl image and dtb. "u-boot-spl-dtb.hex" is needed to
generate the final configuration bitstream for Intel SOCFPGA SOC64
devices.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
3 years agoconfigs: socfpga: Add defconfig for Agilex with VAB support
Siew Chin Lim [Mon, 1 Mar 2021 12:04:15 +0000 (20:04 +0800)]
configs: socfpga: Add defconfig for Agilex with VAB support

Booting Agilex with Vendor Authorized Boot.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
3 years agoconfigs: socfpga: soc64: Move CONFIG_BOOTCOMMAND to defconfig
Siew Chin Lim [Mon, 1 Mar 2021 12:04:14 +0000 (20:04 +0800)]
configs: socfpga: soc64: Move CONFIG_BOOTCOMMAND to defconfig

CONFIG_BOOTCOMMAND have been moved to Kconfig.boot. This patch
move the CONFIG_BOOTCOMMAND macro from socfpga_soc64_common.h to
*_defconfig file for both Stratix 10 and Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
3 years agoarm: socfpga: dts: soc64: Update filename in binman node of FIT image with VAB support
Siew Chin Lim [Mon, 1 Mar 2021 12:04:13 +0000 (20:04 +0800)]
arm: socfpga: dts: soc64: Update filename in binman node of FIT image with VAB support

FIT image of Vendor Authentication Coot (VAB) contains signed images.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
3 years agoarm: socfpga: cmd: Support 'vab' command
Siew Chin Lim [Mon, 1 Mar 2021 12:04:12 +0000 (20:04 +0800)]
arm: socfpga: cmd: Support 'vab' command

Support 'vab' command to perform vendor authentication.

Command format: vab addr len
Authorize 'len' bytes starting at 'addr' via vendor public key

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
3 years agoarm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
Siew Chin Lim [Mon, 1 Mar 2021 12:04:11 +0000 (20:04 +0800)]
arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)

Vendor Authorized Boot is a security feature for authenticating
the images such as U-Boot, ARM trusted Firmware, Linux kernel,
device tree blob and etc loaded from FIT. After those images are
loaded from FIT, the VAB certificate and signature block appended
at the end of each image are sent to Secure Device Manager (SDM)
for authentication. U-Boot will validate the SHA384 of the image
against the SHA384 hash stored in the VAB certificate before
sending the image to SDM for authentication.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
3 years agoarm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
Siew Chin Lim [Mon, 1 Mar 2021 12:04:10 +0000 (20:04 +0800)]
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64

Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
3 years agoMerge tag 'efi-2021-04-rc3-3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Tom Rini [Mon, 8 Mar 2021 00:43:00 +0000 (19:43 -0500)]
Merge tag 'efi-2021-04-rc3-3' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2021-04-rc3-3

New:

* Provide library functions for converting UTF-8 streams either to code
  page 437 or Unicode code points.

Bug fixes:

* Fix the capsule update unit tests.
* Use the terminal size of the video console if it is the primary output.

3 years agoefi_loader: correct uboot_bin_env.its file format
Heinrich Schuchardt [Tue, 2 Mar 2021 07:07:19 +0000 (08:07 +0100)]
efi_loader: correct uboot_bin_env.its file format

Up to now the EFI capsule Python tests were always skipped. The reason is
that mkimage fails with:

uboot_bin_env.its:13.21-23.5: Warning (unit_address_vs_reg):
/images/u-boot-bin@100000: node has a unit name, but no reg property
uboot_bin_env.its:24.21-34.5: Warning (unit_address_vs_reg):
/images/u-boot-env@150000: node has a unit name, but no reg property

If a unit in a device-tree has an address, a reg property must be provided.
But adding a reg property is not the solution here.

Since 2017 unit addresses are disallowed for FIT,
cf. common/image-fit.c:1624.

So remove the unit addresses in uboot_bin_env.its.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agolib/charset: UTF-8 stream conversion
Heinrich Schuchardt [Sat, 27 Feb 2021 13:08:38 +0000 (14:08 +0100)]
lib/charset: UTF-8 stream conversion

Provide functions to convert an UTF-8 stream to code page 437 or UTF-32.

Add unit tests.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agolib/charset: utf8_get() should return error
Heinrich Schuchardt [Sat, 27 Feb 2021 13:08:37 +0000 (14:08 +0100)]
lib/charset: utf8_get() should return error

utf8_get() should return an error if hitting an illegal UTF-8 sequence and
not silently convert the input to a question mark.

Correct utf_8() and the its unit test.

console_read_unicode() now will ignore illegal UTF-8 sequences.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: carve out utf_to_cp()
Heinrich Schuchardt [Sat, 27 Feb 2021 13:08:36 +0000 (14:08 +0100)]
efi_loader: carve out utf_to_cp()

Carve out a function to translate a Unicode code point to an 8bit codepage.

Provide a unit test for the new function.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: move codepage 437 table
Heinrich Schuchardt [Sat, 27 Feb 2021 13:08:35 +0000 (14:08 +0100)]
efi_loader: move codepage 437 table

Move the Unicode to codepage 437 table to charset.c

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: console size of vidconsole
Heinrich Schuchardt [Sun, 28 Feb 2021 17:17:28 +0000 (18:17 +0100)]
efi_loader: console size of vidconsole

If stdout is 'vidconsole', we correctly set the console size.
If stdout is 'vidconsole,serial', the video console is ignored.

We should always evaluate the size of vidconsole if it is the primary
console.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Tom Rini [Sat, 6 Mar 2021 12:25:04 +0000 (07:25 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

- Convert qemu-ppce500 to driver model and enable additional driver
  support
- bug fixes/updates in net-dsa driver, vid driver, move configs to kconfig
- Update Maintainers of some powerpc, layerscape platforms

3 years agodoc: Add a reST document for qemu-ppce500
Bin Meng [Thu, 25 Feb 2021 09:22:59 +0000 (17:22 +0800)]
doc: Add a reST document for qemu-ppce500

Add a reST document to describe how to build and run U-Boot for
the QEMU ppce500 machine.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Move board directory from board/freescale to board/emulation
Bin Meng [Thu, 25 Feb 2021 09:22:58 +0000 (17:22 +0800)]
ppc: qemu: Move board directory from board/freescale to board/emulation

board/emulation is the place for other QEMU targets like x86, arm,
riscv. Let's move the qemu-ppce500 board codes there.

List me as a co-maintainer for this board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Drop fixed_sdram()
Bin Meng [Thu, 25 Feb 2021 09:22:57 +0000 (17:22 +0800)]
ppc: qemu: Drop fixed_sdram()

This function is not called anywhere. Only fsl_ddr_sdram_size() is
necessary [1] for QEMU. Drop it.

[1] arch/powerpc/cpu/mpc85xx/cpu.c::dram_init()

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Drop a custom env variable 'fdt_addr_r'
Bin Meng [Thu, 25 Feb 2021 09:22:56 +0000 (17:22 +0800)]
ppc: qemu: Drop a custom env variable 'fdt_addr_r'

Now that we have switched to CONFIG_OF_CONTROL, and we can use the
env variable 'fdtcontroladdr' directly instead of creating one that
is duplicated.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Delete the temporary FDT virtual-physical mapping after U-Boot is relocated
Bin Meng [Thu, 25 Feb 2021 09:22:55 +0000 (17:22 +0800)]
ppc: qemu: Delete the temporary FDT virtual-physical mapping after U-Boot is relocated

After U-Boot is relocated to RAM already, the previous temporary FDT
virtual-physical mapping that was used in the pre-relocation phase
is no longer needed. Let's delete the mapping.

get_fdt_virt() might be used before and after relocation, update it
to return different virtual address of FDT.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Enable RTC support via I2C
Bin Meng [Thu, 25 Feb 2021 09:22:54 +0000 (17:22 +0800)]
ppc: qemu: Enable RTC support via I2C

The QEMU ppce500 target integrates a Freescale I2C controller and
has a Pericom pt7c4338 RTC connected to it. Enable corresponding
DM drivers so that 'date' command is actually useful.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Enable support for power off via GPIO
Bin Meng [Thu, 25 Feb 2021 09:22:53 +0000 (17:22 +0800)]
ppc: qemu: Enable support for power off via GPIO

The QEMU ppce500 target provides the power off functionality via
the GPIO pin#0, and we can support this using the sysreset gpio
poweroff driver. Let's enable it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agodm: sysreset: Add a Kconfig option for the 'reset' command
Bin Meng [Thu, 25 Feb 2021 09:22:52 +0000 (17:22 +0800)]
dm: sysreset: Add a Kconfig option for the 'reset' command

sysreset uclass driver provides an implementation of 'reset'
command using the sysreset_ APIs unconditionally. It also
supports the 'poweroff' command using the sysreset_ APIs,
but under a Kconfig option CONFIG_SYSRESET_CMD_POWEROFF.

Let's do the same for the 'reset' command, by introducing a
new Kconfig option CONFIG_SYSRESET_CMD_RESET, and set it to
on by default, to allow a board that don't have a sysreset
reset driver yet, but have a sysreset poweroff driver to
compile without any issue.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Enable GPIO support
Bin Meng [Thu, 25 Feb 2021 09:22:51 +0000 (17:22 +0800)]
ppc: qemu: Enable GPIO support

QEMU ppce500 target integrates a GPIO controller that is compatible
with the QorIQ GPIO controller. Enable the DM GPIO driver for it
and the 'gpio' command.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agogpio: mpc8xxx: Support controller register physical address beyond 32-bit
Bin Meng [Thu, 25 Feb 2021 09:22:50 +0000 (17:22 +0800)]
gpio: mpc8xxx: Support controller register physical address beyond 32-bit

dev_read_addr_size_index() returns fdt_addr_t which might be a
64-bit physical address. This might be true for some 85xx SoCs
whose CCSBAR is mapped beyond 4 GiB.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: mpc85xx: Add 'gpibe' register to 'struct ccsr_gpio'
Bin Meng [Thu, 25 Feb 2021 09:22:49 +0000 (17:22 +0800)]
ppc: mpc85xx: Add 'gpibe' register to 'struct ccsr_gpio'

Without this, the DM GPIO driver for MPC8xxx does not compile for
MPC85xx SoCs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Enable VirtIO BLK support
Bin Meng [Thu, 25 Feb 2021 09:22:48 +0000 (17:22 +0800)]
ppc: qemu: Enable VirtIO BLK support

Enable VirtIO BLK driver so that we can store a kernel image to
a disk image and boot from there.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agovirtio: Fix VirtIO BLK driver dependency
Bin Meng [Thu, 25 Feb 2021 09:22:47 +0000 (17:22 +0800)]
virtio: Fix VirtIO BLK driver dependency

The VirtIO BLK driver depends on the blk uclass driver.
Add the dependency in the Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Enable VirtIO NET support
Bin Meng [Thu, 25 Feb 2021 09:22:46 +0000 (17:22 +0800)]
ppc: qemu: Enable VirtIO NET support

By default the QEMU ppce500 machine connects a VirtIO NET to the
PCI controller, although it can be replaced to an e1000 NIC via
additional command line options.

Now that we have switched over to DM PCI, VirtIO support becomes
possible. This commit enables the support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agocmd: Fix virtio command dependency
Bin Meng [Thu, 25 Feb 2021 09:22:45 +0000 (17:22 +0800)]
cmd: Fix virtio command dependency

The 'virtio' command calls blk_common_cmd() which is only available
when CONFIG_HAVE_BLOCK_DEVICE is on. Fix the Kconfig dependency.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Drop CONFIG_OF_BOARD_SETUP
Bin Meng [Thu, 25 Feb 2021 09:22:44 +0000 (17:22 +0800)]
ppc: qemu: Drop CONFIG_OF_BOARD_SETUP

ft_board_setup() is now empty. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Switch over to use DM ETH and PCI
Bin Meng [Thu, 25 Feb 2021 09:22:43 +0000 (17:22 +0800)]
ppc: qemu: Switch over to use DM ETH and PCI

At present the board supports non-DM version PCI and E1000 drivers.
Switch over to use DM ETH and PCI by:

- Rewrite the PCI address map functions using DM APIs
- Enable CONFIG_MISC_INIT_R to do the PCI initialization and
  address map
- Drop unnecessary ad-hoc config macros
- Remove board_eth_init() in the board codes

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agopci: mpc85xx: Support 64-bit bus and cpu address
Bin Meng [Thu, 25 Feb 2021 09:22:42 +0000 (17:22 +0800)]
pci: mpc85xx: Support 64-bit bus and cpu address

At present the driver only supports 32-bit bus and cpu address.
The controller's outbound registers/fields for extended address
are not programmed. Let's program them to support 64-bit bus and
cpu address.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agopci: mpc85xx: Support controller register physical address beyond 32-bit
Bin Meng [Thu, 25 Feb 2021 09:22:41 +0000 (17:22 +0800)]
pci: mpc85xx: Support controller register physical address beyond 32-bit

devfdt_get_addr_index() returns fdt_addr_t which might be a 64-bit
physical address. Use map_physmem() to return the virtual address
that can be used by a 32-bit machine.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agopci: mpc85xx: Wrap LAW programming with CONFIG_FSL_LAW
Bin Meng [Thu, 25 Feb 2021 09:22:40 +0000 (17:22 +0800)]
pci: mpc85xx: Wrap LAW programming with CONFIG_FSL_LAW

For the QEMU ppce500 machine, LAW registers are not implemented
hence CONFIG_FSL_LAW is not turned on and all LAW APIs are not
available. We should wrap all LAW registers programming in the
mpc85xx PCI driver with CONFIG_FSL_LAW.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Switch over to use DM serial
Bin Meng [Thu, 25 Feb 2021 09:22:39 +0000 (17:22 +0800)]
ppc: qemu: Switch over to use DM serial

The QEMU ppce500 target integrates 2 NS16550 serial ports. Switch
over to use the DM version of the driver by:

- drop unnecessary ad-hoc config macros
- add get_serial_clock() in the board codes

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agocommon: Move initr_addr_map() to a bit earlier
Bin Meng [Thu, 25 Feb 2021 09:22:38 +0000 (17:22 +0800)]
common: Move initr_addr_map() to a bit earlier

At present initr_addr_map() is put at a late stage in the
init_sequence_r[] calls. This won't work because lot of
device driver initialization (e.g.: serial port) happens
before it but is lack of the address translation support.

This moves the call to a bit earlier, right after the DM
initialization.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: io.h: Use addrmap_ translation APIs only in post-relocation phase
Bin Meng [Thu, 25 Feb 2021 09:22:37 +0000 (17:22 +0800)]
ppc: io.h: Use addrmap_ translation APIs only in post-relocation phase

In phys_to_virt() and virt_to_phys(), if CONFIG_ADDR_MAP is defined,
they use addrmap_ translation APIs to do the address translation.
However these APIs only work in post-relocation phase.

Update the code logic to fall back to use the default one when in
pre-relocation phase.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agolib: kconfig: Mention CONFIG_ADDR_MAP limitation in the help
Bin Meng [Thu, 25 Feb 2021 09:22:36 +0000 (17:22 +0800)]
lib: kconfig: Mention CONFIG_ADDR_MAP limitation in the help

Mention that CONFIG_ADDR_MAP only works in the post-relocation phase.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agotest: cmd: Add a basic test for 'addrmap' command
Bin Meng [Thu, 25 Feb 2021 09:22:35 +0000 (17:22 +0800)]
test: cmd: Add a basic test for 'addrmap' command

This adds a basic test for the newly introduced 'addrmap' command.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[Rebase]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agocmd: Add a command to display the address map
Bin Meng [Thu, 25 Feb 2021 09:22:34 +0000 (17:22 +0800)]
cmd: Add a command to display the address map

This adds a new command 'addrmap' to display the address map for
non-identity virtual-physical memory mappings.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agolib: addr_map: Move address_map[] type to the header file
Bin Meng [Thu, 25 Feb 2021 09:22:33 +0000 (17:22 +0800)]
lib: addr_map: Move address_map[] type to the header file

At present address_map[] is static and its type is unknown to external
modules. In preparation to create a command to list its contents, this
patch moves its type definition and declaration to the header file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoinclude: Remove extern from addr_map.h
Bin Meng [Thu, 25 Feb 2021 09:22:32 +0000 (17:22 +0800)]
include: Remove extern from addr_map.h

Remove the extern of the header because they are useless.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Enable driver model
Bin Meng [Thu, 25 Feb 2021 09:22:31 +0000 (17:22 +0800)]
ppc: qemu: Enable driver model

At present QEMU ppce500 target has not been migrated to driver model
yet. As a start, let's enable driver model and the 'dm' command.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Enable OF_CONTROL
Bin Meng [Thu, 25 Feb 2021 09:22:30 +0000 (17:22 +0800)]
ppc: qemu: Enable OF_CONTROL

The QEMU ppce500 machine generates a device tree blob and passes
it to U-Boot during boot. Let's enable OF_CONTROL with OF_BOARD
and provide board_fdt_blob_setup() in the board codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Drop board_early_init_f()
Bin Meng [Thu, 25 Feb 2021 09:22:29 +0000 (17:22 +0800)]
ppc: qemu: Drop board_early_init_f()

This function does nothing. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Drop init_laws() and print_laws()
Bin Meng [Thu, 25 Feb 2021 09:22:28 +0000 (17:22 +0800)]
ppc: qemu: Drop init_laws() and print_laws()

These are no longer needed. Drop them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: mpc85xx: Wrap LAW related codes with CONFIG_FSL_LAW
Bin Meng [Thu, 25 Feb 2021 09:22:27 +0000 (17:22 +0800)]
ppc: mpc85xx: Wrap LAW related codes with CONFIG_FSL_LAW

LAW related codes should be wrapped with CONFIG_FSL_LAW.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Fix CONFIG_SYS_PCI_MAP_END
Bin Meng [Thu, 25 Feb 2021 09:22:26 +0000 (17:22 +0800)]
ppc: qemu: Fix CONFIG_SYS_PCI_MAP_END

CONFIG_SYS_PCI_MAP_END currently points to 0xe8000000, which means
the upper end of the virtual address mapped to PCI bus address ends
at 0xe8000000. But this is wrong as the CCSBAR was already mapped
at 0xe0000000 with a 1 MiB size.

Fixes: fa08d3951777 ("PPC 85xx: Add qemu-ppce500 machine")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Support non-identity PCI bus address
Bin Meng [Thu, 25 Feb 2021 09:22:25 +0000 (17:22 +0800)]
ppc: qemu: Support non-identity PCI bus address

When QEMU originally supported the ppce500 machine back in Jan 2014,
it was created with a 1:1 mapping of PCI bus address. Things seemed
to change rapidly that in Nov 2014 with the following QEMU commits:

commit e6b4e5f4795b ("PPC: e500: Move CCSR and MMIO space to upper end of address space")

and

commit cb3778a0455a ("PPC: e500 pci host: Add support for ATMUs")

the PCI memory and IO physical address were moved to beyond 4 GiB,
but PCI bus address remained below 4 GiB, hence a non-identity
mapping was created. Unfortunately corresponding U-Boot updates
were missed along with the QEMU changes and the U-Boot QEMU ppce500
PCI support has been broken since then.

This commit makes the PCI (non-DM version) work again.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agocommon: fdt_support: Support special case of PCI address in fdt_read_prop()
Bin Meng [Thu, 25 Feb 2021 09:22:24 +0000 (17:22 +0800)]
common: fdt_support: Support special case of PCI address in fdt_read_prop()

At present fdt_read_prop() can only handle 1 or 2 cells. It is
called by fdt_read_range() which may be used to read PCI address
from <ranges> for a PCI bus node where the number of PCI address
cell is 3. The <ranges> property is an array of:

  { <child address> <parent address> <size in child address space> }

When trying to read <child address> from a PCI bus node using
fdt_read_prop(), as the codes below:

    /* Read <child address> */
    if (child_addr) {
        r = fdt_read_prop(ranges, ranges_len, cell, child_addr,
                          acells);
        if (r)
            return r;
    }

it will fail, because the PCI child address is made up of 3 cells
but fdt_read_prop() cannot handle it. We advance the cell offset
by 1 so that the <child address> can be correctly read.

This adds the special handling of such case.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoppc: qemu: Update MAINTAINERS for correct email address
Bin Meng [Thu, 25 Feb 2021 09:22:23 +0000 (17:22 +0800)]
ppc: qemu: Update MAINTAINERS for correct email address

Alex's previous email address is no longer reachable.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agopci: fsl_pci_init: Dynamically allocate the PCI regions
Bin Meng [Thu, 25 Feb 2021 09:22:22 +0000 (17:22 +0800)]
pci: fsl_pci_init: Dynamically allocate the PCI regions

Commit e002474158d1 ("pci: pci-uclass: Dynamically allocate the PCI regions")
changes 'struct pci_controller'.regions from pre-allocated array of
regions to dynamically allocated, which unfortunately broken lots of
boards that still use the non-DM PCI driver.

This patch changes the non-DM fsl_pci_init driver to dynamically
allocate the regions, just like what's done in the pci uclass driver.

Fixes: e002474158d1 ("pci: pci-uclass: Dynamically allocate the PCI regions")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agonet: dsa: remove master santiy check
Michael Walle [Wed, 24 Feb 2021 16:40:42 +0000 (17:40 +0100)]
net: dsa: remove master santiy check

Because we probe the master ourselves (and fail if there is no master),
it is not possible that we don't have a master device.

There is one catch though: device removal. We don't support that. It
wasn't supported neither before this patch. Because the master device
was only set in .pre_probe(), if a device was removed master_dev was a
dangling pointer and transmitting a frame cause a panic. I don't see a
good solution without having some sort of notify machanism when a
udevice is removed.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Michael Walle <michael@walle.cc> [DSA unit tests]
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agonet: dsa: remove NULL check for priv and platform data
Michael Walle [Wed, 24 Feb 2021 16:40:41 +0000 (17:40 +0100)]
net: dsa: remove NULL check for priv and platform data

Because the uclass has the "*_auto" properties set, the driver model
will take care of allocating the private structures for us and they
can't be NULL. Drop the checks.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agonet: dsa: probe master device
Michael Walle [Wed, 24 Feb 2021 16:40:40 +0000 (17:40 +0100)]
net: dsa: probe master device

DSA needs to have the master device probed first for MAC inheritance.
Until now, it only works by chance because the only user (LS1028A SoC)
will probe the master device first. The probe order is given by the PCI
device ordering, thus it works because the master device has a "smaller"
BDF then the switch device.

Explicitly probe the master device in dsa_port_probe().

Fixes: fc054d563bfb ("net: Introduce DSA class for Ethernet switches")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agonet: dsa: return early if there is no master
Michael Walle [Wed, 24 Feb 2021 16:40:39 +0000 (17:40 +0100)]
net: dsa: return early if there is no master

It doesn't make sense to have DSA without a master port. Error out early
if there is no master port.

Fixes: fc054d563bfb ("net: Introduce DSA class for Ethernet switches")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: ls1012aqds: Update MAINTAINERS
Priyanka Jain [Fri, 19 Feb 2021 12:20:23 +0000 (17:50 +0530)]
board: ls1012aqds: Update MAINTAINERS

Update LS1012AQDS Board MAINTAINERS entries to
current MAINTAINERS.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: lx2160a: Update MAINTAINERS
Priyanka Jain [Fri, 19 Feb 2021 12:20:22 +0000 (17:50 +0530)]
board: lx2160a: Update MAINTAINERS

Update LX2160AQDS BOARD MAINTAINER entry to
current MAINTAINER.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: ls1046ardb: Update MAINTAINERS
Priyanka Jain [Fri, 19 Feb 2021 12:20:21 +0000 (17:50 +0530)]
board: ls1046ardb: Update MAINTAINERS

Update LS1046ARDB BOARD MAINTAINERS entries to
current MAINTAINERS.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: ls1046aqds: Update MAINTAINERS
Priyanka Jain [Fri, 19 Feb 2021 12:20:20 +0000 (17:50 +0530)]
board: ls1046aqds: Update MAINTAINERS

Update LS1046AQDS BOARD MAINTAINERS entries to
current MAINTAINERS.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: ls2080ardb: Update MAINTAINERS
Priyanka Jain [Fri, 19 Feb 2021 12:20:19 +0000 (17:50 +0530)]
board: ls2080ardb: Update MAINTAINERS

Update LS2080ARDB BOARD MAINTAINERS entries to
current MAINTAINERS.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: ls2080aqds: Update MAINTAINERS
Priyanka Jain [Fri, 19 Feb 2021 12:20:18 +0000 (17:50 +0530)]
board: ls2080aqds: Update MAINTAINERS

Update LS2080AQDS BOARD MAINTAINERS entries to
current MAINTAINERS.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: ls1088a: Update MAINTAINERS
Priyanka Jain [Fri, 19 Feb 2021 12:20:17 +0000 (17:50 +0530)]
board: ls1088a: Update MAINTAINERS

Update LS1088ARDB, LS1088AQDS BOARD MAINTAINERS
entries to current MAINTAINERS.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: ls1043ardb: Update MAINTAINERS
Priyanka Jain [Fri, 19 Feb 2021 12:20:16 +0000 (17:50 +0530)]
board: ls1043ardb: Update MAINTAINERS

Update LS1043ARDB BOARD MAINTAINERS entries
to current MAINTAINERS.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: ls1028a: Update MAINTAINERS
Priyanka Jain [Fri, 19 Feb 2021 12:20:15 +0000 (17:50 +0530)]
board: ls1028a: Update MAINTAINERS

Update LS1028AQDS, LS10128ARDB board MAINTAINERS
entries to current MAINTAINERS.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: ls1021atwr: Update MAINTAINERS
Priyanka Jain [Fri, 19 Feb 2021 12:20:14 +0000 (17:50 +0530)]
board: ls1021atwr: Update MAINTAINERS

Update LS1021ATWR BOARD MAINTAINERS entries to
current MAINTAINERS.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: ls1021aiot: Update MAINTAINERS
Priyanka Jain [Fri, 19 Feb 2021 12:20:13 +0000 (17:50 +0530)]
board: ls1021aiot: Update MAINTAINERS

Update LS1021AIOT BOARD MAINTAINERS entries to
current MAINTAINERS.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: ls1012ardb: Update MAINTAINERS
Priyanka Jain [Fri, 19 Feb 2021 12:20:12 +0000 (17:50 +0530)]
board: ls1012ardb: Update MAINTAINERS

Update LS1012ARDB BOARD MAINTAINERS entries
to current MAINTAINERS.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: ls1012afrdm: Update MAINTAINERS
Priyanka Jain [Fri, 19 Feb 2021 12:20:11 +0000 (17:50 +0530)]
board: ls1012afrdm: Update MAINTAINERS

Update LS1012AFRWY BOARD MAINTAINER entry
to current MAINTAINER.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: corenet_ds: MAINTAINERS: Remove redundant entries
Priyanka Jain [Fri, 19 Feb 2021 12:20:10 +0000 (17:50 +0530)]
board: corenet_ds: MAINTAINERS: Remove redundant entries

Remove MAINTAINERS entries for
P3041DS_NAND_SECURE_BOOT_defconfig
and P5040DS_NAND_SECURE_BOOT_defconfig
as these configs support have been removed.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoconfigs: fsl: move via specific defines to Kconfig
Rajesh Bhagat [Mon, 15 Feb 2021 08:46:14 +0000 (09:46 +0100)]
configs: fsl: move via specific defines to Kconfig

Moves below via specific defines to Kconfig:

CONFIG_FSL_VIA

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoconfigs: fsl: move bootrom specific defines to Kconfig
Rajesh Bhagat [Thu, 11 Feb 2021 12:28:49 +0000 (13:28 +0100)]
configs: fsl: move bootrom specific defines to Kconfig

Moves below bootrom specific defines to Kconfig:

    CONFIG_SYS_FSL_BOOTROM_BASE
    CONFIG_SYS_FSL_BOOTROM_SIZE

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoarm: fsl: common: Improve NXP VID driver PMBus support
Stephen Carlson [Mon, 8 Feb 2021 10:11:29 +0000 (11:11 +0100)]
arm: fsl: common: Improve NXP VID driver PMBus support

This patch adds support for more PMBus compatible devices to the NXP
drivers for its QorIQ family devices. At runtime, the voltage regulator is
queried over I2C, and the required voltage multiplier determined. This
change supports the DIRECT and LINEAR PMBus voltage reporting modes.

Previously, the driver only supported a few specific devices such as the
IR36021 and LTC3882, so this change allows the QorIQ series to be used
with a much larger variety of core voltage regulator devices.

checkpatch warning "Use if (IS_DEFINED (...))" was ignored to maintain
consistency with the existing code.

Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com>
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Tested-by: Wasim Khan <wasim.khan@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoAzure/GitLab: Use buildman -T0 for binman, etc, test
Tom Rini [Thu, 4 Mar 2021 21:59:00 +0000 (16:59 -0500)]
Azure/GitLab: Use buildman -T0 for binman, etc, test

There are times where buildman seems to get stuck in this job when in
CI.  Forcing single-threaded here allows us to complete and move on.

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agobuildman: Support single-threaded operation
Simon Glass [Sun, 31 Jan 2021 05:17:46 +0000 (22:17 -0700)]
buildman: Support single-threaded operation

At present even if only a single thread is in use, buildman still uses
threading.

For some debugging it is helpful to do everything in the main process.
Allow -T0 to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agoNokia RX-51: Enable CONFIG_CMD_BOOTD
Pali Rohár [Wed, 24 Feb 2021 00:27:29 +0000 (01:27 +0100)]
Nokia RX-51: Enable CONFIG_CMD_BOOTD

CONFIG_CMD_BOOTD provides 'boot' command which is required in more scripts.

Signed-off-by: Pali Rohár <pali@kernel.org>
3 years agofs/squashfs: Fix compilation error
Pali Rohár [Wed, 3 Mar 2021 09:52:36 +0000 (10:52 +0100)]
fs/squashfs: Fix compilation error

Commit 401d1c4f5d2d29c4bc4beaec95402ca23eb63295 ("common: Drop
asm/global_data.h from common header") broke compilation of squashfs
filesystem when CONFIG_CMD_SQUASHFS=y is enabled.

Compilation is failing on error:

    aarch64-linux-gnu-ld.bfd: u-boot/fs/squashfs/sqfs_inode.c:121: undefined reference to `le32_to_cpu'

Fixes: 401d1c4f5d2d29c4bc4beaec95402ca23eb63295 ("common: Drop asm/global_data.h from common header")
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
3 years agoMerge tag 'dm-pull-3mar21' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm
Tom Rini [Thu, 4 Mar 2021 03:53:53 +0000 (22:53 -0500)]
Merge tag 'dm-pull-3mar21' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

dm: Fix an obscure bug with empty of-platdata
Fixes for ns16550 base address and frequency-reading
Other minor fixes

3 years agoserial: ns16550: Handle zero <clock-frequency> value
Bin Meng [Wed, 3 Feb 2021 14:42:25 +0000 (22:42 +0800)]
serial: ns16550: Handle zero <clock-frequency> value

A working device tree node of ns16550 should never be populated
with value zero for the <clock-frequency> property. Unfortunately
this is the case for the QEMU ppce500 target.

Let's try to assign plat->clock to CONFIG_SYS_NS16550_CLK as the
last resort to handle such case.

This commit should be reverted when:

- The following QEMU patch [1] is merged, and
- U-Boot CI has upgraded its QEMU version that contains the fix

[1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1612362288-22216-2-git-send-email-bmeng.cn@gmail.com/

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoserial: ns16550: Correct the base address type
Bin Meng [Wed, 3 Feb 2021 13:22:40 +0000 (21:22 +0800)]
serial: ns16550: Correct the base address type

Currently ns16550_serial_assign_base() treats the argument 'base'
with type `ulong`. This is incorrect because the base address was
obtained from device tree with type `fdt_addr_t` that can represent
a physical address larger than 32-bit in a 32-bit system.

Fixes: 9e6ce62190b7 ("serial: ns16550: Fix ordering of getting base address")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>